Dynamic Analysis, Stability and Design of Grid Forming Converters With PI-Based Voltage Control in DC and 3-Phase AC Microgrids

This article analyzes the dynamic behavior of the voltage control loop based on proportional-integral regulators, commonly used for grid-forming converters in 3-phase AC and DC Microgrids and applications that involve a DC-link voltage control. The article proposes a simple and accurate generalized analysis useful both for the system characterization and design. Two different control schemes, based on linear (Direct Voltage Control, DVC) and quadratic voltage feedback (Quadratic Voltage Control, QVC), are analytically studied, simulated and experimentally tested, demonstrating a superior performance of the QVC under the presence of constant power loads. The operation limits, the system stability and the disturbance rejection capability are analyzed considering the effect of control and plant parameters and the effect of the different types of disturbances and the operating point, taking into account the non-linearities of the system. The analysis is mainly focused on the effect of constant power loads given their negative impact on the system performance. The study provides a generic procedure for the analysis and design of proportional-integral voltage controllers, including the selection of the system capacitance for meeting specific dynamic specifications while considering system characteristics as the load level, the stability margins and the maximum voltage deviation under disturbances.


I. INTRODUCTION
T HE increasing need for the integration of renewable ener- gies and Distributed Generation (DG) in the grid have led to the concept of Microgrid (MG).Considering the high presence of electronic loads, DGs interfaced by Power Electronic Converters (PECs) and the significant penetration of renewable generation ruled under maximum power point tracking, grid control based on leader-follower can simplify the MG design and operation [1], [2], [3].In both cases, AC or DC, this approach requires a grid-forming converter controlling the voltage magnitude in DC MGs and voltage amplitude and frequency in AC MGs, usually using a feedback control based on Proportional-Integral (PI) regulators [4], [5], [6].The high presence of tightly regulated Constant Power Loads (CPLs) contributes negatively to the low inertia and pose a challenge for grid-forming controller, affecting its dynamic control [7].The dynamic and stability issues related to the non-linearity that CPLs introduce in voltage control schemes based on PI regulators, have been already addressed in the literature [2], [8], [9], [10], [11], [12], [13] and is still a matter of concern [14], [15], [16].Hardware (increasing capacitance or resistive loads) and control solutions (linear and boundary controllers or virtual impedance) have been proposed to reduce the effect of CPLs [17], [18], [19], [20].Nonetheless, the dynamics, stability limitations and selection of both the passive elements are still a challenging task and depends on the application.
The conventional implementation of PI-based grid-forming is based on the linear relationship between the voltage and the current at the capacitor [21].Hereinafter this method will be referred as Direct Voltage Control (DVC).Despite its apparent simplicity, achieving good dynamic behavior is not straightforward, as already reported in the literature [22].This is due to the non-linear behavior of the voltage reaction to both CPLs and Constant Impedance Loads (CILs) disturbances.
An alternative feedback control strategy has been proposed in the literature referred as fast-acting DC-link voltage controller or energy based controller, that here in after will be referred as quadratic voltage control (QVC) [22], [23], [24], [25].This controller uses the capacitor energy storage capability as an approach to linearize the relation between the voltage and the power at the capacitor plant using a quadratic voltage feedback.This controller has become widely used for the voltage control of the DC-links [26], [27], [28].Nonetheless, its application can be generalized to any cascaded-based voltage control, such as grid-forming converters in both DC and 3-phase AC MGs.However, those techniques have not been further exploited for those applications and few examples are found on the analysis of the dynamic performance and tuning [22], [28], [29], [30].In [29] the QVC approach is combined with a droop control in a DC MG.However, the performance under presence of CPLs is not evaluated and the tuning of the PI parameters is not deeply discussed.In [30] the QVC is applied in the interlinking converter of a hybrid MG operated as a DC grid-forming.Nonetheless, the study is not focus on the operation and benefits of this controller and, as in the previous study, its dynamic behavior and stability analysis under CPLs, as well as the discussion on the selection of the capacitance and the regulator parameters, are not provided.Although the QVC has been applied for DC regulation applications, to the authors knowledge, no records of this alternative are found for AC applications apart from [31].Regarding the dynamic stiffness of grid-forming converters, in some cases the PI regulator might not be enough to ensure proper disturbance rejection and transient voltage quality, especially under CPLs.The literature has revealed that the effects of CPLs can be attenuated by increasing the system capacitance or the resistive loads and reducing the CPLs or the system inductance [7].This can reduce the voltage oscillations and increase the stability margins.However, unlike the controller parameters, the modification of the system hardware is restricted.Alternatively, the dynamic performance can be enhanced through control methods as linear Proportional Derivative (PD) or boundary controllers [7], or by load decoupling, using measurements, observers or estimators [32], [33].Methods adapted from the virtual inertia concept are also an appealing simple solution [34], [35], [36].
This article analyzes the dynamic behavior of the voltage control loop used in grid-forming converters for 3-phase AC and DC applications, considering cascaded voltage-current control scheme.The aims of this article are: r Define small signal linearized and normalized equivalent models of DVC and QVC to fairly compare both approaches under different type of loads, focusing on CPLs.The superior performance of QVC under CPL is demonstrated.
r Define analytical solutions for determining the dependence of system damping, stability limits and disturbance rejection depending on the penetration of the different types of load.
r Evaluate the effect of capacitance, virtual capacitance, inner current control loop, damping and bandwidth in the disturbance rejection.
r Provide methods to define system damping depending on the load levels as well as procedures to select the capacitor value or the bandwidth depending on the maximum allowed transient voltage deviation and the maximum expected CPL step.The proposed models and methods are evaluated both by simulations and experimentally.
This article continues the study presented in [35].The article is organized as follows.Section II presents the system plant.Section III models the PI-based voltage controllers.Section IV analyzes the system behavior under disturbances and define the stability criteria.Section V discusses the effect of the capacitor.Section VI establishes the basics for a generalized analysis and design of the system based on its dynamic response.Section VII discusses the effect of the inner control loop.Section VIII presents the experimental results.Finally, Section IX summarizes the conclusions.

II. PROBLEM DEFINITION AND SYSTEM MODELING
In most of the MG applications requiring a voltage regulation, the system plant to be controlled consists in a capacitor whose voltage derivative is proportional to its current.It is worth to point out that the following discussion assumes a DC system or an AC system modeled in the synchronous reference frame as done in [31].An AC system in the dq reference frame can be considered as two independent DC systems for each of the d and q axis.Thus, the modeling and analysis will consider a DC system, while the 3-phase AC model will consider the proposal in [31].The control in this kind of applications is usually performed by a closed-loop cascaded controller consisting of an inner current/power control loop and an outer voltage control loop.Assuming the inner current/power control loop is fast enough, its dynamics can be neglected.In Fig. 1, the voltage control can be assumed as a voltage regulator, which input is the error, e, between the voltage reference, v * , and the measured voltage, ṽ, while the control action is the current, i, entering the system plant.Considering load disturbances, the system plant can be defined by (1), where C is the system plant total capacitance, v(t) is the capacitor voltage, i(t) is the control action of the voltage control loop, and i g (t) is the load disturbance.
Nevertheless, Constant Current Loads (CCLs) are not the only kind of loads found in power systems.More and more electrical appliances and industrial equipment behaves as CPLs, characterized by a tight control of load power, or as conventional CILs, presenting both of them a non-linear relation between power, voltage and current.Thus, the system in (1) must be reformulated as the non-linear system in (2), where i L , P L and g L are the current, power and conductance disturbances associated to CCLs, CPLs, and CILs respectively.
Some assumptions are established regarding this expression: 1) Only pure resistive CIL are considered modeled as conductances, g(t) in (2); 2) Generation is considered by negative signs in P L and i L ; 3) The effect of line impedance is out of the scope of this article and, thus, it is neglected in this analysis.Therefore, the system load seen by the grid-forming converter is considered as an aggregated current i g .Fig. 2 shows the single phase representation of the defined non-linear system.The behavior of the different loads existing  in a MG are illustrated in Fig. 3 where I n and V n indicate the load nominal current and voltage and I max and V max are the load maximum point of operation.The non-linearities due to CPL and CIL will affect the voltage regulation design and performance.Moreover, unlike CILs, it is well known that CPLs are prone to compromise the system stability.In the literature, several attempts have been carried out for obtaining a linear approximation by defining a negative impedance [1], [7], [10], [11].In this article, the effect of non-linear loads is approached by the linearization of the close loop system.
Before proceeding with the system analysis, it is worth to point out the assumptions and limitations of the analysis proposed in this article: 1) as in any linearized model, the dynamic model accuracy is guaranteed only near the equilibrium point, 2) the scope of this study is only valid for low and negligible line impedance, 3) the feedback sensor effect is neglected, assuming its dynamic response is much faster and delay much lower than the voltage control loop time constant (ṽ = v), 4) the inner current control loop (current controller, PEC topology, filter) is initially consider as ideal, assuming a bandwidth much higher than the one of voltage control (i ≈ i * ).In order to establish the criteria to neglect the sensor effect and the inner current control loop, their effect is analyzed in Section III-D.

III. THE VOLTAGE CONTROLLER: PI-BASED CONTROL TOPOLOGIES AND MODELING
The voltage controller models will be analyzed using linearized models.Two control schemes, shown in Fig. 4, are considered for the implementation of the outer voltage control loop in a grid-forming unit, the DVC and the QVC.

A. The Direct Voltage Controller (DVC)
The DVC control scheme is shown in Fig. 4(a)).A PI regulator in the standard form has been selected for the analysis, defined by (3), where i * is the control action, v * the voltage reference, v the actual voltage, and k p and T i are the PI proportional gain and integral time constant respectively.This controller is based on the linear relationship between the voltage and the current at the system plant capacitor.
Considering an ideal inner control loop (i = i * ), the voltage closed-loop system when using DVC is defined by (4).This expression will be used as the starting point for the dynamic analysis of the DVC-based voltage control.
Despite its apparent simplicity, achieving good dynamic behavior is not straightforward, as already reported in the literature [22].This is due to the non-linear behavior of the voltage reaction to both CPLs and CILs disturbances as evidenced in (4).Nonetheless, if the disturbances are left apart, its reference tracking response is linear, defined by the Laplace domain transfer function (5).

B. The Quadratic Voltage Controller (QVC)
An alternative to the DVC has been proposed in the literature referred as fast-acting DC-link voltage controller and energy based controller, in the context of applications for the DC-link control of DC/DC/AC and AC/DC/AC converters [22], [23], [24], [25].As a contribution of this article, its generalization to any cascaded-based voltage control, such as grid-forming converters in both DC and 3-phase AC MGs applications is proposed.The control scheme is shown in Fig. 4(b)) and the regulator differential equation is given by ( 6).The closed-loop system using QVC is defined by (7).As in the case of DVC, that expression will be used as the starting point for the dynamic analysis of the QVC-based voltage control.
The control is based on the linear relation between the power flowing into the capacitor, and the instantaneous voltage squared.In [22], [24], its design is realized by exploiting the relation between voltage variations and the energy stored in the capacitor.However, the tuning method used in those papers is oriented to the regulation of the DC-link of an active front end (AFE) exposed to the steady state disturbances produced by AC grid unbalances.Here, a general approach based on disturbance rejection analysis is included, considering a meaningful comparison between DVC and QVC dynamic response.
One of the main advantages of QVC, concerning the disturbance rejection and stability analysis, is that the relation between v 2 (t) and P L (t) becomes linear (8), unlike in the case of DVC.This fact could simplify the delimitation of the stable region in case of considering only CPLs.
) However, the controlled variable is still v(t) and considering CIL and CCL disturbances, being necessary the system linearization to perform a proper dynamic analysis.
Leaving the disturbances aside, unlike in the DVC, in the QVC the relation between v and v * is non-linear, (6).The system defined in (7) has been linearized using the Taylor series approach.The linear approximation of the reference tracking transfer function is obtained as in (9), where V * 0 and V 0 are the voltage reference and the actual voltage at the equilibrium point, respectively.Assuming V 0 ≈ V * 0 , the transfer function is approximated by (10).

C. Establishing an Analytical Tuning Methodology
An analytical tuning methodology will be used to establish a parametric design of the regulator gains [2].This will allow a proper an generalized comparison between the DVC and QVC, independent of the numeric value of the regulator gains.The close loop system can be simplified to a second order system with natural frequency ω n and damping factor ζ. Equations ( 5) and (10), can be expressed as (11).Thus, the PI regulator gains for DVC and QVC are tuned according to ( 12) and ( 13) respectively.Fig. 5 shows an example of the reference tracking response, comparing the two methods when using ω n = 2π50 and ζ = 0.7 in both of them.

D. Effect of the Inner Controller, Delays and Sensor
The inner current controller, PEC and sensor shown in Fig. 1 can condition the response given by the voltage controller.This section analyses the effect of those elements to determine the extent to which, considering them ideal, affects the voltage control loop.The linearized system in (11) becomes (14) where G i (s) and G fb (s) are the inner current control loop and the sensor transfer function respectively.
The inner current control can be modeled as a second order filter defined by (15).This transfer function considers a simplified model of the subsystem composed by the current controller, the power converter and the inductive coupling filter, where ω n i and ζ i are the current control loop natural frequency and damping factor respectively.Fig. 6 shows the frequency response for different ω n i /ω n ratios both in open loop, (16), and closed loop, using ω n = 2π50 and ζ = 1 and G fb = 1.Ratios equal and above 10 allow Gain Margins (GM) over 16 dB, Phase Margins (PM) above 60 • and Delay Margins (DM) over 1.6 ms.In closed loop, the effect is shown above frequencies over ω n , and the magnitude is close to ideal response for ratios above 5.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.The sensor transfer function is modeled as pure delay and a 2 nd order Low Pass Filter (LPF) with ζ s = 0.7 as (17).When using digital controllers, the pure delay is usually associated to the sampling time and the LPF represent an anti-aliasing filter, neglecting the non-dominant poles of the voltage sensor in this kind of applications.Fig. 7 shows in a) the closed loop effect of different pure delays and in b) the effect when including the LPF with cutoff frequencies ω n s = 2π / 2τ d (2 times lower than the sampling frequency in case τ d equals the sampling time).It is shown that the effect of the LPF is dominant but in any case G fb is fairly negligible for delays below 500 μs Anti-aliasing filter (17) Given the results, the sensor effect is neglected in the rest of the document while the current control effect will be further analyzed in Section VII.

IV. CLOSED LOOP DISTURBANCE REJECTION ANALYSIS
The main requirement of a grid-forming converter is a stiff voltage control under disturbances.As seen previously, the QVC presents a non-linear response for any case, while the DVC is linear only if CCL are taken into account.However, it is worth noting that the disturbance rejection of the system when using DVC becomes non-linear with CPLs or CILs.To analyze the system behavior under disturbances, the disturbance rejection transfer functions (load disturbance to output voltage) under different type of loads have been obtained by Taylor series linearization.The linearized transfer functions ΔV (s) ΔP L (s) , ΔV (s) and ΔV (s) ΔG L (s) in the Laplace domain are shown respectively in (18) for the DVC, and in (19) for the QVC.It is necessary to point out that an operation close to the equilibrium point is assumed, considering equal the voltage reference and the voltage at the equilibrium point (V 0 = V * 0 ).
In these equations, the equilibrium point is defined by x 0 = [V 0 , P L0 , G L0 ] for DVC and x 0 = [V 0 , I L0 , G L0 ] for QVC.V 0 is the steady state voltage at the equilibrium point.P L0 , G L0 and I L0 are the load level at the equilibrium point in terms of power associated to CPLs, conductance given by CILs and current drawn by CCLs at the equilibrium point.This evince a clear dependence of the dynamic response on the load level at the equilibrium point, affecting the steady state consumption and generation to the system dynamic performance, that can lead to an unexpected behavior.As CPLs represent the most critical type of loads at the present time, special attention will be given to the CPL disturbance rejection transfer functions.The following analysis will mainly focus on the first expressions in (18) and (19).

A. Normalization and Validation of the CPL Disturbance Rejection Transfer Function
Using ( 12) and ( 13) in ( 18) and ( 19), they can be expressed in terms of ω n and ζ as ( 20) and ( 21) for DVC and QVC respectively, leading to similar expressions.
By defining factors for representing the terms related to load level at the equilibrium point, a general expression valid for both DVC and QVC is formulated as (22).
Where the close loop gain can be defined as K = 1 V 0 C , while α 0 and β 0 are normalized factors that represents the effect of the load level, being defined by the expressions in Table I for the different controllers.From (22), it is expected an identical response in absolute value for systems with different V n or C as far as the product V 0 C remains constant.
Furthermore, (22) can be normalized to per-unit (p.u.) by modifying the variable K as shown in K pu (23), leading to the full normalize expression in (24), where V n and P n are the converter nominal voltage and power respectively.
where ΔV pu = ΔV V n and ΔP Lpu = ΔP L P n .From (24), it is expected an identical response in p.u. for systems with different V n or C as far as the term V 2 0 C remains constant.To verify the linearized models, the response of ΔV (s) ΔP L (s) and (s) is compared in Figs. 8 and 9 with the simulation of the non-linear system obtained in Matlab/Simulink, for DVC and QVC respectively.The results have been obtained for 2 example scenarios with different V n and C, maintaining the term V 2 0 C constant.The parameters are listed in Table II.

TABLE II ANALYTICAL AND SIMULATION PARAMETERS
The error between the actual response and the linear approximation validates the linear models near the equilibrium point.However, in the case of DVC, when the load level P L0 is not considered, the linear model considerably deviates from the actual response as the system deviates from the equilibrium point.It is also clear, how the p.u. response remains the same for the two scenarios, validating the ( 22) and (24).
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

B. Effect of the Load Levels in the System Stability
To analyze the effect of the load level at the equilibrium point, the system root-contour for the factors associated to the load level at the equilibrium point, α 0 and β 0 , have been obtained for studying the stability limitations imposed by the load level.The root-contour expression can be generalized into a single equation for DVC and QVC by using the terms α 0 and β 0 defined in Table I.The resulting equation is (25).
This expression leads to the theoretical stability condition in (26), being the system stable whereas the condition is met.
Fig. 10 shows the system root-contour for the (α 0 + β 0 ) term and the Bode diagram of the closed loop disturbance rejection in (22) ( ΔV ΔP L ) with K = 1 and ω n = 2π50rad/s.From Fig. 10, it is clear how the system damping is increased as α 0 + β 0 increases, while it tends to instability as α 0 + β 0 decreases, reaching the expected stability limit.In the DVC topology, α 0 will present negative sign under CPL (i.e. if P L0 is positive).As commented before, in case β 0 ( G L0 C ) is not high enough to cancel the effect of α 0 ( −P L0 V 2 0 C ), the system poles will move to the right as P L0 increases.For the QVC approach, P L0 term does not contribute to the system instability, which is one of the main advantages of this method over the widely used DVC.It is worth to point out that such an advantage has not been reported yet in the literature.Nonetheless, a dependency on CCLs appears in the QVC, represented by the load level I L0 (α 0 = I L0 V 0 C )).Although positive load currents, I L0 ≥ 0, does not present stability problems, a potential issue appears when I L0 < 0, i.e. when constant current     II.generation (CCG) is considered.G L0 appears in both methods and has a positive impact in the system damping for both DVC and QVC.However, if G L0 < 0, i.e., when some equipment in the grid behaves as a negative resistor, like a generator operating in voltage/current droop mode, the system response can be also worsen until instability.An example of the stability limits for the scenario 1 defined in Table II is summarized in Table III.
For the same system, the time domain responses of DVC and QVC for a 2% CPL step (1 kW) are shown in Fig. 11 for different load levels.It is clear how the system tends to oscillate as the conditions in Table III are approached.Conversely, when the load levels move away from the stability limit, the system damping is improved.
The effect of P L0 in the time domain response is illustrated in Fig. 12, where the behavior of DVC and QVC methods are compared under CPL increasing steps, from P L (t) = 0 to P L (t) = 2.6 kW (near the stability limit).As expected, unlike  II.
in the QVC, for the same load step, the response in the DVC method is altered for the worse at higher load levels.

C. Voltage Collapse
The voltage level also represents a potential cause of instability as it deviates from the equilibrium point.The voltage collapse for both controllers is represented in Fig. 13 for a step CPL disturbance.As it is shown, the QVC is not only independent of the CPL load level at the point, P L0 , but also withstands higher CPL step disturbances before it collapses.This effect will be further explored in Section VI-A.

V. EFFECT OF SYSTEM CAPACITOR AND THE USE OF VIRTUAL CAPACITANCE
The capacitor and controller bandwidth take an important role in the system behavior.While the bandwidth is limited by the inner control loop, the size of the capacitor depends on the application.In DC voltage control applications, such as those found in DC-links, the capacitor is usually sized according to the expected oscillations caused by stationary power fluctuations, which in some cases leads to oversizing [24], [37].Regarding AC grid-forming converters, the capacitor is often determined by the filtering requirements of switching frequency harmonics, leading to small capacitor values.
Increasing the capacitor size while maintaining ω n and ζ, will lead to an improved disturbance rejection without compromising the system stability.Fig. 14 shows the dynamic stiffness in the frequency domain and the time domain for 1 kW step response of the disturbance rejection transfer function ΔV (s) ΔP L (s) for different capacitor values using DVC and QVC.It is worth noting that the QVC and DVC performance is the same if P L0 = 0 W .
As expected, the disturbance rejection is improved as the capacitor increases.The size of the capacitor has a direct influence on the maximum disturbance the system can withstand, presenting the QVC a better performance, specially noticeable under low capacitance.
Techniques for voltage control disturbance rejection enhancement have been proposed in the past, mainly based on load decoupling through measurements, observers or estimators [32].A simpler alternative, presented before in the literature [34], [35], [36], is shown in Fig. 15, where D(t) = C v d dt .Using a pseudo-derivative feedback control, it is possible to add a virtual capacitance C v which ideally will be added to the passive capacitance C, improving the disturbance rejection.Assuming  an ideal derivative and ideal sensors, the transfer functions for DVC and QVC, can be modified by substituting the parameter C by C + C v .In addition, the virtual capacitance does not only allow to improve the dynamic stiffness but can also be used to emulate low capacitance systems by applying a negative value, i.e.C v < 0. Nonetheless, it is necessary to consider that the real implementation of the virtual capacitance is limited by the associated LPF.This should be set as high as possible, usually limited by the noise present in the feedback signal, but lower than the current control loop.Fig. 16 shows the non ideal response for a bandwidth of 200 Hz, affecting to the disturbance rejection at frequencies above that, but performing as ideal for frequencies below.

VI. EFFECT OF THE NOMINAL OPERATING POINT AND BANDWIDTH: DYNAMIC ANALYSIS AND DESIGN
Besides the stability limits, one of the most important characteristics considered for the design and analysis is the maximum voltage deviation under CPL steps.In this section, an analytical expression that allows to determine that deviation is proposed.

A. Dynamic Analysis of Maximum Voltage Deviation and Maximum Power Step
To normalize the effect of the capacitance, the nominal voltage and the nominal active power on the system response, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.to make this study applicable to any scenario, the parameter K pu was defined previously in (23), being dependent on these three parameters.If we define a new damping factor ζ as ( 27), the analytical linearized response becomes a function of three factors: K pu , ω n and ζ .Moreover, the stability condition will be now dependent on ζ , being the system stable as far as ζ ≥ 0.
Thus, the maximum voltage deviation ΔV pu max can be obtained with (28), where t m is defined by (29).
To evaluate the effect of K pu and ω n considering the nonlinearities, a non-linear simulation of the systems described by ( 4) and (7) has been conducted as an example using Matlab/Simulink and ode45 solver.ζ = 1 and P L0 = I L0= G L0 = 0 are considered in the equilibrium point.Fig. 17 shows the maximum voltage deviation under a CPL step as a function of K pu , and the power step disturbance, ΔP Lpu .The results are shown for DCV and QVC for two different bandwidths, ω n .ΔV pu = 1 represents the system voltage collapse or instability.It is worth to point out that the QVC extends the region of operation, allowing a better disturbance rejection and avoiding voltage collapse with  higher K pu values compared with the DVC method.The solid black line represents the analytical results for a ΔV pu = 0.5 pu, being in close agreement with the non-linear simulation results.
The voltage control bandwidth plays also an important role in the maximum voltage deviation.As an example of its effect, Fig. 18 shows the maximum CPL step, ΔP L p u that leads to a maximum voltage deviation of ΔV pu max = 0.65 pu.This maximum ΔP L p u is shown as a function of K pu , and the controller bandwidth, ω n .ΔP Lpu = 1 indicates that the system can withstand a CPL step of a power equal to the rated while keeping the voltage ΔV pu max ≤ 0.65 pu.The value of 0.65 pu has been used as an example, but this analysis can be perform for any value of ΔV pu max .

B. System Design Based on Maximum Voltage Deviation
The expressions derived in the previous sections can result as an useful and easy tool for the design and selection of the system parameters as well as its characterization.Both the analytical expressions and the simulation of the non-linear system, allows to select the value of K pu or ω n to comply with a determined  dynamic response, keeping the stability, under CPL steps.It also offers the for predicting the system behavior.When looking for the system design, as K pu depends on 3 parameters, its selection allows to determine the value of one parameter fixing the other 2. Thus, given a ω n , for a determined nominal voltage, V n and nominal power, P n , the size of the capacitor, C, can be obtained for a desired response.Similarly, given C, V n and P n , ω n can be inferred.Two alternative procedures are proposed in Fig. 19.
Table IV shows an example of design to select the capacitance given the system parameters (ω n , ζ, V n , P n ) and the maximum voltage deviation (ΔV pu max ) for a determined maximum CPL step (ΔP Lpu max ) using QVC.Regarding the selection of ω n and ζ, it will depend on the characteristics of the inner control loop and the expected load level in the equilibrium point respectively.In the case of ω n , it can be selected as high as possible, maintaining a high ratio between the outer and inner control loop bandwidth (usually > 10 in cascaded control systems).Appart from this limitation, in case of LC or LCL filters, the resonance frequency has to be damped and kept out of the current control bandwidth, imposing a superior limit for the overall system bandwidth [38].The damping factor ζ can be selected depending on the expected α 0 and β 0 .As those terms will vary depending on the load profile, it becomes interesting to adapt the value of ζ based on the load levels P L0 , I L0 and G L0 .

VII. EFFECT OF THE INNER CURRENT CONTROL LOOP
In the analysis carried out in the previous sections, the inner control loop has been considered as an ideal system with unitary gain and infinite bandwidth.This simplification assumes the decoupling between the outer and inner control loops if the ratio between their bandwidths is high enough.However, in a real implementation, the selection of such a ratio might not be trivial.Although the design and structure of the inner control loop is out of the scope of this article, this section analyses the role of the inner control in the application under study.The inner current control is modeled as the second order low pass filter defined before in (15).
Including this subsystem in the models defined in Sections III and IV and applying linearization, the expression in ( 24) is modified, obtaining the 4 th order transfer function in (30), where a 0 − a 4 are defined in (31).
The inner control loop gives rise to the definition of 4 new terms related with the load level, ω n i and ζ i .The terms α 1 , β 1 , α 2 and β 2 are defined in Table V.
As shown, considering ω n i = ∞, (30) turns to be equal to (24).However, the consideration of finite inner control loop bandwidth reveals new dependencies in the load level.It is worth to point out that a dependency on P L0 appears now in the QVC, which effect depends on the inner loop bandwidth.The larger is ω n i , the smaller the effect of P L0 .To analyze the effect of ω n i and P L0 when considering non-ideal inner loop, the system has been evaluated in two cases: 1) using different ratios between ω n i and ω n blue( ω n i ω n ) for a fixed value of P L0 and 2) using different values of P L0 for a fixed ω n i ω n ratio.Fig. 20 shows the frequency response of (30) for both DVC (left) and QVC (right), using the parameters of scenario 1 in Table II and ζ   In the upper part of Fig. 20, P L0 = 4% and different ratios of ω n are analyzed.ω n i affects mainly at high frequencies, reducing the disturbance rejection as ω n i decreases.Nonetheless, the response is always similar for all the cases (≤ 1 dB) at least for frequencies below the voltage loop natural frequency ω n .Nonetheless, an underdamped response is observed for all the cases in DVC and for QVC with low ω n i .It is worth pointing out that the disturbance rejection for the DVC is worse than for the QVC in any of the cases.The lower part of Fig. 20 shows the response using a ω n i ω n ratio of 10, common in cascaded controllers, and increasing P L0 .As expected, the effect of P L0 in the DVC remains as in the previous analysis, ensuring a similar response only below 14 Hz for the analyzed cases.On the other hand, although P L0 affects the response in the QVC when considering a finite ω n i , the effect is reduced and present only at high frequencies above the voltage control bandwidth.Some conclusions can be drawn, 1) increasing the inner control bandwidth can drastically reduce the effect of P L0 in the QVC but not in the DVC, 2) ω n i affects at frequencies higher than ω n as soon as the system is stable, 3) the effect of P L0 is acceptable in the QVC for ω n i ≥ 10, and 4) the effect of P L0 in the DVC might be more critical than the ratio

VIII. EXPERIMENTAL RESULTS
The control models presented in this article have been tested experimentally under 2 different scenarios, covering the application of voltage control in both DC and AC grids.The experimental results have been obtained using the Triphase power modules PM15F42 C and PM90F60 C. The experimental parameters are included in Table VI.
Fig. 21 illustrates the simplified scheme of the experimental setups.For the DC voltage control, an inverter coupled to the DC/DC converter of a battery energy storage system (BESS) has been used (PM15F42 C).The DC-link voltage is controlled by  56 considering 3-phase system).The AC control has been implemented in the dq synchronous reference frame applying the QVC and DVC to both d and q axis [31].Fig. 22 shows the response of both DVC and QVC under increasing CPL steps for several capacitor values in the DC MG setup.Due to the experimental setup limitations, the capacitor has been resized using virtual capacitance (Fig. 15), being the physical capacitor value 1000 μF .To better illustrate the effect, the voltage regulator bandwidth has been set to 6 Hz.Fig. 23 shows the performance comparison between DVC and QVC in the AC 3-ph MG with an increasing CPL.The instantaneous voltage magnitude is represented.As expected   from simulations, the DVC dependency on the load level makes its response to be worsen with increased CPL level (P L0 ).It is worth noting that the local resistive load provides an improved damping, allowing to move the stability limit from P L0 2.66 kW (see Table III) to P L0 5.5 kW.To demonstrate the use of virtual capacitance applied to the AC setup, the performance under different virtual capacitance values is shown in Fig. 24  the Virtual Capacitance LPF selected experimentally, pursuing the maximum possible bandwidth without being affected by feedback noise.
To demonstrate the viability of the response prediction proposed in Section VI, the experimental data in Figs.22 and 23 have been compared with the expected response obtained analytically with the expressions (28) and (29).The results are shown in Fig. 25, exhibiting a close match between the experiments and the predicted ΔV pu .

IX. CONCLUSION
The article has proposed a simple but effective methodology for the analysis of cascaded voltage control in grid-forming units feeding different type of loads, with a special concern about CPLs.The study has focused in the analysis of two PI-based control methods, DVC and QVC, that have been compared outlining their benefits and drawbacks, summarized in Table VII.The QVC has proved to enhance the dynamic behavior under CPL disturbances.As demonstrated, the proposed generalized method can be applied to converter having different rated values, thus having the potential of becoming a design tool.It is worth noting that the methodology leaves up to the designed the selection of parameters which are application dependant such as the load level in the equilibrium point, the stability margins and the maximum voltage deviation under CPL disturbances.The ideas presented during the theoretical discussion allow for building a methodology for the voltage control loop design or the selection of the capacitor value considering the dynamic performance.Additionally, the use of the virtual capacitance as a tool for response enhancement, and as a tool to experimentally forecast the effect of resizing the capacitance in existing systems, has been evaluated.The ideas and proposals in the article has been validated and illustrated through Matlab simulations and experimental results in an experimental rig integrated by Triphase equipment, matching the expected operation predicted by the analytical analysis.

Fig. 1 .
Fig. 1.Simplified diagram of the grid-forming control and system plant.

Fig. 2 .
Fig.2.Simplified diagram of the control, system plant and load disturbance for a generic DC or 3-phase AC grid-forming unit (considering dq reference frame complex form representation).

Fig. 3 .
Fig. 3. Voltage-Current curves of the different types of loads in MGs.

Fig. 5 .
Fig. 5. Non-linear simulated reference tracking response.Comparison between DVC and QVC when using ω n = 2π50 and ζ = 0.7 in both methods.

Fig. 6 .
Fig. 6.Effect of the inner current control loop.(a) Bode diagram of the open loop transfer function (16); (b) Bode diagram of the transfer function (14) with ideal sensor(G fb = 1).

Fig. 7 .
Fig. 7. Effect of the sensor delay and bandwidth with ideal inner control (G i = 1).(a) Bode diagram of the transfer function (14) and pure feedback delay (G fb = e −sτ d ); (b) Bode diagram of the transfer function (14) with LPF sensor and delay.

Fig. 8 .
Fig. 8. DVC: Non-linear simulated response compared with the linear approximation of ΔV (s) ΔP L (s) under increasing active power steps.Top, absolute value.Bottom, pu deviation.

Fig. 10 .
Fig. 10.System response depending on the load level terms α 0 and β 0 .(a) System root-contour for the gain (α 0 + β 0 ) valid for DVC and QVC.(b) and (c) Bode diagram of the closed loop disturbance rejection transfer function for different values of α 0 + β 0 .

Fig. 11 .
Fig. 11.Step response under a CPL step disturbance of 2%(1 kW).(a) Influence of P L0 in DVC; (b) Influence of I L0 in QVC; (c) Influence of G L0 in DVC; (d) Influence of G L0 in QVC.

Fig. 12 .
Fig. 12. Disturbance response under increasing CPL.Load is increased by steps of 480 W (9.6%) every 30 ms.Dashed lines show the linear approximations.(a) DVC.(b) QVC.Results using the data in TableII.

Fig. 14 .
Fig. 14.Evaluation of the capacitor size effect in the disturbance rejection capabilities.(a) DVC and QVC dynamic stiffness, ΔP L (s) ΔV (s) , for different capacitor values and P L0 = 0W; (b) DVC dynamic stiffness when P L0 = 1.2k;(c) DVC and QVC step response of the transfer function ΔV (s) ΔP L (s) for P L0 = 0W; (d) DVC step response of the transfer function ΔV (s) ΔP L (s) for P L0 = 1.2kW.

Fig. 15 .
Fig. 15.Modified voltage control scheme using virtual capacitance C v .

Fig. 16 .
Fig. 16.Effect of the virtual capacitor LPF in the the disturbance rejection response.LPF BW of 200 Hz.For (a),(b),(c) and (d) refer to caption of Fig. 14.
i = 0.707.Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 22 .
Fig. 22. DC setup experimental results.DC grid forming converter performance for different capacitor values.(a) DVC and b) QVC are compared under multistep P L , from 0 to 5 kW.Dashed lines show average model simulations.

Fig. 23 .
Fig. 23.AC setup experimental results.AC grid forming converter performance.DVC and QVC are compared under multistep P L , from 0 to 5 kW.Dashed lines show average model simulation results under same load profile.

Fig. 25 .
Fig. 25.Comparison between the experimental results and the analytical prediction of ΔV pu for different values of P L0 .Dashed lines represent the predicted response.(a) DC setup using DVC; (b) DC setup using QVC; (c) AC setup using DVC; (d) AC setup using QVC.
comparing the step response of DVC and QVC.The improved response of the QVC with respect to the DVC should be highlighted, specially when low capacitance values are used.A cut-off frequency of 200 Hz has been used for Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE I DEFINITION
OF α 0 AND β 0

TABLE III EXAMPLE
OF STABILITY LIMITS FOR THE SYSTEM DEFINED IN

TABLE IV EXAMPLE
OF SYSTEM DESIGN USING THE PROPOSED METHODOLOGY

TABLE VI SYSTEM
PARAMETERS USED FOR VOLTAGE CONTROL ANALYSIS

TABLE VII COMPARATIVE
SUMMARY OF DVC AND QVC PERFORMANCE