The Formation of a Chip Scale Atomic Clock Ensemble Using Software Defined Radios

Low size, weight, and power (SWaP) clocks are expected to play a key role in new positioning, navigation, and timing (PNT) systems, providing augmentations or alternatives to conventional global navigation satellite systems (GNSS). Distributing high-quality PNT services from payloads with more limited resources than GNSS satellites requires signal generation from low SWaP hardware. This paper describes stable signal synthesis based on a low cost clock ensemble using software defined radio (SDR) metrology techniques and clock ensemble algorithms. First, the capacity to accurately characterize the stability of different clocks using the SDR is demonstrated. Experimental results then establish the ability to steer an oven controlled crystal oscillator (OCXO), initially to a single reference clock signal, and then to the implicit ensemble mean (IEM) of three chip scale atomic clocks (CSACs). This steered output signal has noise comparable to the short term stability of the OCXO and long term stability similar to the best clock in the ensemble.


I. INTRODUCTION
P ROLIFERATED low Earth orbit (pLEO) constellations of small satellites provide new opportunities for global communication, Earth observation services, and alternative approaches to space-based positioning, navigation, and timing (PNT). Most small satellites in low Earth orbit (LEO) rely on free, historically ever-present global navigation satellite system (GNSS) signals to support on-board positioning needs. While GNSS is best known for supporting navigation, disseminating precise time and frequency is equally important for communication and science goals. The time and frequency distributed by GNSS are used by communication systems for accurate carrier frequency generation and data bit alignment. Secure networks have especially stringent timing needs for the synchronization of data encryption and decryption equipment [1]. Science missions require precise timing to support long coherent signal integration in the case of low power signals, particularly in sparse aperture imaging applications [2]. The transmitter clock standards for time-of-flight based, one-way navigation systems, such as current GNSS, are quite demanding due to their direct impact on range measurements and the resulting position and time accuracy (receiver clock errors are solved for in the GNSS solution).
Since the 1950s, the gold standard for timekeeping has been large, laboratory grade, ground-based atomic clocks. Technological advancements have since reduced the clock size to where high-stability atomic frequency standards are hosted on GNSS satellites [3], providing a consistent, accurate, and free frequency source to both military and civil users around the globe. Atomic clocks on-board the satellites are the basis of GNSS timekeeping systems [4], enabling accurate time-tagging of the navigation signals. Clocks used on GNSS platforms are generally not suitable for small spacecraft or ground vehicles due to their size, weight, power, and cost (SWaP-C) requirements. The development and integration of high stability, low SWaP-C clocks to enable such applications is underway in both government and commercial sectors [5].
Small satellites in LEO providing PNT services will need to reliably generate stable signals tied to an established time reference. An alternative to a time reference based on a single, high performance clock is an ensemble of less expensive, lower performance oscillators, from which a high stability clock signal can be derived [6]. Our hardware testbed is comprised of chip scale atomic clocks (CSACs) which form the clock ensemble; software defined radios (SDRs) to process the clock signals; software to implement the ensemble algorithm; and a steerable clock for the realization of the implicit ensemble mean (IEM). The clock ensemble system has been constructed based on approaches implemented at the German Aerospace Center (DLR) [7], [8], [9] and a clock characterization method using software defined radios, introduced by Sherman and Jördens at NIST [10].
The work described in this paper makes two contributions to the field of small satellite timing systems. First, it describes the hardware implementation of a three CSAC ensemble using a commercial software defined radio. The architecture presented here is applicable to co-located clocks on a single platform, such as an unmanned aerial vehicle (UAV) or a small satellite. Second, it details the steering methods used in the hardware realization of the clock ensemble, implemented with controllable OCXOs and a high precision, low cost DAC for frequency adjustments. The steered output signal maintains some of the OCXO short term stability and achieves long term stability comparable to the most stable clock in the ensemble. The methods described are applicable to clock ensemble formation in both self-contained systems with co-located clocks as well as across distributed platforms, such as satellites in clusters or constellations.
The paper describes the final version of a hardware testbed used to form and evaluate the clock ensemble, with block diagram shown in Fig. 1. The following sections describe the individual components and methods. Section II details the theoretical models used for generating simulated clocks, signal steering, and estimation. Section III describes the clocks and SDR hardware, clock metrology method used to characterize these devices, and the results of that characterization. Section IV shows the clock steering hardware implementation; Section V presents the system integration and results. The paper concludes with a summary of our findings and a discussion of future research plans.

II. THEORETICAL MODELS
Software models are developed to evaluate expected system performance prior to hardware implementation. Mathematical representations of the system dynamics and measurements are based on observed clock and testbed behavior, ensuring the fidelity of the models implemented in real-time estimators. Additionally, the software simulations are useful for rapid iteration of different design parameters for later utilization in the hardware implementation.

A. CLOCK PROFILES
The measured or simulated time series of oscillator states is referred to as a clock profile. We use a simple twostate dynamic clock model for simulation and estimation  studies. Oscillator specific stability parameters determine the state evolution for each clock. The equations below describe the discrete time model used in the project [11], [12]. The oscillator states evolve according to the dynamics shown in (1) with state transition matrix, A, detailed in (2). The discretization time step of the system is represented by τ 0 .
The process noise, w k , is assumed to be Gaussian with zero mean and covariance Q(τ 0 ) described by white and random walk frequency noise parameters, q 1 and q 2 , specific to each clock. Reference [13] describes a method to compute these noise parameters from Allan deviation specifications for any device. Realizations of this noise are represented by the noise vector, w k , and are incorporated into the simulation according to (1).
Time series of simulated clocks are generated using the process noise parameters in Table 1. For the simulated clocks, typical accumulated time error after 24 hours is ±2 µs for the CSACs and ±50 µs for the OCXO. The overlapping Allan deviation (ADEV) for the simulated time series is shown in Fig. 2. The ADEV curves show the specification values and the computed stability of each simulated clock as a function of the averaging interval, τ . The OCXO and CSAC ADEV curves intersect at an averaging interval of 200 secondsthus, a desired clock steering response will preserve the short term stability of the OCXO to the left of this point, and steer towards the CSACs at longer averaging intervals to the right.

B. CLOCK STEERING
The repeated adjustment of oscillator frequency is known as clock steering. Clock steering techniques are used in the realization of timescales in order to take advantage of the best clock stability across different averaging intervals [17]. In initial steering tests we steer a simulated OCXO to simulated CSAC 01 from Fig. 2. A steering simulation environment enables rapid evaluation of the different parameters -clock stability, control rate, response stiffness -to understand the effect of each on the output signal.
When steering in simulation, the phase and frequency offset between the OCXO and the target state are known perfectly. The offset is treated as a perturbation from which a frequency correction is computed and applied. We want to minimize the state error -the phase and frequency differences between the OCXO and the CSAC -by adjusting the frequency of the OCXO. The discrete-time oscillator dynamics, including a control input, are presented in (5)- (7).
Through the use of a control input, B, and gain matrix, K, the eigenvalues can be chosen such that the error with respect to a target state is driven to zero over time, indicating phase and frequency alignment with a target oscillator. The gain matrix is computed using the pole placement method where the characteristic equation of A − BK is used to solve for K matrix values that yield the desired poles [18]. Fig. 3 shows the time series of two OCXO steering simulations with a control rate of one second and different gain matrices. The red curve is CSAC 01 -the target state -and the other curves correspond to steered OCXO signal responses. The black curve in Fig. 3 is a steered OCXO response with small gain parameters, indicating gentle steering. The green curve in Fig. 3 has slightly larger gain parameters, which will result in stiffer steering and closer alignment with the time series of the target state.
The goal of clock steering is to generate an output signal with small ADEVs at all averaging intervals. From the time series, the best response is challenging to determine; in fact, it may seem that the black curve is performing worse than the green curve, as it is farther from the target CSAC state. The optimal steered signal response and the effect of control system quantization are discussed in the following section.

1) CLOCK STEERING HARDWARE CONSIDERATIONS
Steering clocks in simulation allows for an extremely high level of precision in the control command and almost no limits on the control rate. In a hardware implementation, both of these assumptions break down; the precision of the control input is determined by the voltage source resolution and the fastest control rate is determined by the system latency. The control command was quantized at a fractional frequency of f f = 4 · 10 −12 and the control rate was set to one-second. These values reflect the limitations of our hardware testbed, specifically the DAC voltage resolution and VOLUME 3, 2023 the fastest realizable control rate. Fig. 4 presents the ADEV of each signal, clearly showing the effects of different control parameters and quantization.
The solid black curve in Fig. 4 represents the ADEV corresponding to the black curve in Fig. 3. This is a very desirable response, as the steered signal has the short term stability of the unsteered OCXO, and CSAC stability at longer averaging intervals. Unfortunately, with the quantization in place, small gain parameters will result in a control command of zero until the state error is sufficiently large to produce a correction that rounds to the minimum frequency adjustment. This results in the dashed black curve significantly overshooting the target ADEV curve until averaging intervals of 10,000 seconds or longer.
The solid and dashed green curves in Fig. 4 represent a signal response with slightly larger gain values, such that control commands with magnitudes larger than the minimum frequency adjustment are immediately produced. The short term stability of the steered signal is slightly degraded compared to the small gain case, but has improved the stability between averaging intervals of 100 to 1,000 seconds when quantization is imposed.
The combined effect of feedback gain parameters, control rates, and hardware limitations all have a coupled effect on the stability of the steered output signal. The optimal configuration depends on the requirements in each individual scenario. Stiffer gain parameters will match the target state long term stability sooner, but by sacrificing short term OCXO performance. If short term oscillator stability is paramount, a soft steering approach may be preferable but comes at the cost of larger instability at intermediate intervals, an effect known as a servo-bump [19].

C. CLOCK ESTIMATION
Our clock estimation strategy is based on Brown's [20] clock ensemble Kalman filter. The phase and frequency of one clock can only be measured relative to another reference oscillator. When a stable reference is not available, the clock states can be estimated from differential phase measurements. The filter uses these phase difference measurements to estimate clock states following the procedures in [7] and [20]. The clock state estimates and differential phase measurements are used to compute the phase and frequency difference between the OCXO and the ensemble average; this error vector is then used to compute a frequency adjustment and steer the OCXO to the IEM.

1) DYNAMIC MODEL
The system states and state transition matrix for the clock estimation Kalman filter are shown below. The state vector is comprised of three clocks, each with two states -phase and frequency -represented by b and f . The numeric subscript represent the clock number and the k subscript represents the timestep index.
The inputs to the filter are phase difference measurements between the ensemble member clocks. The measurements are used to estimate the phase and frequency of each member clock. The standard deviation of the measurement noise, v k , depends on the measurement system and will be discussed in Section III-C. The measurement input, z k , consists of two differential phase measurements at timestep k. The matrix in (11) shows the measurement sensitivity of two differential phase measurements, where the phase of clock one is subtracted from clock two and clock three, respectively.
A system with N clocks and N − 1 differential clock phase measurements will always be unobservable since an error common to all clocks will not appear in differential measurements [20]. The observability matrix in (12) shows that no matter how many differential measurements are made, 80 VOLUME 3, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
the rank of the observability matrix is always less than the number of states we are trying to estimate.
The covariance reduction method detailed in [20] separates the observable and unobservable components of the state covariance matrix, , and uses the observable component to prevent unbounded uncertainty growth. The covariance reduction step uses (13)- (14) and is implemented after the measurement update in the Kalman filter. The reduced covariance matrix, P r , is then propagated in the next filter iteration. 3

) IEM REALIZATION
A steerable OCXO creates the IEM realization for the clock ensemble. The clock state estimates and OCXO phase are used to compute the phase and frequency offset of the OCXO with respect to the IEM. In simulation, this offset can be computed exactly, but in hardware implementation it must be estimated from OCXO phase measurements. Following the theory in [7], the estimate for clock i (x i,k ) and the third measurement (z 3,k ) at timestep k can be written as: The filter output in (15) is the two-state phase and frequency estimate for each ensemble member clock, rewritten as the difference between the true clock state (x i,k ) and the IEM (x 0,k ), plus estimation noise (e i,k ). A third measurement (z 3,k ) provides the phase difference between the OCXO (b 4,k ) and the reference clock (b 1,k ), plus measurement noise (v k ). The phase estimate for the first clock (b 1,k ) and third measurement (z 3,k ) are added together in (17), resulting in the phase difference between the OCXO and the IEM, including both measurement and estimation noise. This phase error is used as a measurement input for another Kalman filter to estimate frequency error -the estimated phase and frequency values are multiplied by a gain matrix, as detailed in Section II-B, to compute a frequency adjustment for the OCXO.

4) ESTIMATION PERFORMANCE
The system response of steering the OCXO to the IEM is analyzed in the same manner as described in Section II-B -the OCXO response is designed using the pole placement method [18] to generate a gain matrix for specified eigenvalues.
The simulation uses three CSACs as ensemble member clocks and an OCXO as the steered signal source. The three individual CSACs were modeled based on lab testing, which showed better stability than the specification. The noise parameters for each of the CSACs are shown in Table 2 and corresponding ADEVs are shown in Fig. 6. The simulated steered signal response uses a control update interval of one second and quantized control commands corresponding to what is used in the hardware implementation.
The time series of the three simulated CSACs, the IEM, and the steered OCXO are shown in Fig. 5. The IEM is shown in black and approximately follows the average of the three CSACs. The steered OCXO, in orange, closely follows the IEM. Fig. 6 shows the frequency stability of all oscillators involved. In this case where CSAC 01 is more stable than the other CSACs, the IEM stability is very similar to the stability of CSAC 01. The effect of OCXO steering results in a servo bump peak at τ = 30 s, reaching an ADEV of 1.6 · 10 −11 . The steered signal has better short term stability than any individual CSAC and turns over to follow the IEM at averaging intervals greater than 50 seconds.

III. CLOCK CHARACTERIZATION WITH SDRs
The previous sections assumed that both the phase and frequency of simulated test oscillators were known. In the lab, we use a software defined radio to observe actual clock behavior. The process for SDR clock characterization is based on [10] which describes methods used to store clock stability information at low data rates. In this architecture, the radio shifts timing signals to a lower frequency -reducing the sample rate required to represent the signal while preserving the low frequency error of interest. When two timing signals are input to an SDR, a test and a reference, both will contain a common error contribution due to the local oscillator. The difference between the computed phase of the test and reference signals causes the common error contribution from the SDR clock to drop out, resulting in the phase of the test oscillator measured against the reference.
Two software defined radios are used for clock analysis -an Ettus N310 and an Ettus N200. The block diagram for clock characterization is shown in Fig. 7 and applies to both SDRs, with slight differences in the RF front end. The processing described in Fig. 7 is a subset of the full system, which is shown in Fig. 1. Because of the SDR hardware, the clock signals processed by the Ettus N310 are first upconverted into the frequency range of the internal AD9371 transceiver (f min = 300 MHz), mixed down using the requested beat frequency, digitized, and then sent to a PC. The signal processing for the Ettus N200 is determined by daughterboards that handle input signals differently. We use a BasicRX daughterboard which directly samples the input timing signal and digitally down-converts to a user specified beat frequency. The low frequency, digitized signal from each SDR is sent over Ethernet to a PC for further processing in GNU Radio Companion [21].

A. GNU RADIO COMPANION
GNU Radio Companion [21] is an open-source dragand-drop programming environment used to interface with software defined radios. In a GNU Radio script the SDR is a signal source for down-converted clock signals. These data streams are represented as a complex combination of two sinusoids, referred to as in-phase and quadrature (I & Q) components. The I/Q data go through the signal processing chain in Fig. 7, which uses built-in and custom functionality to make clock phase measurements. The custom blocks used in the entire system shown in Fig. 1 are listed in Table 3.
Each GNU Radio script begins with SDR I/Q data sources for each signal -however, the data is not streamed one sample at a time. The dynamic GNU Radio scheduler attempts to optimize program performance by breaking the streams of data into chunks. The overhead associated with moving data is significant and the program runs more efficiently when each block operates on a chunk of data rather than a single sample. GNU Radio sets up the program such that each block has buffers that fill up with data prior to operating on the data. This can present a challenge for real-time systems which implement open or closed loop control [22].
The input buffer size will affect the realized input and output rate of each block. A block will only operate on input data once the buffer is filled -as a result, a block will wait for a full buffer prior to operating on the data. The minimum buffer size in GNU Radio is 8 samples. If the input rate to a block is 1 sample per second, the block will operate on all samples every 8 seconds rather than match the output rate to the input rate. In order to realize an output rate of 1 sample per second, the input must be set to a higher rate and decimation should be handled in the Python code to allow time for the buffer to fill. In this method the buffer fills faster than the desired output rate and the output rate is controlled programmatically.

B. CLOCK PHASE MEASUREMENTS
The fundamental measurement used to observe oscillator stability is the test oscillator phase with respect to a reference oscillator. The process for making phase measurements using the SDR is shown graphically in Fig. 7. The test and reference clocks are shown on the left side of the diagram as 10 MHz signal sources. After the SDR performs the down-conversion process, the signal sent to the host PC is at a user specified beat frequency of 73 Hz with a sampling rate of 120 kHz. A beat frequency of 73 Hz was selected so that the signal sample phase shifts in time. During the frequency mixing process the clock on-board contributes a common error present in both signals. The first step in the signal processing is to remove the nominal 73 Hz signal from the incoming data streams, leaving a near-DC complex signal. The argument of the complex signal is computed and yields a phase from [−π, π]; this phase is unwrapped and most remaining phase growth is due to SDR clock instability.
We found that it is important to remove a 73 Hz signal from the beat frequency prior to phase calculations. The unwrapped phase for both 73 Hz beat signals, while not a particularly high frequency, will grow without bound at the rate φ = 2πf beat t. These large unwrapped phases are then subtracted from each other, providing a phase difference time series representing the frequency stability of the test clock. The problem with this approach is the test clock frequency error is much smaller than the beat signal frequency. As the unwrapped phases grow without bound, there is a loss in decimal precision of the phase difference due the finite number of bits used to represent the values. Any loss in phase precision will degrade the accuracy with which the test clock frequency errors can be measured. Removing the 73 Hz signal before unwrapping the phase preserves phase information at the required accuracy.

C. SDR NOISE CONTRIBUTION
Any hardware implementation may contribute noise to the phase measurement, potentially obscuring or misrepresenting the input oscillator behavior. Three experiments were conducted to quantify the error contribution of the following measurement systems: measurements made with the N200, measurements made on the same transceiver of the N310, and measurements made on different transceivers of the N310. The noise is computed using phase measurements of a common input signal. Identical clock signals are connected to each measurement system and go through the processing described in Section III-B. The phase difference between the signals should be zero; any remaining non-zero values represent the system measurement noise.
We found that the noise for each measurement method is approximately zero mean, white, and Gaussian. The 3σ noise value for the N200 system is 30 ps. Measurements on the same daughterboard of the N310 contribute 5 ps (3σ ); whereas measurements across different daughterboards of the N310 contribute 1 ns (3σ ) of noise, a significantly larger value than the others. The ADEV of the measurements shows the size of the noise with respect to the clock stabilities of interest. If the measurement noise is larger than the clock ADEV values, data gathered from that system will obscure the true stability of the clocks at those averaging intervals.
The computed ADEV values from the measurement noise are shown in Fig. 8 along with the stability specifications for the clocks in our lab. Measurements made on the same daughterboard of the N310 have a small noise component (1.7 · 10 −12 at τ = 1 s) that will not obscure clock behavior at all averaging intervals -this result is comparable to the noise results from NIST [10]. The noise of the N200 will obscure the behavior of the rubidium and NEL OCXO at short averaging intervals, but over time the noise will average down below both of those oscillators. Measurements on different daughterboards of the N310 would obscure behavior of the OCXO and Rb signals; however, the contributed noise level is smaller than the CSAC specification for all averaging intervals.

D. MEASURED CLOCK STABILITY
Three categories of clocks are used in this project: CSACs, OCXOs, and a rubidium frequency standard. Three Microsemi SA.45s CSACs are used as the members of a small clock ensemble; an NEL Frequency Controls, Inc. 0-CMR-058IS-N-S-L OCXO produces the realization of the IEM; and a Stanford Research Systems FS-725 rubidium frequency standard is used as a reference oscillator. The measured ADEV values and the specifications for the CSACs, OCXO, and rubidium frequency standard (Rb) are shown together in Fig. 9. The Rb oscillator was characterized at NIST in 2019 using a multi-channel measurement system (MCMS) with dual-mixer time-difference measurement techniques [17]. All other clocks on this figure were evaluated at the University of Colorado (CU) Boulder using the methods described in Section III-B.
The stability values shown in Fig. 9 -with the exception of the Rb -are computed with respect to the Rb on the same transceiver of the N310. The noise contribution from both the measurement system and Rb oscillator is smaller than CSAC noise for all measurement intervals, indicating that this VOLUME 3, 2023 measurement system can correctly represent clock behavior. Interestingly, the measured short term (τ < 5 s) stability of the NEL OCXO is masked by the short term instability of the Rb. The true behavior of the OCXO in the short term cannot be measured using our existing setup, but we assume the actual OCXO stability is better than what is shown.
The manufacturer stability specification for each clock, when available, is included on Fig. 9. All CSACs are performing within the specification with CSAC 01 being slightly more stable than CSAC 02 and CSAC 03. For intervals longer than approximately 5 seconds, the freerunning OCXO starts degrading and become less stable than the CSACs beyond 40 seconds.

IV. CLOCK STEERING
Our local time scale is realized using an OCXO with high quality short term stability. Small frequency adjustments are applied to steer its output to the IEM of the clock ensemble. The OCXO has an electrical tuning input which changes the frequency of the oscillator as a function of applied voltage. The response of the OCXO to a predefined voltage profile was measured experimentally to determine the slope of the voltage / frequency curve. This curve is used in the steering model to compute voltage adjustments based on measured phase differences between the OCXO and the target state. To verify the steering process, the OCXO is first steered towards a single CSAC.

A. CONTROL VOLTAGE SOURCE
Frequency adjustments are computed and applied programmatically in order to implement a closed-loop system. A high resolution, low noise 18 bit DAC (Linear Technology 1684A-A) was used for frequency adjustment voltage commands. The smallest programmable resolution of the device is 19 microvolts. We used a Linduino development board (Analog Devices) which allows users to interface with the DAC as if it were an Arduino product, enabling rapid script development.

B. STEERING TO A CSAC
The steerable OCXO, the voltage control method, and custom GNU Radio signal processing are combined to steer the OCXO to a single CSAC. The phase difference between the OCXO and CSAC is used as an error signal; from this phase error a corresponding estimate of frequency error is generated from a Kalman filter. The two state error vector, phase and frequency, is used to compute a frequency adjustment that is applied to the OCXO.
Gain parameters were determined using the simulation methods detailed in Section II-B. An 8 Hz control rate and small gain parameters were used to generated the steered signal in Fig. 10. The steered signal retains some of the unsteered OCXO stability in the short term and smoothly transitions to the target CSAC state in the long term with minimal overshooting from the servo bump effect.

V. CLOCK ENSEMBLE TESTBED INTEGRATION
The previous sections described components that have been developed and tested individually prior to system integration. The formation of a fully integrated, closed loop clock ensemble uses both SDRs, all of the aforementioned clocks, and custom GNU Radio processing code.
The testbed hardware realization of the block diagram from Fig. 1 is shown in Fig. 11. Three CSACs connected to the N310 form the clock ensemble and the OCXO output is the realization of the IEM. The N310 downconverts the 10 MHz input clock signals to a 73 Hz baseband where they are sampled at 120 kHz and processed in GNU Radio. The clock ensemble Kalman filter running on the computer uses differential CSAC phase measurements to estimate the phase and frequency of the three input clocks. The estimated clock phase for the first CSAC is added to the phase difference between the OCXO and the same CSAC, resulting in the phase offset between the OCXO and the IEM. This phase offset is used to estimate the phase and frequency offset of the OCXO relative to the IEM in the steering Kalman filter. The feedback voltage then adjusts the OCXO frequency to minimize the two-state error vector. In the laboratory we also use an Ettus N200 and rubidium frequency standard to evaluate the behavior of the steered OCXO signal. Evaluating the OCXO in this manner would not be possible in a deployed system, as another reference would not be on-board.

A. INTEGRATED TESTBED RESULTS
Multiple tests were run with different OCXOs, various methods of voltage adjustements, and different control rates to assess the optimal combination. The time series of the OCXO phase was measured against the Rb on the N200 and the ADEV was computed to assess the signal stability. Results from the best hardware and software configuration are shown in Fig. 12.
We found that the high rate, gentle steering demonstrated in Fig. 10 is not possible when steering to the IEM. With the improved stability of the IEM, the previous gain parameters are not stiff enough to drive the OCXO to the IEM; as such, stiffer gain parameters were chosen for the integrated system. At averaging intervals less than 10 seconds the steered NEL OCXO has better stability than any individual CSAC. The effect of steering is clear at averaging intervals longer than 10 seconds as the signal stability is better than the corresponding free-running curve. Steering the OCXO with the DAC yields a small servo bump that overshoots the best performing CSAC by a small amount. The servo bump in the hardware realization is at a similar location and magnitude as in simulation, shown in Fig. 6. The max value is at τ = 30 s, ADEV = 2 · 10 −11 . At longer intervals the stability of the steered signal approaches the IEM.
In the ideal case, the stability of the steered curve would have better stability than any individual member clock. As seen in Fig. 12, the steered clock has a better stability than the two worse performing CSACs, but almost the same stability as the best CSAC. This effect agrees with what is shown in Fig. 6: in the case of a small clock ensemble where one member clock is significantly better performing than the others, the IEM of the ensemble will have approximately the same frequency stability as the most stable oscillator.

VI. DISCUSSION
In this work we demonstrated the ability to characterize clocks using SDR metrology techniques, programmable steering of an OCXO, and clock ensemble formation with the steered OCXO as the IEM realization. The ability to accurately characterize clocks using SDRs depends on the stability of the oscillators under test, the quality of the reference clock, and the measurement system noise contribution. In Fig. 8 it was shown that the best measurement system contributes noise on the 5 ps scale at τ = 1 s, which is much smaller than the short term stability of all clocks. While the CSACs can readily be measured against the Rb with any of the measurement systems, measuring OCXO behavior at short averaging intervals is limited by the stability of the rubidium frequency reference. In order to accurately observe OCXO behavior at short intervals a more stable reference oscillator or alternative methods of clock characterization are required.
The noise contribution from the measurement system had a negligible effect on the ability to characterize oscillators, as it is smaller than the stability of all our clocks at 1 second. If clocks with better stability were used, the short term measurement noise would need to be considered.
The clock steering analysis demonstrated the impact of OCXO stability and the voltage source on output signal quality. An OCXO with improved short term stability with respect to the target clock state will result in a better steered signal as the clock can be gently steered to rely on the improved free-running stability of the clock over short intervals. The voltage source determines the smallest possible frequency adjustment and fastest control rate. A high voltage resolution will result in a smaller discretized frequency adjustment for a given voltage range. Additionally, voltage source settling time and the latency of the OCXO steering system drives the smallest control rate, which had different values when steering to a single CSAC (0.125 s) as compared to steering to the IEM (1 s). The smaller control rate resulted in signal stability that did not overshoot the target state, but  did yield worse short term stability than the larger control rate.
In the case of this small clock ensemble where one oscillator is significantly more stable than the others, the IEM closely follows the behavior of that oscillator. For the purpose of generating a clock signal better than the ensemble members, in this scenario it seems logical to simply steer the OCXO to the best clock and not bother with ensembling. However, this ignores the benefits of using multiple clocks; with only one clock there is a single point of failure in the timing system. With multiple clocks in an ensemble, the effect of clock errors or failures can be detected and mitigated by analyzing the behavior across the relative phase measurement sets.

VII. CONCLUSION & FUTURE WORK
The clock testbed described here enables rapid testing of different oscillators, estimation and tuning algorithms, and the combined impact on an output timing signal. This analysis provides initial research towards architectures that support clock comparison and time transfer across multiple platforms in a satellite constellation or UAV cluster. Additional investigation of suitable hardware for an on-orbit demonstration is required.
Future work will focus on the stability of the steered output signal in the presence of phase and frequency errors in the member clocks. The effect of clock errors on the steered OCXO signal both with and without detection and mitigation systems are of interest. Additionally, we plan on expanding the clock ensemble using additional CSACS and SDRs. The expansion should yield a steered OCXO signal with noticeably improved stability for long averaging intervals.