Comparative Evaluation of Gate Driver and LC-Filter Based dv/dt-Limitation for SiC-Based Motor-Integrated Variable Speed Drive Inverters

Compared to state-of-the-art IGBTs, SiC power semiconductors allow to achieve ever higher system efficiencies and higher power densities in next-generation Variable Speed Drives (VSDs), thanks to their smaller relative chip size, ohmic on-state characteristic and lower specific switching losses resulting in a smaller switching-stage footprint and lower heat sink as well as DC-link capacitor volumes. However, the high slew rate of the switching transitions, an inherent consequence of the low switching losses, represents a major challenge and potentially results in lifetime degrading unequal voltage distribution across the motor windings and bearing currents. This work analytically and experimentally compares different means for d<inline-formula><tex-math notation="LaTeX">$v$</tex-math></inline-formula>/d<inline-formula><tex-math notation="LaTeX">$t$</tex-math></inline-formula>-limitation, namely, a conventional passive LC-d<inline-formula><tex-math notation="LaTeX">$v$</tex-math></inline-formula>/d<inline-formula><tex-math notation="LaTeX">$t$</tex-math></inline-formula>-filter and a Gate Driver (GD)-based approach based on increased GD resistances in combination with explicit Miller capacitors, at the example of a <inline-formula><tex-math notation="LaTeX">$\text {10}$</tex-math></inline-formula> kW industrial motor-integrated VSD. For a state-of-the-art d<inline-formula><tex-math notation="LaTeX">$v$</tex-math></inline-formula>/d<inline-formula><tex-math notation="LaTeX">$t$</tex-math></inline-formula>-limitation of up to <inline-formula><tex-math notation="LaTeX">$\text {6}$</tex-math></inline-formula> V/ns the LC-filter shows lower losses compared to the GD-based limitation. The latter, however, has a higher part-load efficiency and/or lower losses compared to the (roughly) load independent losses in the LC-filter resulting from the dissipation of the energy stored in the filter capacitor within each switching cycle, beneficial for light loads, e.g., <inline-formula><tex-math notation="LaTeX">${< 40}\,$</tex-math></inline-formula>% of rated output power. Next-generation motors with reinforced insulation allow a d<inline-formula><tex-math notation="LaTeX">$v$</tex-math></inline-formula>/d<inline-formula><tex-math notation="LaTeX">$t$</tex-math></inline-formula>-limitation of up to <inline-formula><tex-math notation="LaTeX">$\text {15}$</tex-math></inline-formula> V/ns. In this case, the GD-based limitation shows lower losses in the whole operating range, since they directly scale with the now smaller overlap of voltage and current resulting from the faster switching transitions. Considering a state-of-the-art motor, finally, a hardware demonstrator of a three-phase VSD employing an LC-filter to limit the d<inline-formula><tex-math notation="LaTeX">$v$</tex-math></inline-formula>/d<inline-formula><tex-math notation="LaTeX">$t$</tex-math></inline-formula> to <inline-formula><tex-math notation="LaTeX">$\text {5.6}$</tex-math></inline-formula> V/ns is realized, which achieves a full inverter stage power density of <inline-formula><tex-math notation="LaTeX">$\text {30}$</tex-math></inline-formula> kW/dm<inline-formula><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> (<inline-formula><tex-math notation="LaTeX">$\text {497}$</tex-math></inline-formula> W/in<inline-formula><tex-math notation="LaTeX">$^\text {3}$</tex-math></inline-formula>) and an inverter efficiency of <inline-formula><tex-math notation="LaTeX">$>\! \text{99}\,$</tex-math></inline-formula>%.


I. INTRODUCTION
Between 40 % and 50 % of the global energy consumption is attributed to electric motor-driven systems [2], [3], primarily in industrial applications, which motivates an investigation of improvements in energy conversion efficiency, in particular of three-phase VSD inverter systems. In the multi-kW range, state-of-the-art inverters are typically composed of Si IGBTs with antiparallel freewheeling diodes and are operated at switching frequencies in the range of several kHz to several tens of kHz [4], [5]. SiC MOSFETs are offering an interesting alternative for next-generation VSDs, since they contain internal diodes, hence omitting the need of dedicated external freewheeling diodes, and in contrast to IGBT power devices they do not exhibit a constant forward voltage drop in the onstate, hence offering significantly reduced conduction losses, which is of particular advantage for part-load operation that often contributes a major share in typical mission profiles of electric motors [6]. Thanks to their high switching speed (high dv/dt and high di/dt) and the significantly lower reverse recovery charge of the internal freewheeling diodes, for the same conduction losses, SiC power semiconductors have a significantly smaller chip area and therefore, lower switching losses [7]. For a given loss budget they can thus be operated at a higher switching frequency up to hundred kHz or more [8], which reduces the required capacitance / size of the DC-link capacitor and increases power density. A minimized functional volume, i.e., a high power density, is particularly important for ever-more popular Integrated Motor Drives (IMDs) where the VSD is placed inside the machine housing and thus must be realized as compact as possible due to space restrictions [9]. A further advantage of IMDs is the absence of long motor cables, which on the one hand are expensive and heavy and on the other hand already for relatively low voltage transition rates of the switched PWM output voltage lead to transmission line effects, e.g., voltage reflections and ringing [10] that increase the insulation stress due to overvoltage at the machine terminals.
A higher switching frequency and accompanying lower volume, however, increases the loss density of the inverter system. Given that typical electric motors have efficiencies in the range of 90 − 95 %, a required inverter efficiency of typically > 99 % for IMDs is dictated by the thermal design in order to safely dissipate the losses, more than by the overall system efficiency, which is clearly dominated by the motor.
The high switching speed (in particular the high dv/dt) of 20 . . . > 50 V/ns occurring in SiC MOSFETs imposes various challenges, for example, said transmission line effects typically occurring in state-of-the-art IGBT VSDs with long motor cables can now also occur in IMDs, i.e., even without motor cables [11], [12]. These effects mainly result in an uneven voltage distribution (coil-to-coil and turn-to-turn) within the machine winding, which can drastically reduce the lifetime of the insulation, e.g., due to partial discharge and/or accelerated insulation aging [9], [13]. Moreover, the Common Mode (CM) voltage components with a high dv/dt lead to high bearing currents that reduce the bearing lifetime [14]. While a full sinewave filter would address the aforementioned challenges and thanks to the increased switching frequency in next-generation SiC-based VSDs may be more attractive to implement, it would still significantly impair the inverter power density and would also be a major cost driver. Therefore, it is desired to only implement the absolutely minimum necessary filtering, i.e., to only limit the fast dv/dt voltage transients applied to the motor (a Permanent Magnet Synchronous Motor (PMSM) in the case at hand), e.g., by means of a single-stage LC-dv/dt-filter [15], [16], as shown in Fig. 1. Considering according standards [17], [18], the dv/dt-values (voltage slew rate; measured between 10 % and 90 % of V DC and vice versa) of industrial inverter systems are typically limited to 3 . . . 6 V/ns in order to restrain the aforementioned detrimental effects. However, next-generation electric machines with reinforced motor insulation are projected to FIGURE 1. Three-phase Variable Speed Drive (VSD) inverter system employing latest SiC MOSFETs that achieve a dv/dt > 50 V/ns. To protect the motor isolation, an LC-dv/dt-filter is installed to limit the voltage transition rates to typically 3 . . . 6 V/ns for state-of-the-art motors [1]. The filter capacitor C f for each phase can be referred to the negative (and/or positive) DC-link rail (dashed line) and thereby the filter is effective for limiting the dv/dt of differential-mode (DM) and common-mode (CM) inverter output voltage components. The additional CM choke L CM further limits the CM currents through the bearings arising from the typically relatively large CM capacitance C CM of the machine and moreover reduces radiated electromagnetic emissions.  [1]. It should be noted that there are also concepts to directly mitigate the overvoltage at the machine terminal and/or the unequal voltage distribution across the winding coils inside the machine by means of small auxiliary circuits in parallel to the first few turns ("smart coils") [19]. These solutions, however, need careful tuning for each specific machine and require additional active components (switches) with driving circuitry.
This article focuses on the two most promising dv/dtlimitation concepts on the VSD side, namely a passive LC-dv/dt-filter employing a single stage LC-filter with diodeclamped damping network (DRC damping) [20], [21] as well as a GD-based dv/dt-limiting concept featuring a Miller feedback capacitor in combination with increased GD resistances [22], [23] for the exemplary case of a 10 kW three-phase IMD employing SiC power semiconductors with the specifications listed in Table 1. It answers the question, which concept is better suited in terms of efficiency and power density for two distinct maximum dv/dt-values of 5 V/ns for state-of-the-art motors and 12 V/ns for future motors and different load scenarios (full-load or part-load operation) by theoretical and experimental validation. The switching frequency of f sw = 16 kHz is just above the audible range and is selected to minimize the switching losses and to facilitate direct comparison to state-of-the-art VSDs implemented with IGBTs.
Section II explains the two considered dv/dt-limiting concepts before Section III introduces the accompanying tradeoffs in terms of losses and functional volume. Section IV then analytically compares the two concepts for different dv/dtvalues and load conditions and derives a boundary to select the better-suited concept depending on the operating conditions. The calculations are experimentally verified for both investigated concepts and a three-phase VSD inverter system realization suitable for motor integration is presented. Finally, Section V concludes the article.

A. LC-FILTER BASED dv v/dt-FILTER
Passive LC-dv/dt-filters are composed of a filter inductor L f and a filter capacitor C f , whereas the latter is advantageously referred to the DC-link rails in order to filter CM and Differential Mode (DM) voltage components simultaneously (cf. Fig. 2(a)). The resulting phase modular nature facilitates integration, e.g., into power modules. General filter design goals are to limit the dv/dt to a certain maximum value and at the same time to limit the inductor current swing i Lu and output voltage overshoot v u * n below given boundaries. In this regard, filter damping is essential to avoid overshoot and excessive ringing of the voltage applied to the motor. In the simplest case of a series LCR-filter, damping is implemented with a resistor R f in series with C f (cf. Fig. 1) [24], [25], such that the oscillatory transition excited by each switching pulse quickly decays to the steady state, i.e., v u * n = V DC and i Lu = i u . The drawback of this approach is the dependency of the resultant voltage rise time not only on the filter resonance frequency ω 0 = 1/ √ L f C f but also on the selected quality factor Q = R f /Z f (characteristic filter impedance Z f = √ L f /C f ) that also defines the overshoot and is therefore difficult to calculate [1]. Diode-clamped damping networks (DRC damping) [20], [21] as shown in Fig. 2(a) advantageously decouple the dv/dt and the damping. The desired dv/dt defines the voltage transition rise time t R0 and fall time t F0 (10 % to 90 % of V DC and vice versa) with and thanks to the disconnected damping network for 0 < v u * n < V DC is solely defined by the resonance formed with L f and C f (cf. characteristic waveforms in Fig. 2 Therefrom, the rise time results and finally, the dv/dt can be analytically described as with := arccos(0.1) − arccos(0.9) ≈ 1.02. It therefore only depends on L f and C f , which have to be selected accordingly. Considering that the filter is loaded with the motor (i.e., its input impedance in case of an IMD) or even with the motor cable + motor, the filter characteristic becomes loaddependent. It is very difficult to generalize such a setup due to the large variety of different motors and cables. In the case at hand we focus on an IMD (no motor cable) for the PMSM 1FT7084 from Siemens [26], which is a typical example for an industrial 10 kW drive system with specifications as listed in Table 1. In order to be largely independent of the machine loading, the filter output impedance Z o,f must be smaller than the machine input impedance in the frequency range of interest for the considered dv/dt, i.e., around the filter resonance frequency f 0 = ω 0 /(2π ) [1]. In a typical modulation scheme, only one bridge-leg is switched at a time, which leads to the same voltage step applied to the machine regardless of the switching state changes, i.e., always one phase is switched from 0 V to V DC (or vice versa), while the other two terminals are assumed to be clamped to the negative (or positive) DC-link rail and in addition, considering the worst-case of a direct connection of the negative DC-link rail with PE, i.e., a shorted C Y2 (cf. Fig. 1), also to PE. Therefore, the machine impedance seen between, e.g., terminal u and shorted terminals v, w, and PE (case) (Z U−VWPE ) has to be evaluated and impedance measurements reveal that in the relevant frequency range the PMSM behaves like a capacitance of around 300 pF (cf. Appendix). Thus, in order to ensure Z o,f < Z U−VWPE with the worst-case assumption that Z o,f is solely defined by C f , C f ≥ 1 nF is selected (three times larger value). While the semiconductor losses remain unaffected by placing an LC-dv/dt-filter (they still switch with a very high dv/dt in the range of 20 . . . 50 V/ns), the filter capacitor C f needs to be charged and discharged once every switching period. This translates into an energy loss E C = 2 · 1 2 C f V 2 DC , independent of the switched current, which is dissipated mainly in the resistors of the damping network. It is thus advisable to select the minimum possible C f to minimize the filter losses. For a given C f the filter inductance L f directly follows from the desired dv/dt using (4), e.g., a dv/dt of 5 V/ns and 12 V/ns requires L f = 14 µH and L f = 2.4 µH, respectively, for C f = 1 nF and V DC = 800 V. The filter losses are dissipated in the damping resistors R p and R n (cf. Fig. 2(a)), which are selected to achieve critical damping (Q = 0.5). The additional capacitors C p and C n in parallel to the respective damping resistors do not influence the filter losses but reduce the voltage overshoot v u * n at the cost of a prolonged discharging time, as indicated with the dim curves in the characteristic waveforms of Fig. 2(b). The filter inductors must be designed for a peak current i L,pk =î u + i Lu , with the phase current amplitudê i u and the inductor current swing i Lu = V DC /Z f to charge C f . Fig. 3(a) exemplary shows the required components to implement one slew-rate limited bridge-leg of the three-phase VSD with a dv/dt-limitation of 5 V/ns realized by means of a passive LC-filter employing DRC damping.

B. GATE DRIVER BASED dv v/dt-LIMITATION
The apparent drawback of a passive dv/dt-limiting filter is the additional volume and cost of the filtering elements (though, they are considerably smaller compared to a full sinewave filter). Alternatively, the dv/dt of the voltage applied to the machine can be limited directly via the GD voltage, which only requires very small passive elements and therefore, has a negligible contribution to the component volume, as depicted in Fig. 3(b). Different realizations either limit the gate time constant, e.g., by using different gate resistance values [27], [28], [29] or by implementing closed-loop gate control [30], [31]. An alternative implementation not only modifies the gate time constant but also artificially increases the gate-to-drain capacitance C GD of the MOSFET with an external so-called Miller capacitance C M between drain and gate (in the range of few pF, hence very small) as shown in Fig. 2(c), to inherently slow down the dv/dt transient and thereby potentially gains advantages in terms of losses. A detailed analysis of the resulting MOSFET turn-on and turn-off transitions is carried out in [23] and reveals that both are equally slowed down by the combination of gate resistance R G and C M . This is indicated in Fig. 2(d), which shows a zoomed view of one switching period T sw during the fundamental frequency period T E = 1/ f E where the momentary phase current i u (and thus switched current) is negative (i u in Fig. 2(c) indicates the physical current direction).
The slowed down voltage transitions lead to a voltagecurrent overlap and hence to increased switching losses. The additional overlap losses in the (ideally lossless) turn-off transition (during t R0 for a negative switched current of the low-side transistor T L ) have been comprehensively discussed in [22] and are attributed to the voltage-current overlap resulting from a residual current in the channel of T L while its C GD , C M and the drain-to-source capacitance C DS are charged (and the high-side transistor T H 's C DS , C GD and C M are discharged). Assuming for simplicity no external Miller capacitor (C M = 0 pF) and a certain switched current i u , the resonant Zero Voltage Switching (ZVS) transition would charge C GD of T L with a current i C GD determined by the current divider C GD /(C DS + C GD ) (and similarly charge C DS of T L with a current determined by C DS /(C DS + C GD )), which together with the current discharging the gate-to-source capacitance C GS equals the total gate current i G . The latter is limited to i G,max = (v th + |V GD,n |)/R G,off by the GD as a function of the MOSFET threshold voltage v th , the negative GD voltage V GD,n and the turn-off gate resistance R G,off (composed of the externally placed resistance and a GD-internal part representing the limited current drive capability). For switched currents above a certain limit I k (the so-called "kink" current [22]) and considering only the capacitive current divider, i C GD would need to exceed i G,max , which is not possible. Therefore, a certain residual current (i u − I k ) continues to flow in the MOSFET channel, causing said overlap losses. As derived in [22], the limit I k is defined as the switched current i u = I k that is entirely split between C GD (and C M in parallel) of T L and the parallel combination of C DS of T L , C DS of T H and C GD and C M of T H (current divider) and where i C GD = i G,max , i.e., assuming a very high MOSFET transconductance g m . To account for the non-linear capacitances C DS and C GD with changing voltage, C dQ,DS and C dQ,GD denote the chargeequivalent linear capacitances for a voltage change between 10 % and 90 % of V DC (or between 90 % and 10 % of V DC ), i.e., the voltage range v = 0.8 · V DC in which the dv/dt is evaluated. The factor of two in (5) accounts for the charging/discharging of C DS , C GD and C M of the highside and low-side transistors during the ZVS transition.  Table 2), which accounts for ≈ 24 % and ≈ 70 % of the phase current amplitude at full output power (cf. (11)). Therefore, it is important to consider the effect of I k on the resulting semiconductor losses as it is done in Section III-C. From I k follows now directly the desired reduced turn-off voltage transition rate (straight-line approximation) as further derived in [22] and again using the chargeequivalent capacitances. Moreover, C par includes various parasitic capacitances, e.g., from the PCB layout or the heat sink.
Combining (5) and (6) and neglecting C par , the simplified expression results. Equation (7) clearly illustrates that for a given GD supply voltage, the dv/dt is defined by the product of GD resistance and (total) Miller capacitance and therefore, multiple combinations result in the same dv/dt. Note that (5) to (7) assume C M and C GD connected in parallel, i.e., the internal gate resistance of the power semiconductor is assumed zero. Furthermore, it has to be noted that the dv/dt in (7) slightly increases for switched currents i u > I k , since the gate-to-source voltage during the voltage transition equals the Miller-plateau voltage v M = v th + (i u − I k )/g m (MOS-FET transconductance g m ), slightly raising the maximum possible gate current and thus accelerating the charging of C GD and C M . Given the typically very high g m of power MOS-FETs (g m = 53 S for the device used here, C3M0016120K, cf. Table 2) this effect is not significant. The turn-on transition of T L (during t F0 in Fig. 2(d)), again assuming a negative phase current and thus a negative switched current i u , is a Hard Switching (HSW) transition, which causes overlap losses, because after turn-off of the high-side switch T H , i u commutates in its freewheeling diode, i.e., V DC remains across the low-side transistor T L , and only after an enforced dead time i u commutates to the channel of T L (turn-on of T L ). With increasing gate resistance and/or Miller capacitance the maximum current to charge C GD (and C M ) of T H and to discharge C GD (and C M ) of T L is limited by the GD resulting in increased overlap losses due to the desired slowed down turn-on voltage transition with the positive GD drive supply voltage V GD,p and the turnon gate resistance R G,on .
Resulting from (7) and (8), a certain dv/dt can be achieved with different combinations of R G,on and R G,off and C M , for example a slew rate limit of 10 V/ns could be achieved with C M = 50 pF, R G,on = 9.5 and R G,off = 11.0 or with C M = 0 pF (only the device-internal C GD is effective), R G,on = 30.1 and R G,off = 24.3 [23]. Measurements in [23] show, however, that the losses do not significantly change for different combinations, thus in the interest of simplicity, C M = 0 pF can be chosen and the dv/dt is set entirely with the GD resistance. Actual dv/dt, R G,on , R G,off and C M values for the utilized system are indicated in Table 2. Note that changing the gate resistance directly changes the gate time constant τ GS,on = R G,on · C GS (and τ GS,off = R G,off · C GS ), which influences the time for the gateto-source voltage to rise from the threshold voltage v th to the Miller-plateau voltage v M = v th + i u /g m during the turn-on transition (and vice versa to fall from the Miller plateau to v th during the turn-off transition) and therefore leads to a finite current slew rate di/dt (indicated in Fig. 2(d)). Calculations with the utilized device parameters (cf. Table 2) verify that the current rise and fall times are still more than one order of magnitude faster compared to the voltage transition times t R0 and t F0 and are hence neglected.

III. LOSS AND VOLUME CALCULATION
Both presented dv/dt-limiting concepts cause additional losses, either due to capacitor charging/discharging (filter capacitor C f of the LC-dv/dt-filter) or overlap losses (GD-based limitation), and further contribute a certain volume, e.g., of additional passive elements and of the required heat sink to dissipate the additional losses. Since the goal is to select the best-suited dv/dt-limiting approach based on loss and volume considerations, approximative quantitative loss and volume models are derived in the following. It is important to discriminate the additional losses/volumes caused by dv/dt-limiting concepts from losses that are inherently present, including the capacitive losses occurring due to charging/discharging of the parasitic machine capacitances. These losses act as loss offset and in a first approximation are assumed to not change if the voltage slew rate is limited by either of the concepts.

A. INVERTER OUTPUT POWER
At rated mechanical rotational speed n M = 4000 rpm (ω M = 2π · n M /60 = 2π · 67 Hz) and with the voltage constant k V = V ll,rms n M = 83 mV/rpm and p = 5 pole pairs [26], the induced motor winding (phase) voltage has an amplitudev ind and an electrical angular frequency ω in accordance with [1]. The resulting maximum phase current amplitude at full power (P M,max = 10 kW), i.e., at full torque of T M,max = 23.8 Nm, iŝ with the machine torque constant k T = T M I l,rms = 1.3 Nm/A [26]. Typical mission profiles of industrial drive systems are largely containing part-load operation, e.g., a reduced nominal torque of T nom = 0.8 · T M,max = 19 Nm (î u,nom = 20.7 A) at nominal rotational speed, which justifies investigation of the optimally suited dv/dt-limiting concept for such a part-load case. Unsurprisingly, combining (9) with (11) results in the maximum mechanical output power of P M,max = 10 kW and when using T M,nom instead of T M,max , in P M,nom = 8 kW. The output power of each inverter phase can be expressed with where MV DC /2 denotes the amplitudev u of the inverter phase output voltage (modulation depth M). Assuming the load current to be in-phase with the induced motor voltage v ind , in a complex phasor representation, the projection of the inverter output voltage phasorv u on the real axis, i.e., v u · cos(ϕ), corresponds to the induced motor voltagev ind . According to (9), the amplitude of this projected voltagê v ind = MV DC /2 · cos(ϕ) is directly related to the rotational speed and thus constant and load-independent (typically, there is a superordinate speed controller that regulates n rpm to the desired value). For n rpm = 4000 rpm and the given machine parameters [26], M cos(ϕ) = 0.68 [1] and therefrom P u can be calculated straight-forward.

B. LOSSES AND VOLUME OF THE PASSIVE LC-dv/dt-FILTER
In a passive LC-dv/dt-filter the power semiconductors themselves are switching with a typically very high dv/dt and switching loss models obtained from device characterization (e.g., thermally measured [32]) with quadratic fitting coefficients k 0 , k 1 and k 2 can be used. For a purely sinusoidal switched current, i.e., no current ripple (justified with the relatively large machine inductance), the semiconductor losses per phase (half-bridge losses P l,HB ) for a certainî u then equal C3M0016120K 1200 V SiC power semiconductors (R DS,on = 16 m at T j = 25 • C) are found to minimize the total semiconductor losses (conduction and switching) in the given application with part-load operation at P M,nom = 8 kW (î u = 20.7 A) [1]. Their calorimetrically measured switching loss coefficients are k 0 = 312.2 µJ, k 1 = 7.2 µJ/A and k 2 = 120.8 nJ/A 2 (cf. Table 2). A junction temperature T j = 100 • C is assumed to calculate the conduction losses, i.e., R DS,on,100 • = 20 m [33]. Additional loss components are the charging/discharging losses P C f = C f V 2 DC f sw of the filter capacitance C f , which are dissipated mainly in the resistors of the DRC damping network, and the filter inductor conduction losses P L f = 1 2 R L fî 2 u (neglecting core losses due to the low fundamental frequency and the generally low current ripple given the large motor winding inductance; further neglected are hence the conduction losses arising from the current ripple and the contribution of the current pulse i Lu to the total RMS current, which is found to be negligible). In total, the per-phase losses of a bridge-leg featuring a passive LC-dv/dt-filter are Neglecting the filter capacitor volume (high capacitance density), only the volume of the heat sink to dissipate the filter losses and the filter inductor volume have to be considered. The former can be approximated using the so-called Cooling System Performance Index (CSPI) [34] with a typical CSPI of 20 W/(K · dm 3 ), an assumed heat sink temperature of ϑ HS = 85 • C and an ambient temperature ϑ amb = 40 • C using As derived in Section II-A, the filter inductance directly follows from the selected dv/dt limit. For the given application the maximum phase RMS current equals I u,rms,max = 18.3 A and the peak current follows fromî u,max in (11) and the additional current peak i Lu to charge C f . Even though the VSD is primarily operating in part-load, the filter inductor has to be designed for full-load, i.e., for an RMS current rating I rated ≥ I u,rms,max (as mentioned above, the contribution of the current pulse i Lu on the total RMS current is found to be negligible) and for a saturation current i sat ≥î u,max + i Lu . The dots in the ηρ-Pareto optimization in Fig. 4 show the design trade-off for the LC-dv/dt-filter for dv/dt limits between 3 V/ns and 15 V/ns with the total VSD power density ρ and the part-load efficiency η 8 kW at P M,nom = 8 kW. The filter capacitance C f is fixed to a value of 1.12 nF (two 560 pF capacitors in parallel, connected to the positive and negative DC-link rail) a) to fulfill the filter output impedance criterion (Z o,f < Z M,U−VWPE ) and b) to minimize the (load independent) losses P C f . Generally, high dv/dt limits are accompanied by a higher power density due to the smaller L f . At the same time, a low L f results in lower conduction losses P L f , hence also the efficiency improves (the other loss components in (14) are independent of the selected dv/dt limit). For IMDs, ideally the design with the highest power density is chosen to facilitate integration (highlighted with black circles for each dv/dt).

C. LOSSES AND VOLUME OF THE GATE DRIVER BASED dv/dt-LIMITATION
The GD-based dv/dt limitation leads to increased switching losses E sw,GD , which for a switched current i u have been derived in [23] as with k on = k WF 2 V 2 DC / dv dt and k off = 1 2 V 2 DC / dv dt . The factor k WF = 1.35 is empirically determined and corrects inaccuracies due to the straight-line approximation of the voltage transient between 10% and 90% of V DC , only of a concern for the turn-on transition [23]. Note that the term k 2 considering losses scaling quadratically with the switched current is neglected, since the linearly scaling loss contribution arising from the limited dv/dt is clearly dominating the overlap losses. Moreover, the ZVS losses attributed to the resonant charging/discharging of the transistor output capacitance C oss = C DS + C GD are neglected.
Evaluating (17) for a sinusoidal phase current with amplitudeî u , including the semiconductor conduction losses and again neglecting the current ripple, the total per-phase losses P l,GD for the GD-based dv/dt-limitation are where the values of I k for the two cases with a dv/dt-limitation of (I) 5 V/ns and (II) 12 V/ns are listed in Table 2. For a givenî u , P l,GD scales inversely proportional with the selected voltage slew rate dv/dt, which is intuitively clear that faster voltage transients lead to lower overlap losses.
Since the volume of the gate resistor and additional Miller capacitor is negligible (cf. Fig. 3(b)), consequently, only the heat sink volume has to be considered, which can be calculated with (15) and (16), replacing P l,f with P l,GD (cf. Fig. 7). The squares in Fig. 4 nicely show the trend of higher efficiency at higher voltage slew rates. Moreover, given the direct relation between losses and (heat sink) volume, there is no Pareto front and/or Pareto-optimal design but more efficient designs are automatically more compact. If no dv/dt-limiting would be employed, the losses would be solely defined by the characteristics of the utilized power semiconductor (conduction and switching losses P l,HB according to (13)) and for the given specifications result in an efficiency limit of η max,8 kW = 99.6% (indicated with the dashed line in Fig. 4) to which the GD-based dv/dt-limiting approach converges for very high slew-rate limits.

IV. COMPARATIVE EVALUATION
Having defined the inverter loss and volume models considering both dv/dt-limiting approaches, the question therefore arises, which of the two concepts should be selected to limit the dv/dt of a three-phase VSD inverter system with a certain phase current amplitudeî u to a specific value (e.g., 5 V/ns for state-of-the-art electric motors or 12 V/ns for future motors with reinforced insulation). To not only theoretically but also experimentally verify the analyses, a characteristic three-phase SiC-based VSD to be integrated into a motor housing is designed and constructed as depicted in Fig. 5, in accordance with the specifications from Table 1. The VSD is equipped with a DRC-damped passive LC-filter for dv/dt-limitation but could alternatively also be realized without the filter as GD-based dv/dt-limitation. Two PCBs are vertically stacked to facilitate a compact and phase-modular realization. On the power PCB, besides the power semiconductors (16 m , 1200 V SiC MOSFETs), the LC-dv/dt-filter as well as voltage and current measurements are located. Table 2 [35]. Moreover, the control board -currently placed as external module and included in the boxed volume -could

FIGURE 6. Per-phase losses of the loss-optimal dv/dt-limiting concept for a dv/dt-limit between 3 V/ns and 15 V/ns and phase current amplitudeŝ i u ∈ [0 A, 25 A] (part-load and full-load operation). The thick black line depicts the boundary below which the LC-dv/dt-filter has lower losses compared to the GD-based limitation. In case of the LC-dv/dt-filter, C f = 1.12 nF and L f is always chosen forî u = 25.9 A (full-load).
be fully integrated, enabling a pure inverter power density of roughly 61 kW/dm 3 (1000 W/in 3 ).

A. PER-PHASE LOSS COMPARISON
To promote motor integration of the inverter, the most compact design of the LC-dv/dt-filter is selected from the Pareto front in Fig. 4. Compared to the most efficient (lowest loss) design, the loss penalty is relatively low, whereas considerable volume benefits are apparent. Hence, a single Pareto-optimal filter design results for each dv/dt value for the damped LC-dv/dt-filter approach (highlighted with black circles in Fig. 4), which is compared to the GD-based limitation in terms of per-phase losses. Fig. 6 shows the calculated per-phase losses for both limiting approaches under full-and part-load operation (î u ∈ [0 A, . . . , 25 A] with the LC-dv/dt-filter always designed forî u =î u,max = 25.9 A) for different voltage slew rates dv/dt from 3 V/ns to 15 V/ns. For each combination ofî u and dv/dt, the losses of the better-performing approach are depicted. There exists a clear boundary between the LC-dv/dt-filter and the GD-based limitation (thick black line), where the former is best-suited for slow transitions at highî u and the latter is ideally used for higher dv/dt values. In particular for dv/dt > 11 V/ns the GD-based limitation leads to lower losses (< 25 W per phase) for full-and partload operation. For lower dv/dt values there exists a certain boundary current amplitudeî B below which the GD-based dv/dt-limitation outperforms the LC-dv/dt-filter thanks to its lower part-load losses, e.g.,î B,5 V/ns = 10.5 A for a voltage slew rate dv/dt = 5 V/ns, since the filter has always a constant loss offset of P C f = 11.5 W for C f = 1.12 nF, V DC = 800 V, f sw = 16 kHz (dominant over the inductor conduction losses P L f ). Conversely, for part-load operation withî u,nom = 20 A, the LC-dv/dt-filter outperforms the GD-based limitation for voltage slew rates below 9 V/ns because the losses of the latter scale inversely proportional to the dv/dt and thus exceed the constant P C f losses of the former. Therefore, in theory, a boundary line parametrizationî B,dv/dt = α · dv/dt with α = const. would be expected. The deviation from this linear relation results from the selection of discrete filter inductors from commercially available components, which leads to discontinuities in the LC-dv/dt-filter losses.

B. PER-PHASE VOLUME COMPARISON
A similar boundary is found in Fig. 7 when comparing the functional volume of the two limiting concepts (blue and orange lines for the LC-dv/dt-filter and GD-based limitation, respectively) for the maximum phase current amplitudê i u,max = 25.9 A (part-load operation does not change the volume, since the VSD must be designed to handle the full power of P M,max = 10 kW). For voltage slew rates above 9.4 V/ns the GD-based dv/dt-limitation can be realized with a lower volume (i.e., lower heat sink volume due to the lower losses with the direct relationship via the CSPI, cf. (16)), whereas in case of the LC-dv/dt-filter there is always a certain volume offset given by the filter inductors, which of course can be realized more compact for small inductance L f (high dv/dt), but the volume reduction saturates due to mechanical constraints (current carrying conductors, minimum core thickness, etc.). The discontinuities in case of the LC-dv/dt-filter again result from discrete component selection.

C. EXPERIMENTAL VERIFICATION
To experimentally verify the occurrence of the above discovered boundary, the occurring per-phase losses have been measured on the hardware prototype equipped with either of the two described dv/dt-limiting concepts. The LC-dv/dtfilter is realized with C f = 1.12 nF (two R76QF056050H0J capacitors in parallel, one connected to the positive and one to the negative DC-link rail) and L f = 11.2 µH (two SRP1770TA-5R6M inductors in series) or with C f = 1.12 nF and L f = 1.8 µH (CMLS136E-1R8MS) for a nominal dv/dt of 5.6 V/ns and 14 V/ns, respectively. Note that realizing C f with two capacitors connected to the positive and negative DClink rail does not influence the total energy dissipation, but results in a more symmetric layout and thus more symmetric (parasitic) ringing conditions. In both cases (dv/dt of 5.6 V/ns and 14 V/ns), the damping network is composed of two 10 nF capacitors C p and C n and implements critical damping with R p = R n = 1 2 L f C f +C p (C p denotes the additional damping capacitance in parallel to the damping resistor, cf. Fig. 2(a)). SiC Schottky diodes with low capacitive charge (24 nC, ≈ 0.3 W losses for V DC = 800 V and f sw = 16 kHz) and low leakage current (12 µA) are used for D p and D n (IDM05G120C5). Due to component tolerances, additional parasitic capacitances and inductances (PCB, connections), finally, the desired voltage slew rates of 5 V/ns and 12 V/ns result (cf. Table 1). Note that for a smaller L f (higher dv/dt) the impact of parasitic inductances and capacitances is more pronounced (larger deviation of the actual dv/dt from the nominally set value) due to the small nominal value of L f .
The GD-based limitation is implemented with increased gate turn-on and turn-off resistances of R G,on /R G,off = 56 /43 and 15 /15 (C M = 0 pF) for a dv/dt of 5 V/ns and 12 V/ns, respectively (cf. Table 2). Using (5) with v th = 2.5 V, V GD,n = −4 V, C dQ,DS = 320 pF and C dQ,GD = 16 pF the "kink" current is I k = 6.3 A (5 V/ns) and I k = 18.2 A (12 V/ns) for the two cases. Fig. 8 shows (a) the calculated and measured efficiency and (b) the per-phase losses for dv/dt = 5 V/ns (calculated: dotted lines; measured: circles) and for dv/dt = 12 V/ns (calculated: continuous lines; measured: diamonds) for the LC-dv/dt-filter (blue) and the GD-based limitation (orange) for phase current amplitudesî u = {5 A, 10 A, 15 A, 20 A, 25 A}. These operating points are also indicated in Fig. 6. The losses are measured electrically with a precision power analyzer (Yokogawa WT3000) and show good alignment with the calculations, in particular in case of the GD-based limitation, whereas in case of the LC-dv/dt-filter and for lowî u a certain mismatch is observed. This is primarily explained with the simplified assumption of zero current ripple in the calculation, essentially overestimating the switching losses at low currents (and hence the calculated total losses), since in practice more Partial-Hard Switching (PHSW) and Soft Switching (SSW) transitions occur, which generate lower losses compared to the assumed HSW transitions. In case of the GD-based limitation this effect is less severe, since also the PHSW and SSW transitions lead to overlap losses (forî u > I k ).
As expected from the observations in Fig. 6 based on calculated losses, for a dv/dt of 12 V/ns the GD-based limitation is always more efficient (lower losses) compared to the LC-dv/dt-filter, e.g., for the nominal phase currentî u,nom = 20.7 A the measured losses are 20.5 W with the GD-based limitation and 23.6 W with the LC-dv/dt-filter. For a voltage slew rate dv/dt = 5 V/ns, the boundary currentî B,5 V/ns is verified, i.e., for currentsî u > 10.5 A the LC-dv/dt-filter has lower losses than the GD-based limitation (27.6 W versus 36 W forî u,nom ). The filter losses do not significantly change between dv/dt = 5 V/ns (32.3 W forî u,max = 25.9 A, i.e., η = 99.18 %) and dv/dt = 12 V/ns (28.1 W forî u,max = 25.9 A, i.e., η = 99.29 %) as only the comparably low filter inductor conduction losses differ, whereas with GD-based limitation for the same current, the losses considerably increase for a low dv/dt (45.8 W for 5 V/ns and 25.9 W for 12 V/ns). This trend is also highlighted in Fig. 4 for the two exemplary voltage slew rates of 5 V/ns and 12 V/ns (thick circles / diamonds), to demonstrate that a higher efficiency (and power density) is achieved with the LC-dv/dt-filter for 5 V/ns, and with the GD-based limitation for dv/dt = 12 V/ns. A very interesting property of the GD-based dv/dt-limitation is the high part-load efficiency, since the main loss component (overlap losses) scales linearly with the switched current (and thuŝ i u and P out ), whereas the LC-dv/dt-filter has a constant loss offset P C f , which inherently degrades efficiency at low output power.
Therefore, in future traction applications allowing voltage slew rates above 10 V/ns, a GD-based dv/dt-limitation is favorably used considering full-load and part-load efficiency as well as functional volume. For state-of-the-art applications operating with low dv/dt-values of, e.g., 5 V/ns, an LC-dv/dt-filter typically offers higher efficiency and lower volume unless the required mission profile contains mainly part-load operation below 40 % of full-load (î u < 10 A), in which case also for low dv/dt-values the GD-based limitation becomes more attractive.

D. THREE-PHASE VSD OPERATION WITH dv/dt-FILTER
Finally, the three-phase with operation of the VSD depicted in Fig. 5 connected to a state-of-the-art motor (Siemens 1FT7084 [26]) is verified. Considering the power level of 10 kW and a required the dv/dt-rating below typically 6 V/ns, the dv/dt-limitation is preferably realized with an LC-filter based on the theoretical findings from Fig. 6 and according to the experimental results in Fig. 8.   9 shows the measured voltage slew rate of > 1 million rising transitions of phase u (color-coded intensity grading) with the PMSM directly connected to the output (IMD). The measured dv/dt of 4.71 V/ns is lower than the nominally set 5.6 V/ns, which in a first approximation can be explained with an additional effective capacitance C add at the filter output that influences the dv/dt according to An additional effective capacitance C add ≈ 460 pF explains the reduction of the dv/dt to 4.71 V/ns, where the machine itself contributes 300 pF as described in Section II-A, and the rest is attributed to component tolerances and impact of connections and PCB parasitics.
While it is true that the machine capacitance influences the set dv/dt and therefore, a fully machine-independent inverter and filter design is not possible, a lower than expected dv/dt is typically not critical, since it only reduces the detrimental effects of overvoltage, partial discharges and the like. At the same time, the additional losses (compared to operating the VSD without any LC-dv/dt-filter) are only defined by C f and L f and not the machine (the machine capacitance and -if present -the cable capacitance are anyway charged and discharged with the switching frequency, regardless of a dv/dt-limiting circuit). The impact of the load on the resulting voltage slew rate could obviously be minimized by increasing C f , which, however, would directly increase the filter losses. Fig. 9 further indicates the slight voltage overshoot v u * n ≈ 100 V (12.5 % for V DC = 800 V) resulting from the finite filter resonance damping with C p,n , D p,n and R p,n . Fig. 10 shows the three phase currents of the VSD demonstrating operation at full load of P M,max = 10 kW (î u =î v =î w = 25.9 A). For nominal load (P M,nom = 8 kW withî u,nom = 20.7 A), measured overall system losses of P loss,tot = 580 W and an efficiency of η nom,tot = η nom,VSD · η nom,PMSM = 93.24 % result (including the connected PMSM). Considering the nominal machine efficiency of 94 % [26], the overall VSD losses can be approximated with P loss,VSD ≈ 70 W and η nom,VSD = 99.19 %, which agrees very well with the calculations and the experimental loss measurements (cf. the highlighted point with in Fig. 8(a)).

V. CONCLUSION
SiC power MOSFETs are promising candidates to improve the efficiency and power density of electric motor-driven systems and further to promote the emerging trend of full integration of the inverter system into the motor housing. A primary advantage of SiC power semiconductors is their low specific switching losses that allow to design VSD inverter systems with considerably higher switching frequencies. This comes, however, at the expense of very fast voltage transients (high dv/dt). The voltage slew rate applied to the motor must be limited to prevent surge overvoltage, unequal voltage distribution across the windings or inadmissibly high bearing currents that all lead to accelerated aging and/or destruction of the motor. For a typical industry application of a 10 kW VSD operating primarily under part-load (80 % rated load), this article compares two approaches to limit the applied dv/dt, namely a passive LC-dv/dt-filter (single-stage LC-filter) and a GD-based dv/dt-limitation. While state-of-the-art motors demand voltage slew rates below typically 6 V/ns, future motors with reinforced insulation are forecasted to withstand a dv/dt of up to 15 V/ns, and therefore the question arises, which limiting concept is best-suited in a VSD for a certain dv/dt and phase current amplitude (full-or part-load).
The passive LC-dv/dt-filter mainly contributes a constant loss offset and low current/load dependent losses, whereas the GD-based limitation generates voltage-current overlap losses that scale linearly with output power and the voltage transition times. It turns out that the latter is best-suited for dv/dt-limits above 11 V/ns under full-and part-load operation. For each dv/dt-limit below 11 V/ns there exists a boundary for the phase current amplitude above which the LC-dv/dt-filter is preferably used, since the overlap losses of the GD-based limitation dominate the (roughly) constant losses of the filter. For part-load operation with a phase current amplitude below the boundary, however, the GD-based limitation has lower losses. In any case, it is possible to realize a VSD with an efficiency above 99 % for nominal load operation (8 kW). Similarly to the losses, the functional volume (considering the additional components as well as the required cooling to dissipate the additional losses) of the GD-based limitation is lower for high slew rates due to the lower losses compared to the LC-dv/dt-filter.
The theoretical findings are experimentally verified on an ultra-compact 10 kW tp SiC-based VSD as IMD for a state-ofthe-art PMSM, which according to the findings of this work, features a passive LC-dv/dt-filter to limit the voltage slew rate to a nominal value of 5.6 V/ns. With a power density of 30 kW/dm 3 (493 W/in 3 ) it facilitates full integration of the inverter into the motor housing. The resulting measured dv/dt (4.71 V/ns) during operation with the PMSM is about 15 % lower than the nominal value, attributed to the additional capacitive loading from the PMSM, which slightly alters the filter corner frequency. Nevertheless, a dv/dt below the critical limit is non-problematic, as it further reduces the detrimental effects arising from fast voltage slew rates, while the losses are solely defined by the actual LC-filter components. The same system for a next-generation motor with higher dv/dt-rating would preferably be realized with a GD-based limitation, which not only reduces the total losses but also comes with an additional increase in power density, since no additional passive components must be placed. For Low-Voltage (LV) MOSFETs there exist already highly integrated "smart" GDs that allow to actively (programmatically) set the voltage slew rates without influence of external parasitic effects [36] and it is very likely that in the near future similar concepts will be available for High-Voltage (HV) MOSFETs (≥ 1.2 kV blocking voltage capability).

APPENDIX
In this Appendix the considered PMSM is characterized with impedance measurements and an intuitive, physically explainable lumped-element equivalent circuit is derived to justify the capacitor selection in the LC-dv/dt-filter design. From (4) follows a filter resonance frequency range between 760 kHz and 3.8 MHz for a dv/dt-limitation range between 3 V/ns and 15 V/ns. The impact of the machine on the voltage slew rate can be quantified with a model that is valid in this frequency range. Based on impedance measurements between one machine terminal (e.g., U ) and the remaining two terminals (shorted to PE, e.g., VW PE) as depicted with the blue curves in Fig. 11, the lumped-element circuit model of Fig. 12 with indicated component values results. The first and second parallel resonances at around 130 kHz and 340 kHz, respectively, are modeled with L m1 and C p1 (damping R p1 ) and L m2 and C p2 (damping R p2 ). The damped series resonance in between is composed of the combination of the six elements. The final series resonance at around 25 MHz (not visible in the measurements of Fig. 11) is modeled with L m3 and the series connection of C p1 and C p2 (damping R m3 ). Finally, the capacitive coupling from the terminals and windings to the housing (PE) is modeled with the capacitance C p3 . Despite its simple structure and the absence of frequency dependent  machine inductances and resistances that would be required for accurate high-frequency characterization in the multi-ten-MHz range [19], this model accurately replicates the PMSM impedance in the frequency range of interest up to approximately 4 MHz (highlighted in light blue in Fig. 11). Observing the almost entirely capacitive nature of Z U−VWPE in the highlighted frequency range of interest, the approximation of the PMSM impedance as single 300 pF capacitance from Section II-A to facilitate the filter design is therefore justified. Fig. 11 further highlights the impact of a 10 m long shielded motor cable (Siemens 6FX5002-5DN56-1BA0) on the resultant impedance Z U−VWPE (measurement: yellow). For the calculation model (purple curve), the cable is treated as series of ten distributed RLC-elements with 0.35 , 154 nH, 170 pF each. In the highlighted frequency range the simplified approximation with a constant capacitance (2 nF; 1.7 nF from the 10 m cable and 300 pF from the PMSM) is clearly not valid anymore, since the first cable resonance occurs at 4 MHz, characterized by a drastic drop of the impedance. This is manifested in Fig. 13(a) that shows the simulated dv/dt of a voltage transient in one of the VSD bridge-legs compared to the set nominal values (C filt = 1.12 nF and L filt resulting from (4)) in case of the unloaded filter (no machine; blue), a connected PMSM without motor cable (orange) and a PMSM connected via a 10 m long shielded motor cable (yellow). Fig. 13(b) nicely shows that in case of a connected PMSM without motor cable the dv/dt-reduction below the set value can be explained with the additional effective machine capacitance of 300 pF calculated according to (19). If in addition a 10 m long motor cable is added, the resulting "cable-PMSM"-behavior is not purely capacitive anymore in the frequency range of interest, and the calculated additional capacitance to get the dv/dt from the yellow curve in Fig. 13 (a) is larger than the theoretical 2 nF (cable + PMSM) due to the "cable-PMSM" resonance that is located close to the filter resonance frequency. In any case, the dv/dt is always lower than the nominally set value and therefore allows safe operation of the machine.