Model Predictive Control for Single-Phase Switched-Capacitor Multilevel Inverters

Single-phase switched-capacitor multilevel inverters are an excellent alternative for low-power applications as they provide high voltage gain. However, their control and modulation are not simple due to the particularity of these topologies. Finite Control-Set Model Predictive Control (FCS-MPC) has therefore emerged as an attractive control alternative for these inverters. This article seeks to establish guidelines for the implementation of FCS-MPC in this type of inverter. To that end, FCS-MPC is implemented in two topologies that have previously been described in the literature as well as in a new topology. The results establish excellent methodological guidelines for applying FCS-MPC in this family of inverters, that achieve high dynamic responses.


I. INTRODUCTION
Multilevel inverters (MLIs) are widely applied to renewable energy sources [1], motor drives [2], and micro-grid applications [3] due to their numerous benefits like high power quality, the low voltage rating of the switches, and their ability to handle low-switching frequencies, etc. [4], [5]. In general terms, there are three classical configurations for MLIs: neutral point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) configurations [6], [7], [8]. These three configurations can be divided into three classes: switched DCsource MLIs (SDC-MLIs) like CHB-MLI, switched-diode MLIs (SD-MLIs) like NPC-MLIs, and switched-capacitor MLIs (SC-MLIs) like FC-MLIs. The limitation of SDC-MLIs is that they require multiple independent DC voltage sources that rely on multiple DC-DC inverters or a big transformer. The weakness of SD-MLIs is their use of multiple discrete diodes, which limits their operation in low power factors. The drawback of SC-MLIs is that they require several capacitors to achieve balanced voltage control [9], [10], [11], [12]. Among all types of the aforementioned topologies, switched-capacitor multilevel inverters have recently become popular among researchers for low-power applications since they use only one or few DC voltage sources [12], [13].
Furthermore, with a good design of the SC-MLI topology, they can boost the input dc-link voltage and self-balance the capacitor voltage. This family of MLIs, like other topologies (SDC-MLI and SD-MLIs), suffers from a high number of components (switching devices) and also capacitors to generate more voltage levels [14]. Additionally, some of the presented SC-MLI topologies require a proper algorithm to balance the capacitor voltage, which makes them more sophisticated and costly [15]. [16], [17] have been offered as five-level topologies for SC-MLIs. [16] utilizes six switches and two extra diodes, which cannot be extended as a generalized topology to generate more voltage levels. The suggested topology in [17] to generate five levels needs more additional bidirectional switches than in [16], which increases the conduction losses due to the active one diode and one IGBT in on-state mode. Presented topologies [18], [19] use a high number of switches, eight, to make seven levels. In addition, they need a high number of capacitors, four, which increases the power losses and the cost of the inverter. Three sevenlevel SC-ML topologies have been introduced in [20], [21], [22] using a small number of power switches. Nevertheless, these inverters employ three or more capacitors, except for [22], which uses two. [21] can not boost the voltage, and [22] has high voltage stress on the switches, which affects the power loss and cost of the inverter. [23], [24], [25], [26], [27] have developed SC-MLIs that can boost the output voltage and charge the capacitors in a self-balancing mode, but they need a high number of power switches, ten, some of them are bidirectional. As a result, they lost modularity and experienced increased losses and costs. In addition, most of these topologies require more than two capacitors, which increases the cost and reduces efficiency. Generally, SC-MLIs topologies have been controlled by high-frequency pulse width modulation (PWM) techniques like level-shift, phase-shift, carrier-based PWMs, etc., or by a low-frequency PWM like staircase modulation technique. PWM-based modulation methods have several advantages, including the ability to use extremely high frequencies, independently control the amplitude and frequency, and reduce both load current distortion and filter requirements [14], [15], [16]. Despite these benefits, PWM methods that use a sinusoidal waveform for modulation are not suitable for MLIs because the output inverter frequency must be synchronized with the modulation frequency [17], [18], [19]. In addition, some SC-MLI topologies combine several logical functions with PWM to generate the proper switching pulses, which is more complex to implement [21], [22]. Furthermore, they use a proportionalintegral (PI) controller to achieve closed-loop control, which can be complicated due to the difficulty in determining a suitable value [23]. Indeed, the classical PWM methods for the switched-capacitor MLIs create a higher capacitor voltage ripple, which causes high ripple losses [24], [25].
At present, researchers are introducing new SC-MLI topologies almost daily [26], [27]. Since they are controlled by conventional PWM-based methods, they are difficult to implement. Therefore, it is essential that a proper control technique be developed sooner rather than later to ensure that the new topologies that are being developed will be compatible with the state-of-the-art control techniques and that they can be used well into the future. However, lately, with the development of digital control hardware platforms and fast microprocessors, nonlinear control methods such as Slide Mode Control (SMC) [28], Fuzzy Logic Control (FLC) [29], and Model Predictive Control (MPC) have started to appear in the field of multilevel inverter control [30], [31].
Among the above control techniques, MPC is an attractive control alternative for this family of inverters for the following attributes: 1. Fast dynamic response.
2. Ability to control multiple control objectives. 3. Dead-time compensation ability. 4. Easy inclusion of nonlinearities in the model. 5. Ability to handle shifting control objectives. 6. Easy implementation of the resulting controller. FCS-MPC uses the discrete nature of power electronic inverters to control the current, voltage, power, and torque, etc. In a power electronics inverter, the switches can only be turned on and off in two states, and their combination creates a finite number of states. Using this inherent feature, the inverter switching model can be easily presented, and the prediction can be summarized for the limited situations mentioned. The main elements of this control scheme are the mathematical model of the system and the predefined cost function [32], [33], [34].
The objective of the article is to propose a generalized guideline for applying FCS-MPC to single-phase switchedcapacitor MLIs. In order to accomplish this objective, the conventional FCS-MPC technique is applied to two typical single-phase switched-capacitor MLIs to become familiar with the implementation of MPC for this family of inverters. After that, by obtaining the data from these two typical SC-MLI topologies, a generalized FCS-MPC guideline is proposed in order to apply to any single-phase switched-capacitor MLI. To evaluate the correctness of the proposed guideline, a new switched-capacitor multilevel inverter topology is presented. In addition, the power circuit and operation modes of the proposed topology are illustrated in detail, and then, to show the strength and weaknesses of the proposed topology, it is compared to several state-of-the-art SC-MLI topologies. Then, based on the proposed guideline, the FCS-MPC technique is implemented to control the proposed topology. Finally, the experiment results are presented to confirm the correct operation of the proposed topology based on the proposed guideline.
In the following, in Section II, the conventional FCS-MPC technique is applied to two typical single-phase SC-MLI topologies. The proposed generalized FCS-MPC guideline is introduced step-by-step in Section III. The principal operation of the proposed topology and the implementation of FCS-MPC for the proposed topology based on the proposed guideline are described in detail in Section IV. Section V compares the proposed topology with the state-of-the-art SC-MLI topologies in different aspects. The thermal analysis and efficiency assessment of the proposed topology are presented in Section VI. Finally, the experimental results of the proposed topology are presented in Section VII.

II. IMPLEMENTATION OF CONVENTIONAL FCS-MPC TECHNIQUE FOR TWO CLASSICAL SWITCHED-CAPACITOR MLI
The objective of proposing this section is to introduce a generalized FCS-MPC guideline that is applicable to any single-phase switched-capacitor MLI. To accomplish this, the conventional FCS-MPC technique is applied to the two classical single-phase switched capacitor MLI topologies in this section. Then, in the next section, the proposed generalized FCS-MPC guideline is introduced. In the following, the operation of the topologies as well as the mathematical models of their respective inverters, load currents, and capacitors are described. Finally, both topologies are simulated in MATLAB/Simulink to verify the performance of the control technique.

A. FIRST SC-MLI TOPOLOGY
The power circuit of the first single-phase SC-MLI topology is presented in Fig. 1; this topology was developed by Liu et al. [25]. It consists of ten power switches, six unidirectional switches, two bidirectional switches, and three capacitors (charged in self-balancing mode) and can generate seven voltage levels. Table 1 shows the switching table of this topology.

1) MATHEMATICAL MODEL OF FIRST SC-MLI TOPOLOGY
In this study, the power switches are assumed to be ideal, so they have only two states: ON or OFF. As shown in Table  1, the first SC-MLI topology has eight possible switching states. Therefore, the output voltage of the first inverter V L can be represented in terms of input DC voltage V dc and the switching function of the inverter as follows: The power switches are assumed to be ideal. Therefore, F S 1 , . . . , F S 6 are the switching function of S 1 , . . . , S 6 which have two states ON or OFF.

2) LOAD MODEL
The output voltage of the inverter is given in terms of load current i L and load parameters (L L , R L ) as: The first order derivative of the inverter output current can be represented using the Euler approximation as follows: Here, T s represents the sampling time of the FCS-MPC controller. Meanwhile, (k + 1) and (k) represent the (k + 1)th and (k)th time intervals of the sampled output current of the inverter, respectively. Therefore, by using (4) in (3), the predicted output current for the (k + 1) sample can be represented as follows: In (5), the output current of the inverter is predicted for the (k + 1)th time interval using the (k)th sampled current and the predicted output voltage of the inverter using the voltage vectors. The first presented SC-MLI has eight switching states with seven different output voltages and various effects on the capacitor charging/discharging operations. Using all the available switching states, the controller optimizes the inverter's operation by selecting the optimal switching states.

3) CAPACITOR MODEL
The first topology has three capacitors (C 1 , C 2 , C 3 ), and their corresponding voltages are (V C1 , V C2 , V C3 ); they must maintain 0.5V dc , 0.5V dc and V dc , respectively. The continuous time models of the capacitors' voltages are represented using their initial voltages (V C1 (0), V C2 (0), V C3 (0)) and their corresponding currents (i C1 , i C2 , i C3 ) as follows: Then, the discrete-time modeling of the capacitor voltages is determined via Euler approximation as follows: Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
The capacitors' currents vary based on the applied switching states and the output current direction of the inverter. According to Table 1, the predicted currents of the capacitors are related to the measured output currents of the inverter as follows: By substituting (12)- (14) in (9)- (11) and measuring the capacitors' voltages, their future voltages can be predicted.

4) FCS-MPC CONTROLLER
The inverter's predicted and reference load current and capacitor voltages are included in the cost function of the FCS-MPC controller as follows: where λ 1 and γ 1 represent the weighting factors of the capacitors' voltages (C 1 , C 2 , C 3 ) that are required to achieve proper operation of the proposed topology. The weighting factor is calculated in terms of the rated load current and capacitor reference voltages ( to compensate for the difference in the nature of the control objectives [30]. The reference values of the capacitor voltages are controlled by the following:

B. SECOND SC-MLI TOPOLOGY
The schematic circuit of the second topology is a classical stacked multicell converter (SMC), shown in Fig. 2 [8]. The SMC generates five levels with eight power switches, two DC-link capacitors (C 21 , C 22 ), and two floating capacitors (C 11 , C 12 ). The DC-link capacitors are charged to half of the dc-link voltage V dc . The floating capacitors are charged to a quarter of the dc-link voltage. The SMC's power switches operate complementary to ensure the normal operation of the system. The switching pattern of the classical five-level SMC is illustrated in Table 2.
As in the first topology, the output voltage of the SMC (V L ) can be expressed in terms of the DC-link, floating capacitor voltages, and switching function as: Here, F S 11 , F S 12 , F S 21 , F S 22 , are the switching function of S 11 , S 21 , S 12 , S 22 which have two states ON or OFF.
The model of the load is given by (2)-(5), and the model of the capacitors can be obtained from (6)- (11). As previously stated, the capacitors' currents vary according to the applied switching states and the direction of the inverter's output current. According to Table 2, the predicted current of the capacitor is related to the measured output current of the inverter by the following: The inverter's predicted and reference load currents and capacitor voltages, as well as the second SC-MLI's switching frequency reduction, are included in the cost function of the MPC controller as: The reference values of the capacitor voltages are equal to those of the first topology as expressed in (16). The switching frequency reduction in the power inverters refers to commutations between switches that can be easily controlled by MPC. Therefore, as can be seen in (21), another term in the cost function to reduce the number of switches, which change between S(k) and S(k + 1), which can be expressed by using (18) as:

C. SIMULATION STUDY
Both the presented topologies are simulated in MAT-LAB/Simulink to verify the performance of the proposed FCS-MPC. The inverters feed an R-L load. The input DC-link is set to 120[V]. The simulation parameters are listed in Table  3. The topologies are evaluated for a step change load current at 6.6[ms] to demonstrate the dynamic response of the MPC. The simulation results of the first SC-MLI are shown in Fig. 3, and those of the second topology are shown in Fig. 4. Fig. 3(a) shows the load voltage of the first SC-MLI. As can be seen in the figure, when the reference current is decreased from 3[A] to 2[A] the number of levels reduces from seven to five. The reference and load currents are shown in Fig. 3(b). The load current correctly tracks the reference signal before and after the current change. In addition, it has a fast dynamic response when the reference signal is reduced. The capacitor voltage waveforms are shown in Fig. 3(c). As can be seen, the capacitor voltages are balanced in their references in both: steady state and transient state (after the step change in the reference signal). Fig. 4 shows the simulation results for the 5L-SMC topology. For this inverter, in addition to current control and capacitor voltage balancing, the communication reduction has been included in the cost function. The switching frequency  reduction is applied at time 11 [ms]. We considered a step change in the weighting factor γ 2 , which is initially zero and increases to 0.08 at time 65 [ms]. Consequently, as illustrated in Fig. 4(d), the number of commutations is reduced while the capacitors are kept fixed at their reference values and the load current tracks its reference properly.

III. PROPOSED GENERALIZED FCS-MPC GUIDELINE FOR SINGLE-PHASE SC-MLIS
In this section, based on applying model predictive control to two conventional SC-MLI topologies, a generalized FCS-MPC guideline is presented step-by-step to apply for any single-phase switched-capacitor multilevel inverter.

A. GENERAL DESCRIPTION 1) ELECTRICAL SYSTEM IDENTIFICATION
In the first step, all valid switching states of a multilevel inverter are identified through the power circuit of the inverter. They are then summarized in a single table, as shown in Table  1 and Table 2. The identification table is a tool for managing information. In this table, the switching states are included based on the output voltage of the inverter and their effect on the capacitor voltages.

2) PREDICTIVE MODEL
In the second step, the capacitor voltages and currents are written based on the load current i L and input voltage V dc because they are typically the only measured variables. It is important to consider that the equations will be based on measurements and switching states; the latter can be considered in a mathematical and logical way as expressed by (1)- (14). Because these equations are in discrete time, the multilevel inverter model will be a function of the input DC-link voltage, capacitor voltages, and switching states S. As a result, V L = F 1 (V dc , V C , S) can be shown. Likewise, the model of the load is a function of the load parameters, expressed as i L = F 2 (V L , i L ), and the voltage of the capacitors is a function of the capacitors' current, reference voltage, and switching state, i.e., V C = F 4 (V C , i C ). Therefore, the capacitor current is a function of the load current and the switching states

3) COST FUNCTION
After identifying the prediction model, it can be included as a cost function. Weighting factors must be included in the cost function. They are heuristically designed based on the behavior of the objective variables. Furthermore, it is possible to include other control objectives, like switching frequency reduction (see Fig. 4).

B. FCS-MPC ALGORITHM
The FCS-MPC algorithm is shown in Table 4. First, the measurement signals are written for the SC-MLI; these typically include DC link voltage, capacitor voltage, and output current. The capacitor voltage and output current are then added as reference signals, denoted by (k). Then the delay compensation, which is based on the model predictions for one switching state and denoted by (k+1), is incorporated. The compensation delay must be included in the FCS-MPC algorithm due to the time delay between the measurements and actuation. This time delay improves the system's responsiveness. Next, the relationships between the inverter's model with switching states, the load model, and the capacitor's model are written in a control loop, and the last line, i.e., the cost function indicated by (k+2), is written. The value of the cost function is compared with its optimal value. If it is less than its optimal value, the optimal value is chosen. Finally, based on the optimal cost function, the best switching state is chosen and applied to the inverter. This cycle is repeated for all switching states.

A. DESCRIPTION
The power architecture of the proposed switched-capacitor multilevel inverter topology is illustrated in Fig. 5. The circuit of this topology requires only one DC power supply and two  capacitors that are connected through the four semiconductor switches (S 3 , S 4 ) and (S 7 , S 8 ).
By paralleling with the input DC source, the voltage of the two selected DC capacitors (C 1 , C 2 ) is charged naturally at half of DC source (0.5V dc ). Thus, the proposed switchedcapacitor inverter does not require any further charge balancing in the control circuits.
Therefore, the proposed inverter provides a stepped waveform with seven different voltage levels (0, ±0.5V dc , ±V dc , and ±1.5V dc ). These voltage levels are created by connecting the DC power supply with capacitors in series and in parallel. Consequently, the proposed inverter boosts the DC power supply input by 1.5 times.
In addition to the boost advantage of the proposed inverter, it also mitigates the voltage stress of the power switches because it does not require a conventional H-bridge inverter to change the output voltage polarity.
The voltage and current stress of each power switch during the generation of each voltage level are given in Tables 6 and  7. Since the four switches (S 1 , S 2 ), (S 5 , S 6 ) are operettas in complementary, hence the voltage stress of these pair switches are V dc and their current stress is equal to load current I L . Similarly, the voltage stress of two switches (S 4 , S 8 ) are equal to V dc and load current is passing from these switches. The voltage stress that two switches (S 3 , S 7 ) endure is equal to half of the input dc-link voltage 0.5V dc and the current stress

TABLE 7. Current Stress of Each Switch of the Proposed Seven-Level SC-MLI for Generating Each Level
for these switches is the sum of DC current and load current. Therefore, based on Tables 6 and 7, the voltage rating and current rating of (S 1 , S 2 , S 4 , S 5 , S 6 , S 8 ) are V dc and I L , respectively. The voltage and current ratings switches (S 3 , S 7 ) are 0.5V dc and (I L + I dc ), respectively. The Total Stress Voltage (TSV) of the proposed inverter is obtained from the sum of the maximum voltage stresses on all semiconductor switches. Consequently, the proposed inverter TSV value is 7V dc , which is low and leads to selecting IGBTs with a low-rating voltage. Hence, in this shape, all semiconductor switches consist of an IGBT along with one anti-parallel diode, except for one pair of IGBTs (S 3 , S 7 ) that do not require anti-parallel diodes.

B. OPERATION MODES
All possible switching states, capacitor charge conditions, and output voltages of the proposed sub-module switchedcapacitor inverter are shown in Table 5. In this table, "↑" is for charging, and "↓" is for discharging capacitors, and "−" is the neutral mode. As can be seen in Table 1, there is some redundancy in creating voltage levels of ±0.5V dc and the zero level. All operation modes used to create the seven voltage levels in the proposed multilevel inverter, as shown in Fig. 6, are explained in detail as follows: r First mode: the first mode has zero levels. For this mode, there are two states. The first state produces zero levels in the output by switching the three switches of (S 2 , S 6 , S 7 ). In addition, the power switch S 3 is also turned on so that the capacitors are charged in parallel with the input DC supply. The other state that creates zero levels can be produced by switching the switches (S 1 , S 3 , S 5 ) along with S 7 to charge the capacitors. r Second mode: the second mode is +0.5V dc . As with the zero-level mode, there are two different states that produce this mode. The first and second states produce 0.5V dc by switching three switches, either (S 1 , S 6 , S 8 ) or (S 1 , S 4 , S 5 ). In this mode, the voltage of the capacitor C 1 is discharged through the load current, and the voltage level of +0.5V dc can be generated.
r Third mode: The third mode is +V dc . By turning on three power switches (S 1 , S 3 , S 6 ), the magnitude of the input DC supply can be generated at the output. Switch S 7 is also turned on to keep the capacitor voltages charged.
r Fourth mode: This mode provides the maximum positive level, 1.5V dc , which is obtained from the sum of the voltage of C 1 and the input DC supply. This voltage level is produced by the switching of three switches (S 1 , S 4 , S 6 ).
r Fifth mode: In this mode, the output voltage is equal to the capacitor voltage of C 2 , that is −0.5V dc . As in the second mode, there are two available states that produce this mode. It is created by turning on three switches, either (S 2 , S 4 , S 5 ) or (S 2 , S 6 , S 8 ).
r Sixth mode: In this mode, the output voltage is equal to the negative value of the input DC power supply −V dc ; it is generated by three switches (S 2 , S 5 , S 7 ). In addition, switch S 3 is turned on to charge the capacitors.
r Seventh mode: This mode provides the second negative level, −1.5V dc , which is obtained from the sum of the capacitor voltage C 2 and the input DC supply. This output voltage level is achieved by the switching of three switches (S 2 , S 5 , S 8 ).

C. APPLYING FCS-MPC FOR THE PROPOSED SC-MLI BASED ON PROPOSED GENERALIZED GUIDELINE
The proposed generalized FCS-MPC guideline is implemented for the control of the proposed seven-level SC-MLI. In the two previous subsections (A and B), all operation modes of the proposed topology are described, and all valid switching states based on the output voltage of the proposed inverter and capacitor voltage and currents are described in detail. Therefore, the first step of the proposed guideline, which is electrical system identification, has been completed.
The second step of the proposed guideline is predictive control. This step is about extracting the model of the proposed inverter and load model. Therefore, in the first place, the model of the proposed inverter is derived based on switching states from Table 5. As detailed in Table 5, the proposed topology has ten different switching states. Based on the proposed seven-level inverter in Fig. 5, the output voltage of the inverter V L can be represented in terms of input DC voltage V dc and the switching function as follows: Here, F S 1 , · · · F S 8 , are the switching function of S 1 , . . . , S 8 which have two states ON or OFF.
Then the load model that is a resistive-inductive load is derived. As we wrote the load model and capacitor model for two classical SC-MLI in Section II, the model of the load is obtained from (2)- (5), and the model of the capacitors can be obtained from (6)- (11). In the proposed topology, the capacitors' currents vary according to the applied switching states and the output current direction of the inverter. According to Table 5, the predicted capacitor current is related to the measured output current of the inverter (i L ) and the DC source current (i dc ) as follows: where K 1C 1 , K 2C 1 , and K 1C 2 are: Here, "∧" is the AND sing, "∨" is the OR sign, and "¬" is the NOT sign as used in Boolean logic.
The last step of the proposed guideline is to define the cost function. Load current control and capacitor voltage control are two control objectives that are included in the cost function. Therefore, the predicted and reference load currents and capacitor voltages of the inverter are included in the cost function as follows: The weighting factor of λ and the reference values of the capacitor voltages are computed by (15) and (16), respectively.

D. CAPACITOR RIPPLE ANALYSIS
In the proposed topology, both used capacitors are charged to generate voltage levels (±0.5, ±1.5V dc ). Therefore, the voltages of these two capacitors shouldn't drop to less than an allowable value. Hence, to calculate the capacitance of the capacitors, it is necessary to measure their stored energy (that pumps to the output). Fig. 7 shows the capacitor charging and discharging in all operating modes. As can be seen from this figure, the longest discharging time (LDT) for both capacitors is the same, which happens for the maximum output levels (±1.5V dc ) in time intervals (t 4 − t 3 ) and (t 10 − t 9 ). Therefore, the amount of charge discharged during LDTs for (C 1 , C 2 ) are obtained as follows [20], [21], [22]: where I L is the magnitude of the load current, and ω = 2π f o .
Since the switching frequency of MPC is variable, the time intervals t 3 , t 4 and t 9 , t 10 are variable but similar average frequency calculations for MPC, these time intervals can be obtained by calculating their average values (t i ) from the following equation: Here, k is the number of cycles. It is obvious that the highest discharging value and, thus, the greatest voltage ripple of capacitors occur in a purely resistance load. However, because MPC works with a resistance inductive load, we assume the inductance value of the load is so small that it is ignored. Hence, Q C 1 ,C 2 are computed as follows: Hence, the ripple voltage of capacitors ( V ripple,C 1 , V ripple,C 2 ) are obtained as:

V. COMPARISON OUTCOMES
To demonstrate the performance of the proposed seven-level SC-MLI, a study is performed on the proposed topology and state-of-art switched-capacitor MLI topologies [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [35], [36], [37]. The parameters used to compare the proposed topology with the other existing SC-MLIs are given in Table  8. The parameters of the comparative study are the number of components, on-state IGBTs, the per-unit value of TSV, boosting gain, generalized configuration, leakage current, charge balancing, control or modulation technique, and efficiency. In addition, the proposed topologies' costs are compared by defining a cost function (CF). The greatest costs of multilevel inverters are related to the number of components and the TSV where α is the TSV weighting factor. According to Table 6, [16] and [17] produce five levels with six and seven switches, respectively, so they have a high-cost factor. The high number of IGBTs required to produce seven levels is attributed to [18] and [19], as well as the presented MLIs [23], [24], [25], [26], [27]. Meanwhile, the lowest number of required IGBTs is for the proposed topology and [21], [22] to generate seven-level. Also, [37] uses eight switches to generate five levels. As a result, the proposed topology requires fewer switches than the other MLIs. In addition, the proposed SC-MLI produces less voltage stress than the other SC-MLIs, except for [21], which has a low TSV. Furthermore, the proposed SC-MLI requires fewer diodes than other SC-MLIs. This reduction is due to the use of two IGBTs without the need for anti-parallel diodes in the proposed topology. The number of capacitors for the proposed topology is also less than most of the presented SC-MLIs. Although [22] uses the same number of switches and capacitors as the proposed topology, the voltage stress of the switches is very high, which results in the cost factor of the inverter. Also, it cannot be extended as a generalized topology to reach a high number of levels. The presented topologies [35], [36], [37] are grid-connected inverters that have been presented for photovoltaic systems. We also compared the proposed topology with these topologies. As you can see, the proposed topology still generates seven levels and requires a low number of switches and capacitors. It also doesn't need any extra inductance in its circuit. As can be observed in Table  8, almost all topologies use low frequency PWM (NLC) or high frequency PWM techniques, which are open-loop (OL), except for grid-connected inverters [35], [36], [37] that are close-loop (CL), in contrast to the proposed topology that uses MPC, which naturally is a simple close-loop control without using any PI controller of modulation signal. As depicted in Table 8, the proposed seven-level SC-MLI requires fewer semiconductors and capacitors than other similar SC-MLIs to generate a seven levels with the lowest TSV and low CF; this makes it more efficient, affordable, and practical.

VI. THERMAL LOSSES AND EFFICIENCY
To calculate the power losses, the suggested seven-level structure is thermally modeled in PLECS software. For this investigation, the IGBT IKFW60N60DH3E is used. The value of (Ron) is chosen based on the switch and diode datasheet, which is used for power loss analysis of the proposed topology. The current-voltage curve of the switch is defined in the software. In addition, the junction temperature evaluation of all power switches is also being investigated. The junction temperature of all the IGBTs is evaluated using their characteristics and the thermal models mentioned in Table 9. The inverter's input is connected through a DC link with a value of 120 [V]. The inverter's output is linked to a 10[ ] and 5[mH] resistance inductive load to deliver power 1[kW]. The suggested FCS-MPC is used to control the proposed topology. The starting temperature is 25[ • C] for this study. Fig. 8(a) shows the output waveform of the proposed topology and capacitor voltages. This figure confirms that seven voltage levels with a peak of 180[V] are generated by the proposed topology and that the capacitors are charged at 60[V]. The power losses of each IGBT and its parallel diodes are shown in Fig. 8(b). In addition, the capacitor voltage ripple losses are displayed in Fig. 8(b). Because the switches S 3 and S 7 are used to charge the capacitors, they have a larger power loss than the other devices, as illustrated in Fig. 8(b). Fig. 8(c) shows the junction temperature of each switch, and as can be observed, two switches, S 3 and S 7 , have greater temperatures than the others due to larger power losses. The proposed inverter has a total loss of 54[W] at an output power of 1[kW], with an efficiency of 94.6%, as shown in Fig. 8(d).
In this investigation, the capacitor ripple loss (P Ripple,C ), it is also known as the capacitor loss, and is calculated as follows: Here f o indicates the output frequency.

VII. EXPERIMENTAL VALIDATION AND DISCUSSION
The experimental results for the proposed seven-level inverter are presented to validate the theoretical study. The prototype of the proposed topology is built using eight IGBTs as switches and two electrolyte capacitors. The input of the proposed topology is a dc-link voltage that is supplied by a laboratory dc power supply (which is set to 120[V]), and the output of the topology interface consists of a resistanceinductive load (R = 50[ ], L = 10[mH]). The proposed model predictive control algorithm is programmed on a Digital Signal Processing (DSP), and a Field-Programmable Gate Array (FPGA) is used to apply dead time 2[μs] to prevent short-circuiting. The gating signals are transferred to the IGBTs through an optic wire. The load voltage, load current, and the capacitor's voltages are measured by a separate sensor board. Table 10 provides a list of the components used in the experiment. of each switch in the proposed topology is different due to the nature of MPC, which has a variable frequency.

A. STEADY-STATE PERFORMANCE
In order for the inverter to control the load current in the proposed FCS-MPC strategy, a sinusoidal waveform with a peak value i * L of 3[A] is chosen as the reference load current. Fig. 9 illustrates the steady-state experimental results of the proposed seven-level inverter. Fig. 9(a) shows the load voltage, load current, and capacitor voltages. Fig. 9(b) shows a zoomed view of Fig. 9(a)

B. TRANSIENT AND DYNAMIC PERFORMANCE
The transient and dynamic response of the proposed topology is tested with load reference current changes, which is a typical test for the evaluation of multilevel inverters. The system is evaluated by making changes in the amplitude, phase angle, and frequency parameters of the reference load current. Fig.  10 displays the load voltage, load current, and reference load current along with capacitor voltages used for adjusting the amplitude of the load reference current.
The first test is for the load current amplitude changes. As shown in Fig. 10(a)

1[s] when reference current is reduced from 3[A] to 2[A]; (c) zoomed (a) for 0.1[s] when reference current is increased from 2[A] to 3[A].
Close-up views of the step changes are displayed in Fig. 10(b) and (c). Fig. 10(b) shows the inverter's response to the step change in the current from 3[A] to 2[A] (66% decrease). This figure shows that by decreasing the amplitude of the reference current signal, the number of voltage levels of the proposed topology is decreased from seven to five, which means the peak of the load voltage is reduced from 180[V] to 120[V]. The proposed control strategy implemented in the proposed topology demonstrates a good dynamic response to this sudden change, as the load current tracks the reference signal such that it does not cause a spike in the load current and causes only a small shape change in the load voltage and current waveform. . This figure shows that by raising the amplitude of the reference current signal, the number of voltage levels increases from five to seven, raising the peak voltage from 120[V] to 180 [V]. The figure also shows that the proposed MPC has a good dynamic response to this amplitude increase as the transient time required to track the reference current signal is minimal. Additionally, it shows that the load current tracks the reference current signal quickly with a short transition time that does not cause a spike in the load current.
The test of the proposed topology with the proposed FCS-MPC then continues for the amplitude changes, phase shift, and frequency step change. Fig. 11 shows the experimental results of load current and load reference for these step changes. Fig. 11(a) shows the experimental results of load current and load reference current for the amplitude step increasing from 0 to 3 [A]. As shown in this figure, the load current tracks the reference current signal properly without any change in the shape or amplitude of the load current. Fig. 11(b) documents the dynamic and transient response of the proposed topology for a phase shift in the load reference current from 0 to 180 • . In this case, the load current can track the reference load current, and no spike is observed during the transient process. It reveals that the proposed topology has a good dynamic performance with the proposed FCS-MPC technique.
The experimental results of the load reference signal and load current for a step frequency change from 50[Hz] to 100[Hz] are shown in Fig. 11(c). For this test, like in previous tests, the proposed FCS-MPC control strategy implemented on the proposed topology has good dynamic and transient responses due to good tracking of the load reference current with no spike or change observed in the load current.

C. COMPARISON FCS-MPC AND CLASSICAL PWM TECHNIQUES FOR SC-MLIS
In this subsection, the FCS-MPC is compared with the classical PWM methods for the control of SC-MLIs in order to show the advantage of FCS-MPC for this family of inverters. As we showed in Section II and this section, FCS-MPC has the ability to control multiple objectives, such as current control, balancing the voltage of the capacitors, and switching frequency control, by including them in the cost function. In addition, it reduces the capacitor's voltage ripples and THD magnitudes. In contrast, a classical PWM control technique for SC-MLIs uses two or more PI controllers for current control and balancing the voltage of the capacitors, which makes the control hard and complex [38], [39]. In addition, industrial applications need several operational amplifiers (OpAmp) to tune the control objectives, which increases the final cost of massive production.
In conclusion, by advancing the speed of the microprocessor model, predictive control can be applied in the future to industrial productions to overcome the computational burden, which is the main disadvantage of MPC.

VIII. CONCLUSION
Single-phase multilevel inverters are attractive topologies for improving quality in low power applications, such as photovoltaic systems. However, control and modulation with classical strategies are not easy to implement. On the other hand, finite set model predictive control has been positioned as a good alternative for complex topologies, in which the direct control and application of the states of the converter help to correctly and easily manage different kinds of converters. In this article, a generalized guideline for the implementation of the FCS-MPC strategy to control single-phase SC-MLIs was presented. Through simulation results, the FCS-MPC was tested and evaluated for two classical SC-MLI topologies. Then, to facilitate the application of FCS-MPC in all types of SC-MLIs, the generalized FCS-MPC guideline was presented. Furthermore, a seven-level SC-MLI topology was presented; it has several advantages over previously reported SC-MLIs, such as lowering the TSV and reducing the number of power semiconductors and capacitors. FCS-MPC was easily implemented in this novel topology by following the proposed guidelines. The experimental results show that the proposed FCS-MPC technique can provide a high-quality output waveform while maintaining a balanced capacitor voltage with a low voltage ripple.