Low Frequency Ripple Reduction in Input DC Current and AC Line Currents With 240$^{\circ }$ Clamped Space Vector PWM in Grid-Connected Photovoltaic Converters

240<inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula>-Clamped Space Vector PWM (240CPWM) is a lowest switching loss PWM method in cascaded architecture of DC-DC stage followed by DC-AC stage that reduces the switching loss by 85% in the DC-AC stage at unity power factor as compared to conventional space vector PWM (CSVPWM). 240CPWM requires unique six-pulse dynamically varying DC link voltage instead of constant DC link voltage which introduces low frequency harmonics predominantly around six times the fundamental frequency (<inline-formula><tex-math notation="LaTeX">$6f_{1}$</tex-math></inline-formula>). These low frequency harmonics distort the input DC current and AC line currents. Moreover, they change the operating point of maximum power point tracking (MPPT), reducing the efficiency of grid-connected Photovoltaic (PV) converter. In this article, three topologies are proposed to reduce the low frequency ripple in input DC current and AC line currents in three-phase grid-connected PV systems with 240CPWM. A three-phase 1.5 kW Silicon Carbide based hardware prototype in grid-connected mode is developed to validate the performance of the proposed topologies. Experimental results show that the maximum reduction of 68.8% in (<inline-formula><tex-math notation="LaTeX">$6f_{1}$</tex-math></inline-formula>) harmonic component in DC input current is achieved in active filter based Topology II without any significant detrimental effect on THD in AC line currents and inverter efficiency as compared to standard topology.


I. INTRODUCTION
With ever dwindling conventional energy resources, there is a natural shift towards alternate renewable energy sources [1]. Use of renewable energy has rapidly increased through the advancement in grid integration technologies [2]. Solar photovoltaic (PV) and wind energy have gained a substantial growth to an all-time high of more than 256 GW of added capacity in 2020 [3].
As compared to standalone PV systems, use of gridconnected PV systems is widely adopted in practical applications [4], [5]. Single phase PV converters are normally used in residential homes while industrial and commercial loads use three phase PV converters [5]. In PV systems, DC-DC stage followed by DC-AC stage is a standard configuration wherein DC-DC stage is a boost converter or its variant [6], [7]. Low frequency input current ripple at twice the fundamental frequency is a well known problem in single phase inverters. Due to the instantaneous input and output power unbalance in two-stage single-phase PV inverter, its front-end boost converter tends to draw a current ripple with twice the grid frequency. This low frequency ripple perturbs the operating point of PV arrays continuously that reduces the efficiency of maximum power point tracking (MPPT) [8]. Large electrolytic capacitors can be used to minimize that ripple but they are not desirable because of large volume and low life span [9]. Active power decoupling techniques have been proposed to reduce the low frequency current ripple in single phase PV converters [10], [11], [12]. In three phase grid connected PV converters with conventional PWM methods, low frequency ripple at twice the fundamental frequency exists only under unbalanced three phase load that produces pulsating power causing DC link to generate low frequency ripple that eventually propagates to PV cell [13].
Various advanced PWM methods have been discussed in literature to improve the performance of power converter. A discontinuous PWM method is proposed in [14] that reduces the switching loss at the expense of increased switching frequency ripple and total harmonic distortion (THD). A set of hybrid PWM methods has been discussed in [15] that effectively reduces the common mode voltage (CMV) but this reduction is achieved at the cost of high switching loss, THD and DC-link current stress as compared to conventional space vector PWM (CSVPWM). In [16], a control technique to improve the power quality and performance of grid-connected single to three-phase power converter is proposed wherein advanced bus clamped PWM method is used to reduce the DC link voltage ripple in such power converters. 240 • -Clamped Space Vector PWM (240CPWM) is a relatively new PWM method that has the lowest switching loss to date when cascaded configuration of DC-DC stage followed by DC-AC stage is used. In PV systems, DC-DC stage followed by DC-AC stage is a standard configuration [6], [7]. Hence, 240CPWM can be conveniently used in any three-phase twostage PV systems without increasing the component count or changing the topology. The application of 240CPWM has been discussed in grid-connected PV converter in [17], [18], [19], [20], [21], [22], [23], [27] and motor drives in [24], [25]. Details of 240CPWM concept, generation of switching signals and implementation of 240CPWM using space vector approach have been discussed in detail in [24]. In [26], 240CPWM is selected as an ideal candidate for grid connected PV converters in terms of all round performance of switching loss, THD, DC link current stress, CMV and leakage current. Despite various advantages of 240CPWM, it comes with the inherent problem of low frequency harmonics i.e., six times the fundamental frequency (6 f 1 ) harmonics to maintain six-pulse dynamically varying DC link voltage. These low frequency harmonics distort the input DC current and AC line currents especially with large values of DC link capacitance. Moreover, they change the operating point of MPPT, reducing the efficiency of grid-connected PV converter. The low frequency harmonics in input DC current in PV application with 240CPWM have been shown in [18], [20], [21]. However, methods to mitigate the low frequency harmonics in input DC current and AC line currents with 240CPWM have never been discussed before. Fig. 1 shows the characteristic waveforms in grid-connected mode with 240CPWM in a fundamental cycle where input DC current has low frequency ripple to support the dynamically varying six-pulse DC link voltage. Fig. 2 shows a three phase grid connected PV converter with 240CPWM along with input current, dynamic DC link voltage and FFT of normalized inverter current (normalized with respect to peak value). The 6 f 1 and other low frequency harmonics due to the dynamic DC link voltage distort input DC current and AC line currents as shown in Fig. 2.
The DC-DC stage in standard PV converters is generally a boost converter or its variant [30]. Many commercial inverters use interleaving to increase power handling capability and to reduce the size of passive components [7]. We have also used three phase, DC-DC interleaved boost converter (IBC) as the main input stage, with topological modifications that aim to minimize the low frequency distortion in the input PV current without affecting the THD of AC line currents. The major contributions of this work are summarized below: a) Analytical calculation of low frequency harmonic components in input DC current due to dynamic DC link voltage with 240CPWM. b) Proposed three novel topologies to reduce low frequency harmonics in input DC current and AC line currents with 240CPWM which has been a main impediment to the adoption of 240CPWM in two-stage converter. It is shown that all the proposed topologies effectively reduce the low frequency harmonics in input DC current and AC line currents; c) Hardware results from a 1.5 kW two-stage PV converter with Silicon Carbide IBC switching at 50 kHz and Silicon Carbide three-phase inverter switching at 100 kHz with 240CPWM are presented to validate the performance of the proposed topologies to reduce low frequency harmonics in input DC current. This article is organized as follows. The analytical discussions on low frequency harmonics in input DC current due to six-pulse dynamic DC link voltage in 240CPWM are outlined  in Section II. Three novel topologies based on two types of 6 f 1 harmonic reduction schemes are presented in Section III. Detailed comparison of all the topologies is carried out in Section III-C. All the topologies are validated experimentally using a 1.5 kW experimental prototype in Section V. Section VI summaizes the conclusions.

II. LOW FREQUENCY RIPPLE IN INPUT CURRENT WITH 240CPWM
The expression of dynamic DC link required for 240CPWM shown in Fig. 3(a) when 0 ≤ ωt ≤ π/3 is shown in (1) [24].
Analytical expression of the frequency spectrum of dynamic DC link voltage is given in (2). The average component of dynamic DC link voltage is 3 π V dc,pk and other low frequency components like 6 f 1 , 12 f 1 , 18f 1 and so on can be obtained by using n = 6,12,18... in (2) where a n = 6V dc,pk π (1−n 2 ) cos nπ 2 and b n = 0 12,18 [a n cos(nθ ) + b n sin(nθ )] Using a n and b n in (2), Fourier series of instantaneous dynamic DC link voltage is obtained as follows: From (3), the DC component and low frequency harmonics of normalized dynamic DC link voltage are calculated as shown in Table 1. The harmonic content of the DC link voltage from analysis and PLECS simulation are shown in Fig. 3(b) corresponding to a peak DC link value of 680 V. In a standard topology of three phase grid connected converter with 240CPWM as shown in Fig. 2, the dynamic energy in DC link capacitor (E st andard ) and corresponding dynamic power (P st andard ) which is d dt (E st andard ) for 0 ≤ ωt ≤ π/3 is calculated in (4) and (5).

TABLE 2. Grid-Connected PV Converter Specifications in PLECS Simulation
The DC link capacitor draws dominant low frequency harmonic components due to dynamic DC link voltage required for 240CPWM (associated with charging/discharging of the DC-link capacitor to follow the six-pulse DC-link waveform). This low frequency harmonic power or pulsating power in the DC link capacitor is supported either by input DC side or grid side which is dictated mainly by the control scheme used in the DC-DC stage. If the DC link capacitor power is supported by AC side, the grid currents have higher harmonics which increase the THD in grid currents. Instead, if it is drawn from the input DC side, in the context of a PV inverter system, the pulsation in the input power makes the maximum power point tracking sub-optimal and reduces the power drawn from the solar panels.

III. TOPOLOGIES TO REDUCE LOW FREQUENCY RIPPLE IN INPUT CURRENT
In this section, two types of schemes that minimize the low frequency ripple in input DC current are discussed. In the first scheme, dynamic DC link voltage is split into a larger constant part and a smaller dynamically varying part. Topology I is based on this concept. The second scheme comprises of an active filter to compensate for the low frequency harmonics in input DC current (i.e., Topology II and III).

A. TOPOLOGY I
Topology I is the simplest of the configurations proposed here to reduce 6 f 1 ripple. In this topology, DC input voltage (PV voltage) is made part of DC link voltage such that DC-DC converter is only responsible for generating dynamic part of the DC link voltage and constant part of DC link voltage comes directly from the input source V in . The main advantage of this topology is that it does not involve adding any new components or increasing the rating of any components. This topology along with ideal voltages corresponding to the parameters of Table 2 are shown in Fig. 4. For peak DC link voltage of 680 V, constant part of DC link voltage (i.e. 580 V) comes from the input source directly and dynamic DC link voltage varying from zero to 100 V is generated by IBC. It reduces the total change in the energy of the DC link capacitor during each pulsating period, which reduces low frequency input power pulsation and ultimately low frequency harmonics in input DC current. Here, IBC is controlled in a dual loop fashion where the outer voltage loop is much slower with a bandwidth of 3 kHz and the inner current loop with a bandwidth of 20 kHz. The control block diagram of Topology I is shown in Fig. 4. The outer voltage loop regulates the six-pulse dynamic DC link voltage V dc (t ) where the peak value of the reference DC link voltage V dc−re f is 680 V for the converter specifications shown in Table 2. The inner current loop receives the reference current I * in from the outer voltage loop and regulates the input current of IBC. Since the DC input voltage is made part of DC link voltage such that IBC is only responsible for generating dynamic part of the DC link voltage and constant part of DC link voltage comes directly from the input source V in , this allows to achieve a dynamic part of the DC link voltage (V C−var ) on the DC link capacitor C dclink varying from 0 to 100 V for a peak DC link voltage of 680 V.
The energy (E T 1 ) and power (P T 1 ) in DC link capacitor with Topology I for 0 ≤ ωt ≤ π/3 are calculated in (6) and .
The energy difference from peak to lowest voltage in DC link capacitor for standard topology ( E st andard ) and Topology I ( E T 1,min ) when the input voltage is maximum is calculated in (8) and (9) corresponding to Fig. 5 (a,b) where Comparing (8) and (9), the Topology I at maximum input voltage results in nearly 93% reduction in energy pulsation compared to the standard topology. At arbitrary V in , the energy difference from peak to lowest voltage in DC link capacitor for standard topology remains the same as (8) but it changes for Topology I which is calculated in (10) corresponding to Fig. 5 The ratio of energy difference from peak to lowest voltage in DC link capacitor for standard topology and Topology I ( E st andard / E T 1 ) at arbitrary input voltage is shown in Fig. 6(a) where this ratio is 14 at maximum input voltage and it reduces significantly as the input voltage decreases. Hence, Topology I gives the highest reduction of 14 times in  energy change in DC link capacitor when the input voltage is maximum.
The ratio of peak-to-peak DC link capacitor power in standard topology and Topology I (P st andard /P T 1 ) is shown in Fig. 6(b) where the highest reduction of 16 times is achieved at maximum input voltage and the savings are reduced as the input voltage decreases. The input power pulsation from PLECS simulation with standard topology and Topology I at various input voltages corresponding to the parameters of Table 2 is shown in Fig. 7. Standard topology has the highest peak to peak power pulsation as shown in black and the power pulsation reduces with Topology I. The peak to peak power pulsation with Topology I at maximum input voltage is shown in blue which is 16 times lower than the standard topology.
The average model of DC-DC stage as related to the DC link capacitor current in standard topology is shown in Fig. 8(a) where I in = I c /(1 − d ). Fig. 8 To calculate the input current harmonics analytically for standard topology, Fourier analysis of (5) is carried out and then I in = P in /V in is used to obtain harmonic components of input current. The Fourier coefficient a n for (5) corresponding   to standard topology comes out to be as follows: a n = ± k 1 π 9 √ 3n 1 − 9n 2 (11) + for even n, − for odd n.
where k 1 = −0.5C dc,link V dc,pk ω o and −π/3 ≤ ω o t ≤ π/3. Table 3 shows the harmonic components of input current for standard topology for V in = 400 V and V in = 550 V. I in,sim comes from PLECS simulation of the average model similar to that shown in Fig. 8(a) with the duty ratio d given by (1-V in /V link ) and the DC-AC stage modeled as constant power load. I eqn comes from (5) implemented in PLECS in time domain and I coe f f comes directly from (11) for n = 1, 2 and 3. A good match between all these quantities shows accuracy of the analysis and simulation models.
Using the same approach, harmonic components of input current for Topology I are calculated analytically from the Fourier analysis of (7). The Fourier coefficients a n of (7) are given by (12) a n = ± k 1 n π + for even n, − for odd n. Again using the same approach as done for standard topology, Table 4 is obtained for Topology I wherein a good match is observed in harmonic components of input current obtained from analysis and simulation. The harmonic components in input current from Topology I ( Table 4) are significantly lower than harmonic components obtained from standard topology (Table 3) as expected. The 6 f 1 component in input current with Topology I is 62% and 85.4% lower than the 6 f 1 component obtained from standard topology at V in = 400 V and 550 V respectively. Fig. 9 shows the input currents from PLECS simulation with complete switching models of the DC-DC stage and DC-AC stage and corresponding to the parameters shown in Table 2 with original topology and Topology I at high input voltage i.e., V in = 550 V. 6 f 1 harmonic is significantly reduced with Topology I as shown in the periodic average input current in Fig. 9(b). It has high switching frequency component shown in the instantaneous input current as the DC link capacitor current flows through the input source also in Topology I. The high frequency component can be easily filtered with small LC filters unlike 6 f 1 components.
An example of lower V in as compared to previous case is shown in Fig. 10 wherein V in is kept at 400 V. The periodic average input current with Topology I at low V in (Fig. 10(b)) has lower peak to peak low frequency ripple as compared to the original topology ( Fig. 10(a)) but higher than the periodic average input current with Topology I at high V in (Fig. 9(b)).

B. TOPOLOGY II
Topology II is second type of 6 f 1 reduction scheme presented in this work where an active filter (AF) is used in boost configuration. The active filter current compensates for the low frequency harmonics in DC input current. An auxiliary ripple storage circuit or active filter is a well known method to effectively reduce the low frequency input current ripple in single phase PV converters [32]. A similar method is used here for three phase grid-connected PV converter with 240CPWM such that the active filter supports the low frequency power FIGURE. 11. Topology II: Active filter in boost configuration to reduce low frequency input current ripple with 240CPWM.

FIGURE. 12. (a) Input current with Topology II, (b) FFT of input current with original topology and Topology II from PLECS simulation.
pulsation in the DC link capacitor, thus minimizing the low frequency harmonics in the input current. Fig. 11 shows the Topology II with AF in boost configuration with ideal voltages and currents in a three phase grid-connected PV converter under consideration for the parameters in Table 2.
The switching frequency of AF is set to 600 kHz. Capacitance C a f and inductance L a f of AF are chosen as 10 uF and 150 uH respectively in PLECS simulation. Both IBC and AF are controlled in a dual loop fashion. IBC regulates the average voltage of active filter capacitor voltage V a f with a slow outer voltage loop and input current of IBC I in with a fast inner current loop. AF regulates the dynamic DC link voltage V dc (t ) by controlling its input voltage and active filter inductor current i a f in a dual loop control. The output voltage of AF is controlled to have higher magnitude by setting a higher value in V a f −avg as compared to the maximum dynamic DC link voltage. For example, in this case for a peak DC link voltage of 680 V, V a f −avg is set as 900 V. Moreover, the output voltage of AF is controlled to have opposite shape as compared to the dynamic DC link voltage as shown by V a f waveform in Fig. 11. This V a f enables the active filter current i a f to compensate for the low frequency harmonics in input current. Ideally, the low frequency harmonics in input current are removed with this topology. Fig. 12 shows the input current and its FFT with Topology II. It is clear that the 6 f 1 harmonic component in input current is reduced to just 0.233 A as compared to the 3.33 A in the standard configuration. Fig. 13 shows V a f and i a f for the parameters corresponding to Table 2. As expected, V a f has a higher peak value of 1000 V and is inverted as compared to typical DC link voltage required for 240CPWM. i a f is centered around zero and has a lower peak value of 5 A. The drawback of this topology is that the added switches and capacitor of AF have to be rated for high voltage due to high V a f as compared to Topology III discussed next. Fig. 14 shows the Topology III with an active filter in buck configuration. The output voltage of AF is controlled to have lower magnitude and opposite shape as compared to the dynamic DC link voltage as shown by V a f in Fig. 14 which allows the active filter current i a f to compensate for the low frequency harmonics in input current. Fig. 15 shows the input current and its FFT with Topology III. The 6 f 1 harmonic component in input current is reduced to just 0.33 A as compared to the 3.33 A in the standard configuration. The advantage of this topology is that the devices and capacitor of Topology III are rated for much lower voltage as compared to Topology II. However, the current rating for the AF switches is increased compared to Topology II.

IV. LOSS ANALYSIS AND COMPARISON OF TOPOLOGIES
All the topologies discussed so far will now be compared in terms of total power loss, THD, low frequency harmonic components in input current, total VA rating of switches (sum of I pk V pk of switches), inductor ratings (sum of product of LI pk I rms of all the inductors) and capacitor ratings (sum of product of CV 2 pk of all the capacitors) from PLECS simulation at 23 kW. Simulation parameters are shown in Table 2.
Loss analysis of DC-AC stage with 240CPWM is carried out in detail in [24]. Power loss breakdown of DC-AC stage with 240CPWM obtained from PLECS simulation at 23 kW is shown in Fig. 16.

A. LOSS BREAKDOWN OF STANDARD TOPOLOGY
Total power loss in standard topology and its loss breakdown both at low input voltage (V in = 400 V) and high input voltage (V in = 550 V) are shown in Fig. 17 and Fig. 18 respectively. Power loss at high input voltage is reduced because currents are decreased to maintain the same power level.

B. LOSS BREAKDOWN OF TOPOLOGY I
Power loss is Topology I is very similar to the standard topology. It is only slightly lower than standard topology. Loss

C. LOSS BREAKDOWN OF TOPOLOGY II
The active filter current compensates for the low frequency harmonics in DC input current. Since the active filter processes only fractional power and supports small current, conduction losses in active filter switches are minimal. However, switching losses are relatively higher because of very high voltage on the switches because of boost configuration of active filter (i.e., in this case 800 to 1000 V) for DC link voltage of 680 V. Fig. 21 shows loss breakdown of Topology II. It is evident that total power losses incurred in active filter are very small (for a 23 kW simulation) that makes it a viable topology for 6 f 1 ripple reduction in input current.

D. LOSS BREAKDOWN OF TOPOLOGY III
In Topology III, active filter is used in buck configuration with IBC. Again, the conduction losses in active filter switches are minimal because the active filter processes only fractional power and supports small current. Switching losses in active filter switches in this topology are less as compared to Topology II because of low voltage on the switches due to its buck configuration. This topology is a viable approach for 6 f 1 ripple reduction in input current because of very low power losses in the added components. Fig. 22 shows loss breakdown in Topology III.
A comprehensive comparison of all the topologies discussed is shown in Table 5 in terms of low frequency components in DC input current (6 f 1 and 12 f 1 components), THD in AC line currents, total power losses, total VA rating of switches, inductor and capacitor ratings obtained from PLECS simulation at P = 23 kW and V in = 400 V. It is evident that power loss of Topology II and Topology III are slightly higher than standard topology and Topology I because of the addition of active filter, but they give maximum reduction in undesired low frequency harmonic components in DC input current.

V. EXPERIMENTAL VALIDATION
Three topologies based on two types of schemes to reduce low frequency ripple in input DC current are discussed in Section III. Experimental validation is carried out for the proposed topologies with a scaled down hardware prototype at 1.5 kW in grid-connected mode. Specifications of hardware setup are shown in Table 6. Picture of experimental set-up consisting of DC-DC converter and DC-AC inverter with Silicon Carbide (SiC) MOSFETs is shown in Fig. 23. Two cases will be discussed with Topology I i.e., low V in and high V in . Fig. 24 shows the experimental results at 1.5 kW in gridconnected mode both with original topology and Topology I at low V in of 100 V for DC link voltage of 200 V. The 6 f 1 ripple in input current reduces from 0.8 A to 0.6 A with Topology I i.e., 25% reduction in 6 f 1 ripple is achieved whereas 12 f 1 harmonic is reduced from 0.25 A to 0.1 A (60% reduction). Switching frequency ripple is visible in input current with Topology I that can be easily filtered out using small film capacitors. The AC line currents are sinusoidal and FFT of line current i a shows that the low frequency harmonics are very small on the AC side with Topology I.  Fig. 25 shows the experimental results at 1.5 kW in grid-connected mode both with original topology and Topology I. The 6 f 1 ripple in input current reduces from 0.4 A to 0.2 A with Topology I i.e., 50% reduction in 6 f 1 ripple whereas 12 f 1 harmonic is reduced from 0.2 A to 0.05 A (75% reduction). As expected, the saving in 6 f 1 and 12 f 1 ripple in input current with Topology I at high V in is more because almost all the constant part of DC link voltage comes from input voltage directly. The THD in line current is 3.7% and inverter efficiency is 98.75% with Topology I. At same test conditions, the THD in line current is 3.2% and inverter efficiency is 98.95% with standard topology. Fig. 26 shows the periodic average input DC currentĪ in with Topology I both at low and high input voltage. The switching frequency ripple in input DC current I in in Topology I at low V in (Fig. 24(b)) and at high V in (Fig. 25(b)) is removed in the periodic average input currentĪ in . Moreover, the low frequency ripple inĪ in is very small (y-axis is highly zoomed in). As expected, the low frequency ripple inĪ in is almost negligible with Topology I at high V in as compared to low V in . Fig. 27 shows the experimental result with Topology II where active filter in boost configuration is used. The switching frequency of AF is set to 50 kHz. C a f and L a f are chosen as 5 uF and 560 uH respectively. 6 f 1 ripple in input current is reduced to 0.25 A as compared to 0.8 A with original topology i.e., 68.8% reduction whereas 12 f 1 harmonic is reduced from 0.25 A to 0.1 A (60% reduction) without compromising on THD in grid currents. Power loss in the added components of active filter is very small because of very low power processed by them. Inverter efficiency with original topology is 98.95% and with Topology II is 98.8%. Fig. 28 shows the experimental result with Topology III where active filter in buck configuration is used. 6 f 1 ripple in input current is reduced to 0.25 A as compared to 0.8 A with original topology i.e., 68.8% reduction in 6 f 1

TABLE 7. Comparison of Topologies for Low Frequency Ripple Reduction in Input Current in Grid-Connected Mode From Experiments
component is achieved without compromising much on THD in grid currents and inverter efficiency (98.83%). The active filter voltage (V a f ) in Topology III is much lower than that of Topology II which allows to use low voltage rated capacitor and devices as compared to AF in boost configuration. Table 7 summarizes the comparison of Topology I, II and III with standard configuration at 1.5 kW in grid-connected mode from experiments. Topology I gives lowest 6 f 1 harmonic in input current when the input voltage is high. Topology II and III give the over all best performance in terms of low 6 f 1 harmonic in input current, comparable THD and efficiency as compared to the standard configuration. However, these performance benefits are achieved at the expense of four additional components. Topology III is better as compared to Topology II as lower voltage rated capacitor and devices can be used. The percentage saving in the 6 f 1 harmonic in input current are lower in experiments as compared to PLECS simulation. The experimental results are shown for 1.5 kW whereas PLECS simulation results are at 23 kW.

VI. CONCLUSION
240CPWM is a low-loss PWM method viable for gridconnected PV applications. 240CPWM requires a unique six-pulse dynamic DC link voltage instead of a constant DC link voltage which introduces low frequency harmonics (6 f 1 ) in input DC current and AC line currents. These low frequency harmonics in input current are undesirable as they affect maximum power point tracking (MPPT) in grid-connected PV systems. Three topologies based on two schemes are proposed to minimize the low frequency harmonics in input DC current. It is shown experimentally that the proposed topologies effectively minimize the low frequency harmonics in input DC current in grid connected PV system. Maximum reduction of 68.8% in 6 f 1 harmonic is achieved without any significant impact on THD and inverter efficiency with Topology II and III as compared to the standard topology. Among Topology II and III, Topology III is considered as an over-all best performing topology because of low voltage rating of active filter components.