A Three-Level GaN Driver for High False Turn-ON Tolerance With Minimal Reverse Conduction Loss

This paper presents a three-level gate driver for GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) for high false turn-on tolerance and low reverse conduction loss during both dead time at turn-on and turn-off. The proposed gate driver reduces the reverse conduction loss by clamping between the gate and source terminals only during dead time. It has a capacitor which works as a negative voltage source and prevents from the false turn-on phenomenon. It operates only with a single voltage source and a PWM (Pulse Width Modulation) output signal. The proposed gate driver is implemented on a 48V-to-12 V synchronous rectifier buck (SR-buck) converter and compared with other countermeasure methods for the false turn-on phenomenon. At the condition of 1 MHz, 30 ns dead time, and 120 W output power, the efficiencies of the proposed and conventional operations are 95.1% and 92.8% respectively. The margin between the threshold voltage and the peak of oscillated voltage of the proposed method becomes 1.3 times larger than that of the conventional method on average.


I. INTRODUCTION
Nowadays, power converters with high efficiency and density are required to reduce carbon dioxide. Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) have excellent device characteristics such as fast switching capability, low on-resistance, and zero reverse recovery loss. Thanks to these characteristics, switching and conduction losses can be reduced, and power converters implemented by GaN HEMTs can operate at high frequency with smaller passive elements [1], [2], [3], [4]. Since GaN HEMTs have similar properties to Silicon-based power MOSFETs except for those excellent characteristics, it is also advantageous that existing technologies are easy to migrate.
However, GaN HEMTs are vulnerable to the false turnon phenomenon [5], [6], [7], [8], [9]. If the false turn-on phenomenon occurs, the power loses due to the short-circuit current. In the worst case, the power devices may be broken. GaN HEMTs have lower threshold voltage V th than Siliconbased power MOSFETs. Thus, for GaN HEMTs, the false turn-on phenomenon is more likely to occur than Siliconbased power MOSFETs.
One of general driving method to prevent from the false turn-on phenomenon is to apply a negative bias voltage during off-state [10], [11]. Increasing the margin between the driving voltage during off-state and V th improves the tolerance of the voltage oscillation at the gate terminal. However, applying a negative voltage to the gate terminal increases the reverse conduction loss due to the unique I-V curve of GaN HEMTs [12], [13], [14]. The larger negative V GS becomes, the larger source-to-drain voltage V SD becomes, increasing the reverse conduction loss. Therefore, there is a trade-off between prevention from the false turn-on phenomenon and reduction of the reverse conduction loss.
To resolve them, various three-level gate drivers have been proposed [15], [16], [17], [18], [19], [20], [21], [22]. In these driving methods, negative voltage is applied to the gate terminal at turn-off. After the period when the false turn-on phenomenon may occur, the gate-to-source voltage V GS goes to 0 V to reduce the reverse conduction loss during turn-on dead time. However, since GaN HEMTs turns off with negative voltage, the reverse conduction loss during turn-off dead time remains to increase. In [23], a three-level gate driver to reduce the reverse conduction loss during both dead time has been proposed. However, additional voltage source and control signal are required.
To reduce the reverse conduction loss, the adaptive dead time control techniques have been proposed [24], [25], [26], [27]. In these methods, dead time is optimized by feedback, resulting in reducing the reverse conduction loss. However, accurate dead time control requires high performance control circuit and gate drivers. The performance variation and production cost must be considered. Thus, a simple and inexpensive method to reduce the reverse conduction loss is mandatory.
In this paper, we propose a three-level gate driver for high false turn-on tolerance to minimize increase of the reverse conduction loss. The proposed gate driver can reduce the reverse conduction loss to equalize the voltage levels of the gate and source terminals during both dead time periods. To prevent from the false turn-on phenomenon, the negative voltage applies to the gate terminal at the same time that the voltage oscillation occurs. Since the dead time is over, the large negative voltage can be used, and the tolerant for the false turn-on phenomenon can be improved. The proposed gate driver has a capacitor that works as a negative voltage supply to generate the third level voltage. Thus, it does not require any additional voltage source. In addition, the control signals for the proposed three-level gate driving method can be generated by a general dead time controller using a PWM output signal. Thus, it can operate only with a single PWM output signal. Since it can be also configured to other countermeasure driving methods, we compared them under the same conditions except for gate driving methods.
This paper is organized as follows. We explain the issues of GaN HEMTs and the related works in Section II. Section III presents the proposed three-level gate driver and its operation principle. Section IV shows an experimental setup and measurement results. Finally, the conclusions are given in Section V.

A. SWITCHING ISSUES OF GAN HEMTS 1) FALSE TURN-ON PHENOMENON
In many power converters, phase-leg configurations are used. Regardless of the kind of power devices, the false turn-on phenomenon may cause in these circuits. Due to the false turn-on, there are risks of power loss by the simultaneous turn-on of both switches and power device failure in the worst case. Fig. 1 shows the mechanism of the false turn-on phenomenon in the case of a SR-buck converter described as follows. a) When the low-side switch is off-state and the high-side switch turns on after the dead time is over, high positive dv/dt from the drain to source terminal of the low-side switch is generated. b) By the dv/dt, the Miller current I Miller flows to the gate and source terminals of the GaN HEMT through the Miller capacitor C GD . c) Due to I Miller and the gate resistor R G , voltage oscillation beginning at the positive edge occurs at the gate terminal. If the voltage oscillation exceeds V th of the low-side switch, it turns on undesirably. This is called the false turn-on phenomenon. V th of Si and SiC power MOSFETs are typically around 3 V to 4 V, while that of GaN HEMT is typically around 1 V to 2 V. Thus, GaN HEMTs are more likely to suffer from the false turn-on than Si and SiC power MOSFETs. Moreover, GaN HEMTs have a higher dV /dt at the drain terminal than other power MOSFETs due to their fast-switching capability. Thus, the amplitude of the voltage oscillation may be large.
When the high-side switch turns off, high negative dv/dt from the drain to source terminal of the low-side switch is generated. For the similar reason, current flows from the gate terminal to the drain terminal and the voltage oscillation beginning at the negative edge occurs. If the high-side switch is still off-state, both switches will not turn on simultaneously. However, if it exceeds the threshold voltage of the low-side switch when the high-side switch is not completely off-state, both switches could simultaneously turn on.
The general method to prevent from the false turn-on phenomenon is to drive the GaN HEMT by a negative voltage during off-state. By this method, the margin between off-state driving voltage and V th increases and the tolerance for the voltage oscillation improves. However, an additional voltage source to apply a negative voltage is required, resulting in circuit area increase.

2) REVERSE CONDUCTION LOSS
GaN HEMTs have another issue to increase the reverse conduction loss due to the unique reverse conduction mode.  MOSFETs have a parasitic diode between the source and drain terminals called body diode. Drain current I D flows through a body diode in the reverse conduction mode. Thus, source to drain voltage V DS is equal to the forward voltage of the body diode. On the other hand, GaN HEMTs do not have a body diode. However, GaN HEMTs can behave like a diode in the reverse conduction mode. Fig. 2 shows an equivalent model of GaN HEMTs. Since GaN HEMTs have a symmetrical structure, the channel of GaN HEMTs is formed when V GS or V GD exceeds their V th . In the reverse conduction mode of GaN HEMT, the parasitic capacitor C GD and C DS are charged. After V GD reaches V th of GaN HEMTs, I D flows through the channel. V SD is expressed as In addition, the effective channel resistance R SD occurs the voltage drop. Because V GD is equal to V th in the reverse conduction mode, V SD is expressed as As the result, the I-V curve of GaN HEMTs in the third quadrant is illustrated as shown in Fig. 3. In a SR-buck converter, I OUT and I D are approximately equal in the reverse conduction mode. Thus, the reverse conduction loss P T D(OFF) during turn-off dead time T D(OFF) is expressed as where f SW is the operation frequency. In the condition of the same I OUT , applying a negative V GS in the reverse conduction  mode increases V SD , leading to the increase of the reverse conduction loss. Therefore, there is a trade-off between the false turn-on prevention and the reverse conduction loss increase.

B. RELATED WORKS 1) THREE-LEVEL GATE DRIVER
To prevent from the false turn-on phenomenon and reduce the reserve conduction loss at the same time, the three-level gate drivers have been proposed [15]- [23]. As an example, Figs. 4 and 5 show a capacitor-based three-level gate driver and the operating waveforms of the GaN HEMTs in a SR-buck converter in [18]. To prevent from false turn-on, the GaN HEMT turns off with a negative voltage. After that, the gate terminal goes back to 0 V to reduce the reverse conduction loss during turn-on dead time. To go back to 0 V, they have a Miller clamp circuit or a RC discharge circuit. However, in these methods, the reverse conduction loss during turn-off dead time is still large because the GaN HEMT is driven by a negative voltage during turn-off dead time. In addition, some proposed gate drivers require an additional voltage source and control signal, resulting in increase in circuit size. Moreover, it is required to adjust the parameters of the components such as resistors, capacitors, and zener diode. If more components must be adjusted, it is hard to guarantee the reliability of operation.

2) ADAPTIVE DEAD TIME CONTROL
To reduce the reverse conduction loss, the dead time must be optimized. The dead time is generally fixed. However, the slew rate of the voltage at the switching node depends on the load current. Since the dead time is set for the load current with the smaller slew rate, the dead time is longer for load currents with the larger slew rate, resulting in increasing the reverse conduction loss.
To resolve it, the adaptive dead time control methods have been proposed [24], [25], [26], [27]. In these methods, dead time is optimized by feedback to reduce the reverse conduction loss. However, to prevent from the false turn-on phenomenon, an additional voltage source is required. In addition, accurate dead time control requires high performance control circuit and gate drivers, resulting in higher cost. The performance variation at production must be also considered.

A. GATE DRIVING STAGE
We propose a capacitor-based 3-level gate driver to address the aforementioned issues with high false turn-on tolerance, the reverse conduction loss reduction, and ease to drive. The schematic of the proposed gate driver is depicted in Fig. 6. The gate driver (GD2), the capacitor (C sub ), and the diode (Diode) are added to the 2-level gate driver. The capacitor C sub works as the negative voltage source. Thus, the proposed gate driver operates only with a single voltage source. It works with two control signals and a negative voltage is applied to the gate terminal at the period when Sig2 is low.
The waveforms of the control signals for the proposed 3level gate driving method are shown in Fig. 7. To reduce the reverse conduction loss, V GS is set to 0 V during the turn-on dead time T D(ON) and turn-off dead time T D(OFF) . On the other hand, in order to prevent from the false turn-on phenomenon, the proposed 3-level method applies a negative voltage to the gate terminal from the end of T D(OFF) to the beginning of T D(ON) . Fig. 8 show the operation principle of the proposed gate driver described as follows.
a) GaN HEMT turns on. At the same period, current flows to the ground through C sub and Diode, and energy to use during off-state is stored in C sub .  b) GaN HEMT turns off. To reduce the reverse conduction loss during the turn-off dead time, the gate terminal of GaN HEMT is clamped to the source terminal through Diode. c) Simultaneously turning on of high-side switch, to prevent from false turn-on, a negative voltage is applied to the gate terminal of GaN HEMT. In this period, C sub works as a negative voltage supply. d) To reduce the reverse conduction loss during dead time just before turn-on, the gate terminal of GaN HEMT is clamped to the source terminal through Diode again. In the conventional 3-level gate driver, the component parameters must be adjusted to achieve the recommended negative voltage (from −2 V to −3 V) because large negative voltage during dead time increases the reverse conduction loss [28]. On the other hand, in the proposed 3-level method, the component parameters do not have to be optimized because the dead time is over and the reverse conduction loss does not increase. In addition, the high false turn-on tolerance can be achieved by applying a large negative voltage to the gate terminal. Therefore, in order to apply enough negative voltage, C sub should be larger than the input capacitance of GaN HEMT in use.
Since the proposed gate driver changes V GS back to 0 V at the same time as the high-side switch turns off, the false turnon phenomenon may be less likely occur due to the negative V GS during the initial phase of the voltage at the switching node V SW transition.
A concern is switching characteristics degradation. Compared with a general 2-level gate driver, the rise time are not affected because the turn-on path is the same. However, the fall time is predicted to be slow due to added diode on turn-off path. Therefore, Diode is desirable to have a low forward voltage because it may affect the turn-off voltage.

B. SIGNAL GENERATOR FOR THE PROPOSED 3-LEVEL METHOD
Because the conventional 3-level method clamps the gate terminal to the source terminal during off-state, it needs to generate the dedicated signal such as activating a miller clamp circuit in that time. Thus, the controller could be complex. On the other hand, the proposed 3-level method clamps the gate terminal to the source terminal at the start of the turn-on dead time. The control signal Sig2 can be generated by inverting the control signal of the high-side switch SigHS. Sig2 is easily generated from a general dead time controller using a PWM output signal. The schematic of the general dead time controller is shown in Fig. 9. It generates signals with dead time for the low-side and high-side switches. In the process of generating these signals, the inverting signal for the high-side switch is already generated. Therefore, the proposed 3-level gate driver can operate at the proposed 3-level method by a single control signal PWM OUT in Fig. 10. In the measurement results described in the next section, the proposed 3-level method can be implemented with this signal generator (Fig. 11).

IV. MEASUREMENT RESULTS
In this section, measurement results are shown when the proposed gate driver is implemented to a resistive load circuit and a 48V-to-12 V SR-buck converter.

A. SWITCHING CHARACTERISTICS
To compare the switching characteristics of the proposed and other gate driving methods, the proposed gate driver is implemented on the resistive load circuit. The resistive load circuit for the proposed gate driver is illustrated in Fig. 12. The component names and experimental setups are shown in Tables 1 and 2. The GaN HEMT used is GS61004B (GaN Systems, V th.min = 1.1 V). The gate resistor is set to 1 . We measured V GS and the drain-to-source voltage V DS . From the results,  switching characteristics are compared for the proposed 3level method (P3L method) and conventional methods such as the 2-level method (0 V/5 V) (2 L method) the negative bias 2-level method (−3 V/5 V) (N2L method), and the conventional 3-level method (C3L method) [18]. All methods can be measured on the same print circuit board. N2L, C3L, and P3L methods are changed by Sig2. P3L method can be implemented with the signal generator in Fig. 11. 2 L method is configured by replacing Diode to 0 resistor and removing C sub . The measurement conditions are at 48 V of input voltage V IN , 12 of R load , 1 MHz operation frequency, and 50% duty ratio. The periods of mode (b) and mode (d) for P3L method are set to 50 ns. C sub is adjusted to −3 V of the recommended negative voltage in the conventional methods. Figs. 13 and 14 show the entire and all magnified switching waveforms of V GS and V DS for all methods. According to Fig. 14(a), GaN HEMT is driven by 0 V during 50 ns just after turn-off by P3L method. After that, a larger negative voltage than that of the other methods is applied to the gate terminal. Therefore, it is expected to reduce the reverse conduction loss during not only turn-on dead time but also turn-off dead time and improve the tolerance for the false turn-on phenomenon.   Table 3 shows the evaluation results of switching characteristics. 2 L, C3L, and P3L methods have the same rise time T rise because the turn-on path is common and their V GS start up from the same voltage 0 V. T rise for P3L method is 40% slower than that for N2L method because V GS starting up from a negative voltage gives high dV GS /dt. On the other hand, the fall time T fall for P3L method is 11%, and 9.3% slower than those for N2L and C3L methods respectively because the negative voltage discharges the input capacitance of GaN HEMTs faster. T fall for P3L method is 3.5% slower than that for P3L method. Because the gate terminal is clamped to the source terminal via a diode, P3L method becomes slower. Therefore, it is predicted that P3L method increases switching loss at turn-off more than the conventional methods.

B. 48V-TO-12 V SR-BUCK CONVERTER
To evaluate the tolerance for the false turn-on phenomenon, reverse conduction loss during dead time, and power conversion efficiency, the proposed 3-level gate driver is implemented on the 48V-to-12 V SR-buck converter. A schematic of the SR-buck converter including gate drivers are shown in Fig. 15. The tolerance for the false turn-on phenomenon is evaluated by the margin voltage V margin between V th of GaN HEMT and the peak of the oscillated voltage at V GS of low-side switch V GL .

TABLE 4. The Specifications of SR-Buck Converter
The high-side gate driver is a conventional gate driver. To drive a high-side switch, high-side gate driver has a bootstrap circuit composed of capacitor C BST , fast recovery diode D BST , zener diode Z BST , and resistor R BST . The turn-on and turn-off resistors for the high-side switch are set to 10 and 1 , respectively. The low-side gate driver is the proposed 3-level gate driver. As well as the resistive load circuit, all methods are measured on the same print circuit board. The measurement conditions are described as below.
1) Output power is fixed to 48 W, and dead time is swept from 10 ns to 50 ns (every 10 ns) 2) Dead time is fixed to 30 ns, and output power is swept from 24 W to 120 W (every 24 W) By the measurement condition (1), the dead time dependence of the power conversion efficiency is evaluated. By the measurement condition (2), the load dependence of the power conversion efficiency is evaluated.
The specifications of the SR-buck converter are shown in Table 4. The photograph of the SR-buck converter is shown in Fig. 16. Fig. 17 show the magnified waveforms of gate voltages for all methods. The evaluation results of V margin are shown in Figs. 18 and 19. At the condition (1), the V margin of P3L method is 1.5 times larger than that of C3L method. At the condition (2), the V margin of P3L method is 1.3 times larger than that of C3L method. The negative voltage for C3L method is about −3 V, while that for P3L method is about −4 V. Thus, the proposed 3-level method can improve the tolerance for the false turn-on phenomenon compared to the conventional 3-level method. Fig. 20 show the magnified waveforms of V SW and V GL at the condition of 120 W output power and 30 ns dead time.   In all methods, V GL does not exceed V th before the time V SW reaches 10%. After that, V GL exceeds V th and all methods take 2.0 ns to 2.8 ns to exceed V th due to the high speed turn-off of GaN HEMT and the negative edge beginning of voltage oscillation. Thus, simultaneously turning on of both switches is unlikely to occur due to the high negative edge dV/dt at V SW .     Table 5.
The V SW during turn-off dead time T D(OFF) for P3L and C3L methods are −3 V and −6 V, respectively. Thus, the reverse conduction lose during T D(OFF) is reduced by 50%. The V GL of C3L method during T D(OFF) is −3 V, while that of P3L method   during T D(OFF) is 0 V. Thus, from (2), the V SW during T D(OFF) for P3L method is 3 V smaller than that for C3L method, resulting in reducing the reverse conduction loss.
The efficiencies of all methods except for 2 L method without the tolerance for the false turn-on at the condition (1) and condition (2) are shown in Figs. 22 and 23. At the condition (1), efficiencies of all methods are improved as the dead time becomes shorter. This is because shorter dead time directly reduces the reverse conduction loss. In particular, shorter dead time is effective for N2L and C3L methods. However, even at a shorter dead time, the efficiencies of P3L method are the highest of all. At the condition of 50 ns dead time, the efficiencies of P3L and C3L methods are 94.8% and 92.6%, respectively. Thus, the proposed 3-level method improves the efficiency by 2.2%. From (3), the difference of P T D(OFF) between C3L and P3L methods is 0.6 W, which is equal to 1.2% of the input power. According to Fig. 21, the spike voltage and ringing are caused at V SW . Thus, it is expected that the difference of P T D(OFF) between C3L and P3L methods is more than 0.6 W. Since the measurement condition is the same except for the driving method, the power conversion efficiency is improved due to reduction of the reverse conduction loss.
At the condition (2), according to Fig. 23, the efficiencies of P3L method are the highest of all. As well as at the condition (1), the power conversion efficiency is improved due to reduction of the reverse conduction loss.
Therefore, by using the proposed 3-level method and gate driver without any precise dead time control and multiple control signals, the tolerance for the false turn-on phenomenon and power conversion efficiency can be improved due to the reduction of the reverse conduction loss.

V. CONCLUSION
In this paper, we propose the capacitor-based 3-level gate driver for GaN HEMTs effective in a circuit with a phase-leg configuration. The proposed gate driver can prevent from the false turn-on phenomenon and reduce the reverse conduction loss during both dead time periods only with a single voltage source and PWM output signal.
The efficiencies of the proposed and conventional 3-level methods implemented with the 48V-to-12 V SR-buck converter are 94.8% and 92.6% respectively at the condition of 48 W output power, 50 ns dead time, and 1 MHz operation frequency. Even with a shorter dead time, the efficiencies of the proposed 3-level method are the highest of all. The tolerance for the false turn-on phenomenon is 1.5 times larger than conventional methods on average. By using the proposed gate driver without precise dead time control and multiple control signals, the tolerance for the false turn-on phenomenon and power conversion efficiency are improved due to reduction the reverse conduction loss.