Parasitic Component Inclusive Optimum Phase-Frequency Contour Enabled Synchronous Rectification of Asymmetric CLLC Resonant Converter

With an objective to reduce the switching losses in a bidirectional resonant CLLC DC/DC converter for electric vehicle (EV) charging applications, this paper presents an elaborate frequency dependent general harmonic approximation (GHA) based secondary side turnoff current minimization technique by investigating the optimum operating point to achieve synchronous rectification (SR). Formulation of an accurate all-inclusive gain model is presented, specifically focusing on effect of parasitic components on the resultant gain-frequency trend, backed with thorough experimental validation. Further, meticulous modeling of the GHA based state equations is presented to obtain a contour of feasible operational frequencies and corresponding phase shifts to ascertain accurate SR operation with a multi-dimensional optimization technique to ensure reduced switching losses. In addition to that, to precisely characterize the resonant tank equivalent circuit, stressing on its effect on SR phase calculation, a detailed 3D finite element analysis (FEA) based R-L-C modelling of the employed high frequency planar transformer (HFPT) is explained. To validate and benchmark the performance of the proposed gain model while ensuring accurate SR operation, a 1 kW all-GaN based CLLC experimental prototype is developed for a resonant frequency of 500 kHz, with a power density of 106 W/inch3. Experimental waveforms at corner conditions are presented for a wide-gain bidirectional operation, portraying a peak converter efficiency of 98.49%.

flow, to detect the turn-on instant. The study mentioned in [7] is based on resonant inductor voltage sensing which is used to formulate the instantaneous current flowing through it, which is used to actively detect the turn-on instants corresponding to current zero-crossings. Zhuoran et al. in their study [8] utilize a Rogowski coil and a zero-crossing detector (ZCD) to synthesize the switching instants. However, all the abovementioned methods utilize an extra voltage/current sensor to realize SR, which increases the overall cost and losses in the circuit. Further, in these cases, accuracy of SR highly depends on the sampling frequency of the sensor, which limits their use for high frequency application. In addition, intermediate failure in the auxiliary sensing circuit might adversely affect the power stage due to damage caused due to inaccurate phase tracking.
The studies presented in [9], [10], [11], [12], [13] provide an elaborated time-domain model highlighting the switching instants and formulating detailed system equations, to analytically calculate the required phase for enabling SR. These methods portray superior tracking accuracy, which is sufficiently backed by detailed sensitivity analysis corresponding to change in system parameters. However, these methods include relatively complex mathematical synthesis and solving complicated differential equations for each switching instants with several small signal approximations, limiting its widespread acceptance. In addition to that, these methods do not account for the stray components appearing in the resonant tank, thus rendering the work deficient.
Addressing the limitations of time domain models, the works in [13], [14], [15] utilize frequency dependent first harmonic approximation (FHA) model to synthesize the state equations and corresponding obtain the required phase to enable SR. However, FHA ignores the effect of higher order harmonics in formulating the system equations, thus limiting the accuracy of presented analysis. Further, inaccurate phase tracking based on FHA results in a degraded efficiency due to higher mismatch between the secondary current zero-crossings, leading to higher switching losses. To address the limitations of FHA, the study presented in [16] utilizes an extended harmonic approximation (EHA) strategy to synthesize the phase shift for ensuring minimal switching losses. In addition, detailed sensitivity analysis is also presented which highlights the accuracy of the proposed method for significant changes in resonant tank parameters. However, this method, like all the previously referred works, does not account for the stray components: (a) winding resistance and (b) inter and intra-winding capacitance of the HFPT, leading to inaccuracy in terms of frequency modulation to achieve a particular gain, which significantly affects the resultant phase tracking accuracy.
Addressing the aforementioned limitations pertaining to the state-of-the-art methods of enabling SR, the key contributions of this paper are as follows: (a) Intricately curated all-inclusive GHA based modeling of CLLC converter with asymmetric tank accounting for stray parameters and their effect on the resultant gain trend, highlighting the experimental accuracy of the presented analysis, (b) A non-approximated frequency domain model-derived formulation of required phase shift enabling SR, accounting for the stray parameters and corresponding minimization of turnoff current based on multi-dimensional optimization approach, and (c) Precise parameterization of frequency dependent winding losses in conjunction with thorough analytical characterization of leakage inductance, winding resistance and stray capacitances based on 3D FEA for multiple winding configurations of HFPT.
The rest of the paper is structured as follows: Section II presents the GHA based model of CLLC topology with detailed analysis on the gain derivation accounting for the stray components of the resonant tank. A comprehensive analysis turnoff current minimization approach enabling SR for the secondary side switches is presented in Section III. Section IV characterizes the tank parameters emphasizing the analytical modelling of stray parameters. Further, Section V provides various experimental analysis at different operating conditions to validate the presented analysis. Finally, Section VI points out some conclusive points with relevant discussions. Fig. 1 shows the bidirectional CLLC DC/DC converter topology operating at a resonant frequency f r = 1 2π

II. FREQUENCY DOMAIN GHA BASED EQUIVALENT CIRCUIT SYNTHESIS AND MODELING FOR ASYMMETRIC CLLC
√ L s C s , where C p and C s denote the resonant capacitors for the primary and secondary side, respectively and L p and L s denote the resonant inductors obtained as integrated leakages  from the HFPT designed with a turns ratio of n : 1 and magnetizing inductance L m .
Referring to the application of auxiliary charging systems corresponding to (400-600 V) to (24-28 V) conversion, a turns ratio (n) of 22:1 is selected based on the trade-offs between the core loss and winding loss, to adhere to the unity nominal gain requirement of the CLLC converter resulting in efficient voltage regulation [7], [9], [17], [18]. Fig. 2 shows the FHA based voltage gain magnitude versus the switching frequency ( f s ) trend of the designed CLLC converter for the design specifications mentioned in Table 5. As observed, for a design gain range from G = 0.88 (for 600V − 24V conversion) to G = 1.54 (for 400V − 28V conversion) corresponding to the corner operating conditions, with the selected turns ratio and resonant tank parameter selection, the gain modulation is seamlessly achieved by varying the operational frequency between 200 kHz and 650 kHz.
Please note the tank is considered asymmetric (i.e., L p = n 2 L s , C p = n 2 C s ) to bring in more design flexibility in terms of supporting wider gain range for both forward and reverse power flow. Also, it is practically difficult to ensure that the designer would be able to fabricate a leakage inductance of L s = L p /n 2 , which is in the range of ∼100nH for the high step-down transformer under this study. The advantage of having asymmetric tank structure in CLLC converter is extensively discussed in [18], [19], [20]. As discussed in the referenced works, due to asymmetric nature of L p and L s , the quality factors (Q P and Q S ) (as shown in (1)) and corresponding resonant inductance ratios (m P and m S ) (as shown in (2)) are different for forward and reverse power flows. Further, as observed in [21], [22], the values of Q and m play a crucial role in deciding the profile of the gain curve.
To illustrate the variation of gain trends with respect to different values of Q and m factors, Fig. 3(a)-(b) portray the FHA based gain versus frequency obtained by varying L p and L s , while Fig. 3(c)-(d) portray the input impedances perceived for forward and reverse power flow respectively. Further, as observed, the variations in the leakage inductances affect the maximum achievable gain, the frequency range for the gain requirement, and the gain gradient (dG/df ) for a particular loading condition for forward and reverse power flow. Based on this trend, an iterative design analysis is carried out to comprehend the aspects pertaining to the frequency modulation range for accurate voltage regulation (adhering to the least count precision of the microcontroller) [23], loss budget for understanding the switching/conduction losses at different operational frequencies (based on the RMS values of tank currents) and ensuring inductive operative zone for ZVS (decided by the selection of L m ) [24]. Following this analysis, the specifications as mentioned in Table 5 were selected for ensuring superior efficiency and desired voltage regulation for both forward and reverse power flow by implementing asymmetric tank structure.
Further, to provide intricately curated realistic model highlighting the stray components, a comprehensive HFPT circuit representation is highlighted in Fig. 1 and thoroughly explained in Section IV. As observed, R p and R s signify the effective winding resistances of the HFPT employed. Further, C p,in and C s,in denote the intra-winding capacitances of the primary and secondary windings of HFPT, while C ps,in signifies the inter-winding capacitance between the two windings.
To account for the influence of the above-mentioned stray components on the system performance, the equivalent tank structure shown in Fig. 1 is remodeled using a series of star (Y)-delta ( ) conversions to obtain the effective impedance parameters in equivalent Y and models, as shown in Fig. 4.
To formulate an all-inclusive GHA based gain equation, a detailed multi-harmonic AC equivalent impedance model based on the equivalent tank model is shown in Fig. 5. The resonant tank is excited by a square-wave voltage of magnitude corresponding to the DC input that can be decomposed into a series of multiple sinusoidal voltage sources that essentially accounts for the fundamental and higher order harmonics. Considering G2V operation, for finding the gain equation considering the inclusion of higher order harmonics and the parasitic components, with a constant input voltage source V in , the reactive power flow in the system is assumed to be negligible. This assumption is realized as the tank parameters (mentioned in Table 5) are designed in a way that the superimposed phase lag between V S and I S (obtained as a GHA based superposition of phase lags between fundamental and higher order harmonic components) at operating conditions corresponding to f s > f r and f s < f r is restricted within ±2.5 • at all the corner conditions, which results in the amount of reactive power to be under 4.3% of the total apparent power. Thus, the secondary side can be modelled as a load with equivalent resistance R o,GHA [16], as shown below: k=13,5,...
As observed in Fig. 5, GHA enables the designer to analyze the effect of each harmonic component on the resultant gain by individually formulating the system equations for each component and superposing them to synthesize the equivalent gain. In that context, the input voltage (V p (t )) and corresponding input current (I p (t )) to the resonant tank can be written as summation of 'k' harmonic components as shown below: where , denotes the input impedances and α k = ∠Z e f f ,in,k .
Referring to (11)-(12), the cumulative power input accounting for the series connected voltage sources signifying summation of k harmonic components can be written as: Further, substituting (11)- (12) in (13), the input power is formulated as shown below: The GHA based gain (|G|∠ϕ g ) accounting for all the stray components is derived by equating (15) to invoking the power balance condition as shown below: where, ϕ g is the gain angle which is obtained by finding the angle of equivalent impedance networks used to obtain the gain magnitude (nV o /V in ). Fig. 6 elucidates the gain versus frequency curves for first harmonic approximation (FHA), GHA [16], and the proposed gain model as shown in (16) with the experimentally obtained gain modulation trend for the design specifications mentioned in Table 5. As observed, due to intricately curated gain characteristics accounting for all the stray components in the asymmetric CLLC under study, the presented gain model follows the experimentally obtained gain model with an average mismatch of 0.44%, thus validating the exactitude of presented analysis.
In addition to that, it is worthwhile to note that the accuracy of the proposed all-inclusive gain model depends on the amount of harmonics considered while formulating the analytical model. To understand this dependency, Table 2  elucidates the effect of increasing number of harmonic components included in the analytical model of the proposed method and correspondingly compares the resultant error between the analytical and experimental gain points for four cases.
As observed in Table 2, with a defined mismatch threshold of <0.1% between the analytically formulated and experimental gain values, the order of harmonics considered in the proposed model is limited to k = 31. Further, to prove the accuracy of the proposed all-inclusive gain model, zoomed in snapshots of two instances of the gain plot comparison are presented in Fig. 6. As observed, implementing FHA based modeling, the unity gain point appears at operational switching frequency equal to the resonant frequency (500 kHz). However, when verified experimentally, the unity gain point shifts to 522.3 kHz, which matches the response portrayed by the proposed all-inclusive gain model. This occurs to due to the effect of parasitic components and higher order harmonics present in the system, which is encompassed by the proposed all-inclusive GHA based gain model. In addition to that, the nominal gain point (|G|=1.54) occurs at 248 kHz switching frequency, which also coincides with the plot elucidated by the proposed gain model. The above two instances indicate that the inclusion of parasitic components in the gain modeling plays a crucial role to obtain accurate output voltage regulation.

III. OPTIMUM PHASE-FREQUENCY CONTOUR-ENABLED SR BASED TURNOFF CURRENT MINIMIZATION
With an objective to reduce the on-state conduction losses in conventional diode based secondary side bridge, the use of active switches operating with phase shift (ϑ) with respect to the primary side gate pulses facilitates accurate phase tracking with the switch voltage, resulting in reduced turn-off losses. Further, precise estimation of the mentioned phase shift is quintessential for enabling SR; the failure to do so results in significant turnoff losses, which is directly proportional to the error in phase tracking (ϑ e ). Fig. 7 elaborates on this phenomenon by depicting the inaccurate phase tracking for two cases: (a) f s < f r and (b) f s > f r and compares it with an accurately estimated SR operation.
As observed, due to inaccurate phase shift provided to switch S 5 (represented by dotted lines), the current at turnoff instant is not zero, leading to additional switching losses as seen in (17)-(18).
For cases including operation at f s < f r or f s > f r , a gain angle (ϕ g ) between V P and V S will exist, which needs to be factored in for maintaining the resultant gain for SR operation. In that context, a combination of { f s , ϑ} operating points corresponding to the desired gain and connected load will be required to ensure the required phase shift between the primary (V P ) and secondary (V S ) bridge voltages. In order to synthesize the required phase shift (θ) to alleviate the turnoff losses through SR, a detailed analysis elaborating on the system equations incorporating the effect of stray parameters is presented in this section. Referring to the equivalent model as shown in Fig. 4(d), the secondary voltage can also be synthesized as a combination of 'k' voltage sources, each corresponding to the harmonic content of the quasi-square waveshape, as shown below: where, ϕ g is the gain angle that essentially represents the phase difference between primary and secondary bridge voltages at a particular loading condition.
Utilizing (11) and (19), the current equations in the system can be formulated as follows: Referring to Fig. 4(c), the secondary bridge current i s (t ) can be synthesized (as shown in (24)) as a sinusoidal waveform having a zero crossing at ω s t = ϑ, where ϑ accounts for the effect of additional phase shift required. where, The analytical model developed for i s (t ) provides a generic correlation of operating points (V in , V o , P o ) and is valid for any given set of phase and operational frequency set, where its practical amplitude limit is decided by the load power level. Fig. 8 portrays a phasor diagram elucidating the abovementioned phase relationships between the port voltages and current for 'kth' harmonic component.
Please refer to the terms A k and δ k in (24), which have implicit dependence on the voltage gain magnitude (G) and gain angle (ϕ g ), so the SR accomplishment i.e., the solution of i s (t ) = 0 inherently incorporates the voltage gain constraint. Additionally, the function of i s includes the effects of the operating frequency (ω s ) and SR enabling phase shift (ϑ k ).  To obtain the required phase shift between the primary and secondary side gate pulses, the zero crossing of (24)

A. NEWTON BASED TURNOFF CURRENT MINIMIZATION FOR OPEN LOOP OPERATION
To obtain the most optimum operating point resulting in minimum value of i turnof f , an iterative multi-dimensional Newton method [25] using minimization approach with a residual error margin ( ) of 0.1%, as shown below: where, X denotes a matrix of all the feasible values of {ω * s , ϑ * } and F is the set of non-linear function depicting the values of i s at the switching transition corresponding each possible value of {ω * s , ϑ * } for one switching cycle (t ∈ {0, 2π }), as shown below: Iteratively solving (25) for u iterations, the (u+1)th solution set is formulated as shown below: where, J(X (u) ) denotes the Jacobian matrix, while {F(i s {X } (u) )} represents the residual error of the uth iteration. Further, applying the constraint {F(i s {X } (u) )} < 0.1%, results in optimum set of solution → { ω s ,θ}. It is worthwhile to note that as the formulation of i s (t ) (as seen in (24)) includes the influence of higher order harmonics due to adoption of GHA based approach and the effect of parasitic components in the resonant tank, the solution set ({ f * s = ω * s 2π , ϑ * }) obtained provides an accurate estimate of optimum operating points, resulting in significantly reduced turnoff losses.

B. SR ENABLED PULSE-FREQUENCY MODULATION (PFM) BASED CLOSED LOOP REGULATION
The closed loop regulation of the CLLC converter to achieve the voltage regulation and SR action is shown in Fig. 11. As observed, the sensed output voltage (V o ) is compared with its reference value (V ref o ) to generate the error (V oe ), which is then processed in a PI controller to obtain the value of the frequency shift ( ω s ). The frequency perturbation is then added to ω * s , which portrays an initial estimate of the switching frequency (generally obtained from open loop gain plots), to obtain the required modulated frequency (ω * s + ω s ). A limiter is used to constrain the operational frequency (200 kHz < f * s (= ω * s + ω s 2π ) < 650 kHz) to stay in the limits based on the ZVS criteria, gain requirements and device stresses for forward power flow, while the limiter is set to 430 kHz < f * s < 650 kHz for reverse power flow. This is done by setting the time base period (TBPRD) register limits in the microcontroller employed. Further, a voltage-controller oscillator (VCO) is used to generate the gate pulses for the primary side switches (S 1 − S 4 ) corresponding to the modulated frequency signal. To enable SR for the secondary side switches (S 5 − S 8 ), an additional phase shift (ϑ) is added based on the look-up table (corresponding to Fig. 9) that encompasses the information pertaining to the connected load, realized using a time-variable delay block.

IV. PARAMETRIC R-L-C MODELING OF HFPT FOR ALL-INCLUSIVE GAIN MODEL ESTABLISHMENT
Following the comprehensive gain model highlighting the effect of stray components (C p,in , C s,in and C ps,in ) in the resultant gain versus frequency trend presented in Section II and corelating its dependency on switching loss minimization using SR, it is hence noteworthy to study the effect of different winding configurations based on the structural configuration of the windings. In addition to that, accurate characterization of effective winding resistance to yield minimum winding losses is also essential for ensuring high efficiency power conversion, specifically at higher operational frequencies. It is well established [26], [27] that interleaved winding configurations result in minimized winding losses due to relatively even current density distribution. However, interleaved configurations result in significantly lesser values of leakage inductances, thus rendering it infeasible for the mentioned leakage integrated CLLC converter design. Referring to the above-mentioned objectives, a detailed 3D FEA based R-L-C analytical modelling and quantification is presented in this section for non-interleaved winding configurations (see Fig. 12).

A. ANALYTICAL MODELLING FOR R-L-C SYNTHESIS
Complying to the objective of achieving higher power density, thus eliminating the external resonant inductors, adjustable air gaps between the core (h w ) and the windings (h g ) are provided to enable intentional flux leakage in a controlled manner. Corresponding to this leakage flux, the linked electromagnetic energy (∈) is used to analytically quantify the leakage inductance as shown as follows: where, μ o represents the permeability of the core, H denotes the field strength, which is formulated by the ampere turns linked, l w is the length of each winding, b w is the window width of the core and h t is the thickness of the conductor. Further, dl is the incremental thickness situated at a distance of l from the inner surface of the conductor, as observed in Fig. 12. Utilizing (31), the leakage inductance can be analytically formulated as: where, I w represents the RMS value of primary/secondary winding current, n x ; x ∈ {12, 3..k} denote the number of windings in each layer. Further, to quantify the AC winding losses in the HFPT analytically, Dowell's equation [28] is employed, that formulates the ratio of AC resistance (R ac ) to the winding DC resistance (R dc ) for different winding configurations, as shown below: where, MMF(k) denotes the magnetomotive force (MMF) of windings in layer k, ρ is the resistivity of the conductor and γ = h t δ , where δ is the skin depth. As observed in Fig. 12, the MMF increases linearly proportional to the NI product of the winding layers, which results in higher R ac R dc for the inner PCB layers. Fig. 12 also shows the voltage distribution of the primary winding which is assumed to vary linearly according to the turn distribution for each layer. Thus, the potential at each turn of the winding (V u ) can be formulated as: Referring to the voltage difference (V uv ) between two adjacent winding or windings in two adjacent layers, a virtual capacitor is created accounting for the overlapping surface area of the conductors and corresponding distance between them.
Where, ε o and ε r denote the permittivity of air and relative permittivity of the dielectric material respectively, S uv is the overlapping area between turns u and v as observed in Fig. 12 d uv denotes the spacing between the two conductors, w o,uv is the overlapping conductor width and dl represents an infinitesimally small sectional length of a turn, which is integrated over the entire circumference to form a complete turn of length l t . Thus, the inter (C wy,in ) and intra-winding (C w,in ) capacitance can be formulated as follows: where, q denotes the number of conductor overlaps, n wy is the number of windings in the last layer of primary winding and w wy is the width of each winding.

B. 3D FEA MODELING, VERIFICATION, AND COMPARATIVE ANALYSIS
To verify the analytical formulations presented to characterize the HFPT parameters and to choose the most optimum winding configuration resulting in minimum winding losses, three winding configurations are compared in Table 2 for a 4-layer PCB for primary (connected in series) and secondary (connected in parallel) winding by solving the FEA model in ANSYS Maxwell electrostatic and eddy current solver. As observed in Table 3

C. SENSITIVITY ANALYSIS OF THE HFPT COMPONENTS
As the HFPT parameters are prone to change in temperature, operating condition and layout, it is important to understand the effect of variation of the tank parameters with respect to change in resultant gain, optimum phase and operational frequency of the system. To elucidate this change, a sensitivity term (S M N ) [29] is introduced, that is defined as the relative change in the parameter M with respect to relative variation in parameter N.
Further, Table 4 shows the analytically calculated sensitivity of resultant gain (G), the optimum phase shiftθ and the operating frequency ( ω s ) with respect to ±15% variation in the tank parameters. As observed in Table 4, the change in the resultant operating points (G,θ and ω s ) is relatively small for changes in the tank parameters. On the other hand, the sensitivity of stray capacitances is relatively larger that might lead to considerable changes in the optimum operating points. However, as observed in (38) and (39), the values  of stray capacitance depend on the dielectric constant of the insulation used and the overlapping conductor thickness and relative distance between them. As the copper windings are fabricated in the PCB, their thickness and dimensions are relatively constant for any given operation status, temperature, or aging. Further, the dielectric coefficient of the FR4 material also remains constant with temperature (typical range of operation: −20 • C to to 170 • C ) as verified in [30], [31]. It is also ensured that the thickness of the windings of the HFPT are selected in such a way that at rated load condition, the temperature rise is limited to 40°adhering to IPC 2221 [32]. To validate the same, a thermal image depicting the winding temperature at the rated loading condition is shown in Fig. 13. Thus, the values of stray capacitances are relatively unfazed with change in temperature, aging or operation status, thus leading to minimal effect on the resultant gain, optimum SR phase shift and the operating frequency.
In addition to that, the value of magnetizing inductance (L m ) depends on the selected magnetic core which portrays non-linear relation in permeability with change in operational frequency [33]. In that context, the resultant value of L m depends on the reluctance ( ) offered by the core, and can be analytically formulated as: where, A e and l e denote the effective area and length of the core respectively and μ r is the relative permeability of the core. Please note that for the selected magnetic core (FR45810EC) with a specific value of h g , μ r varies nonlinearly with the operational frequency ( f s ), which for the CLLC resonant converter topology is modulated as per the loading conditions, due to its dependency with the resultant gain (G). Referring to the material properties of R-material [34], it was observed that the sensitivity of μ r with respect to frequency variation for the required gain range at all loading conditions (G ∈ [0.88 to 1.54] for f s ∈ [200650] kHz) is S μ r f = dμ r /μ r df s / f s < 1.29%, leading to a sensitivity in resultant L m with respect to μ r to be S L m μ r = dL m /L m dμ r /μ r < 1.62%. Utilizing this dependency, the gain trend for selected specifications experiences a variation of <1.85%, which validates the core selection and its variation with a negligible effect on the output voltage regulation and corresponding SR action.

V. EXPERIMENTAL VERIFICATION AND BENCHMARKING
To validate the findings and analysis presented in the previous sections, an experimental prototype (as shown in Fig. 14) is developed for the specifications corresponding to auxiliary charging systems for ground military vehicles [35], [36] as mentioned in Table 5, and detailed analysis elucidating results obtained for both light and heavy loading conditions are presented. This prototype is developed with a targeted application of bidirectional EV charging, where the high voltage side corresponds to a DC link voltage of 400 V-600 V nominal, while the low voltage side corresponds to a battery at 28 V nominal with a depletion threshold of 24 V [37], [38]. In addition to that, following similar investigation pertaining to the gain FIG. 14. Experimental proof-of-concept for developed CLLC converter.

TABLE 5. Design Specifications For Bidirectional CLLC
and phase shift requirement, experimental results of reverse power flow are also presented accounting for the switching loss minimization objective. The required gate pulses with a phase shift enabling SR are provided using TMS320F28379D dual-core digital signal processor. The primary side bridge is realized using Transphorm TP90H050WS (900 V, 22 A, 63 m ) cascode GaN-FETs, while the secondary side consists of four EPC2020 (60 V, 90 A, 2.2 m ) switches connected in parallel, thus enabling an all-GaN power converter solution, ensuring a superior power density of 106 W/inch 3 . Following the analysis presented in Section IV, an accurately modelled HFPT is fabricated using {7P-4P-4P-7P, 1S-1S-1S-1S} winding configuration, thus facilitating reduced winding losses and achieving required integrated leakage inductance. Magnetic planar EE core FR45810 from Mag Inc. is used to realize the HFPT, that results in a core loss of 4.2 W for an operational frequency of 500 kHz.
A comprehensive flowchart to elucidate the optimization approach and its implementation is presented in Fig. 15. As observed, with the knowledge of the design specifications and HFPT parasitic components, an offline calculation of optimum operating points is executed using multi-dimensional Newton optimization method. With respect to the cost function (min i turnof f ) defined, the function F (i s {X (u) }) is solved iteratively and corresponding error {F (i s {X } (u) )} is calculated for every iteration. The algorithm converges when the criteria: {F (i s {X } (u) )} < 0.1% is satisfied (which indicates that the function has reached its minimum value), resulting in operating points { ω s ,θ} that correspond to minimum turnoff current. To quantify the stop criteria for the optimization algorithm, Fig. 16 portrays the plot of the error with respect to number of iterations. As observed, the function converges after 54 iterations, when the error values satisfy the convergent criteria ( {F (i s {X } (u) )} < 0.1%). The number of iterations can be further reduced by adding a learning coefficient α k in the optimum point tracking process [25]. These optimum points are stored along with the load information in the microcontroller (TMS320F28379D) as a lookup table. The number of entries in the lookup table significantly affects the accuracy of SR control, which is selected by analyzing the storage space and corresponding computation time of the microcontroller and % efficiency degradation (as compared to 1% variation in load) on account of linear interpolation applied to the nearest entry in the lookup table. In that context, Table 6 provides the analytical comparison of increasing number of lookup table entries with respect to accuracy of SR tracking.
As observed in Table 6, by restricting the mismatch to <1% (avg.) corresponding to an efficiency degradation of 0.84%, the number of lookup table entries can be restricted to 33, thus ensuring accurate SR tracking while avoiding any additional computational burden to the microcontroller employed. For open loop operation of the developed converter at the optimal operating point, the load information is sensed, and corresponding gate pulses are given to switch S 1 to S 4 having a switching frequency of f s = ω s 2π . In addition to that, the gate pulses are shifted by a phase ofθ and are applied to secondary side switches (S 5 to S 8 ) to obtain the required SR action.
Please note, due to significantly high magnitude of I s , the interface between the HFPT and secondary bridge PCB is made using 20 Litz wires of same specification, connected in parallel to (a) facilitate near-equal sharing of current amongst all the wires and (b) to minimize any additional stray inductance, thus ensuring optimal tank design. Relevant experimental results for I s have been obtained by probing one of the Litz wire. resulting in minimum switching losses (of 62 mW), portraying a strong agreement with the presented analysis, having a mismatch of 0.29% only. As observed, the instantaneous current at turn-off instant is significantly less (∼1.4A), which ensures ominously reduced turnoff losses for the secondary side switches. Further, as observed in Fig. 18, the primary current lags the primary bridge voltage thus achieving ZVS operation [39] (i p < 0 at turn-on), which matches the presented analysis and justifies the winding selection and ZVS based constraint.
In addition to that, as observed in Fig. 17, as the optimum operating point occurs at f s < f r , there is a small phase lag (<1.7 • ) between V S and I S , where the reactive power (Q) of the system is not zero. This phase refers to the superimposed phase lag obtained as cumulative phase difference between fundamental and higher order harmonic components obtained by GHA based harmonic decomposition of V S and I S . But, as this lag is relatively small and falls in the ±2.5 • limit as discussed in the initial assumption adopted (10), the Q due to this phase lag is negligible and does not interfere with the SR action, maintaining reduced switching losses at the secondary side.
To elucidate the wide-gain capability of the designed converter, Fig. 19 shows experimentally obtained waveforms for 400-24 V conversion, with its optimum operating point located at { f s , ϑ} = {452.5 kHz, 42.2 • }. As observed, the primary switches undergo ZVS turn-on, while the secondary side switches experience minimal switching losses (84 mW) accounting for the comprehensive phase identification method used to enable SR.
Further, to elucidate the optimum SR phase and frequency tracking for a higher voltage step down condition, Fig. 20 portrays the experimentally obtained waveforms for 600 V-28 V conversion at the rated load of 1 kW. As observed, the ZVS and SR operations are retained, thus also achieving superior efficiency for a wide input voltage gain range.
While adhering to the efficiency maximization objective by reducing the secondary side switching losses at higher loading conditions, the presented analysis also portrays its effectiveness in light loading conditions. Fig. 21(a)-(b) illustrates the converter operation at 10% load, while achieving the required gain range to obtain V o = 28 V and V o = 24V , respectively. As observed, ZVS operation is maintained, while the turnoff losses at the secondary side are limited to 59 mW due to accurate SR tracking.
Further, to portray the feasibility of efficient reverse power flow for V2G applications, Fig. 22 shows experimentally obtained waveforms implementing the optimal phase detection method as explained in Section III. As observed, the turnoff current is reduced to ∼ 0.5A that corresponds to switching losses of only 62 mW in the secondary side, in addition to ZVS at the primary side, leading to reverse power peak efficiency of 96.2%.
To benchmark the efficiency improvement of the proposed SR method for 400 V-28 V and 400 V-24 V conversion, a detailed analytical loss breakdown at rated load of 1kW is provided in Table 7, that compares the various aspects of system losses for FHA, GHA, and the proposed method. As the SR action maintains a near-zero phase angle between secondary current and bridge voltage fundamental, it results in the least RMS current for a specific power transfer amount and reduces the device and winding conduction losses, when compared to other conventional FHA and GHA methods. Therefore, an illustrative loss breakdown for 400 V-28 V and 400 V-24 V conversion is graphically presented in Fig. 23. As observed, due to the accurate characterization of the system parasitics and inclusion of all the higher order harmonic components in the analytical model, the steady state values of SR enabling phase shift (ϑ) and operational frequency (f s ) obtained from the turnoff current minimization algorithm result in significant reduction of the SR phase tracking error (ϑ ε ) (less than 0.1%), as compared to the FHA and GHA based approaches (∼12% and ∼4% respectively). This ensures substantial reduction in the switching losses incurred in the secondary side, thus portraying a reduction of 77.9% and 46.4% in the overall switching losses for a 400 V-28 V conversion as compared to FHA and GHA based approaches respectively. Moreover, as observed in (44), for the same amount of output power (P o ) processed in the converter, as the phase lag error (ϑ ε ) is reduced, the RMS value of secondary side bridge current is also reduced, which results in reduction in the conduction losses of the switches (31.1% and 23.4% as compared to FHA and GHA respectively) and AC winding losses of the HFPT (22.4% and 21.3% as compared to FHA and GHA Further, Fig. 24(a) compares the forward power flow efficiency trend, while Fig. 24(b) portrays the reverse power flow efficiency trend for various loading and corner gain conditions. As observed, due to elaborate and precise modelling accounting for the stray components affecting the system operating point, the proposed model yields a peak efficiency of 98.49% at an ambient temperature of 22 • C , depicting its superiority even at a high operational frequency. The main reasons leading to this enhanced efficiency profile trace back to the aspects including the employment of GaN devices that portray ultra-low body capacitors [40] and low R ds,on [41] resulting in reduced switching and conduction losses, optimized selection of phase-frequency operating point to facilitate reduced turn-off losses in the secondary bridge, and an optimum HFPT winding selection leading to reduced winding resistance and corresponding high-frequency AC losses.

VI. CONCLUSION
Meticulously considering the effect of stray parameters on the performance of a bidirectional asymmetric CLLC DC/DC converter, a comprehensive GHA based modeling and analysis is presented in this paper. Stressing on the influence of the stray components, a detailed all-inclusive gain model is derived, which is further validated with several experimentally obtained gain points, portraying an average mismatch in gain modulation trend of 0.44% only, thus confirming its accuracy. Unlike other state-of-the-art methods focusing only on phase modulation or frequency modulation, the proposed SR phase detection technique provides a contour of feasible {ω * s , ϑ * } points for different gain/load operations. Further, a non-linear multi-dimensional minimization function for the secondary current zero crossing is defined with an error margin of 0.1%, that tracks the phase required to facilitate SR, and is experimentally verified elucidating a phase error of 0.29%. To facilitate the proposed SR tracking method and to ensure optimum transformer design, a thorough parametric RLC modeling of HFPT aided with detailed 3D FEA analysis is presented. To validate the presented model and SR phase detection method, exhaustive experimental analysis for a 1kW prototype operating at 500 kHz resonant frequency with results at various corner conditions are presented. Experimental results for forward power flow for 400-28 V and 400-24 V are provided which portray a turnoff current of ∼1.4A, highlighting reduction in switching losses, thus achieving a peak efficiency of 98.49%. In addition to that, the reverse power flow capabilities of the designed converter are also verified for different conditions (28-400 V and 24-400 V), which due to accurate phase detection, portrays a peak converter efficiency of 96.2%.