Model Predictive Controllers With Capacitor Voltage Balancing for a Single-Phase Five-Level SiC/Si Based ANPC Inverter

Employing both high bandwidth (HBW) controller and wide bandgap (WBG) devices in the structure of converters improve the system size, performance, and efficiency. In this paper, HBW model predictive controllers (MPCs) are proposed, with both fixed and unfixed switching frequencies, to control a single-phase five-level hybrid active neutral-point-clamped (ANPC) inverter. A hybrid modulation technique is considered in this paper, in which some of the switches are modulating with high frequency. Therefore, Silicon-Carbide (SiC) MOSFETs are employed in the converter structure to increase the switching frequency and consequently reduce the filter size and increase converter power density. To have the functionality of multilevel output voltage, some restrictions are defined in the adopted MPC with unfixed switching frequency. In the MPC with the constant switching frequency, predefined switching sequences are employed for all sectors. Moreover, to control the neutral point (NP) voltage, the applied times of both small voltage vectors are sets through a cost function. Finally, the simulation and experimental results prove the ability of both proposed methods to control the voltages of the load and NP.

Step time t x Applied time of vector x t y Applied time of vector y t y1 Applied time of first small vector t y2 Applied time of second small vector λ Weighting factor S k (k = 1 …8) Switch number V i (i = 1 …8) Output voltage vector

I. INTRODUCTION
With increasing the penetration of renewable energy and energy storage systems, the demand for power converters as a key role is rising [1]- [3]. Among these applications, singlephase converters are employed in photovoltaic (PV), electric railway traction, and power factor correction applications [4]- [9]. Compared to the conventional two-level converter, multilevel converters have become more interested due to their superior characteristics, such as lower dv/dt, improved current and voltage total harmonic distortion (THD), lower common-mode voltage, and smaller filter inductance [10], [11]. The three main structures of multilevel converters are Neutral-point-clamped (NPC), flying capacitors (FC), and cascaded H-bridge (CHB) converters. One interesting topology for single-phase application is the 5-level single-phase NPC converter, which presents high efficiency and compact design compared to a 3-level converter [6], [12], [13]. One of the derived topologies from NPC structure is a 5-level singlephase hybrid active NPC converter [6], in which just eight switches are utilized. Moreover, this structure presents the ability of hybrid switching frequency to improve the efficiency of the converter. Meanwhile, employing recent emerging of wide bandgap (WBG) switches such as SiC MOSFETs can improve the efficiency and reduce the converter size.
Apart from the topology of the converter, controlling the converter is a determining issue. A wide variety of control strategies have been discussed for single-phase converters, such as proportional integral derivative (PID), and proportional resonant (PR) and current hysteresis controls, etc [14]- [17]. However, these linearized controllers suffer from slow dynamic responses. Therefore, the implementation of novel and complex control algorithms such as model predictive control (MPC) have been considered and proposed in the literature with the release of advanced and fast microprocessors, digital signal processors (DSPs), and field-programmable gate array (FPGA) platforms in the market [12], [17]- [24]. The MPC strategy, as an interesting alternative controller, utilizes the mathematical model of the system to predict the behavior of converters. In fact, the controller can predict the future behavior of converters based on the discrete characteristics of the power electronic converter and the system output values. A cost function is also employed to determine the next switching state of the converter to find the optimum operation mode. Meanwhile, this process is repeated at the next sampling cycle [12], [17], [25]. One of the popular MPC strategies is finite control set MPC (FCS-MPC), in which the output voltage vectors of a converter are considered as the control inputs to handle the optimal control problem [12], [26]- [28]. The most advantageous features of FCS-MPC are its fast-dynamic response, the simplicity of its implementation, and the ability to integrate advanced control objectives in the design of its cost function [12], [17]. Moreover, the need for switching modulators and inner control loops and their delays are eliminated by employing the FCS-MPC. Therefore, the system can be operated with higher bandwidth and faster performance [29]. However, this FCS-MPC strategy employs only one output vector of the converter in every control period. Thus, the switching frequency of the converter is unfixed [12], [13], which can be counted as the main disadvantage of FCS-MPC.
To deal with the unfixed switching frequency of MPCs, several techniques, e.g., optimal switching sequence, have been presented for single-phase converters [12], [13], [17], [30]. In [13], an MPC based on the optimal switching sequence has been proposed for a single-phase H-bridge NPC. However, NP voltage balancing is not considered. The same MPC with controlling the NP voltage has been modified in [12]. Ref [17] developed an MPC with a fixed switching frequency for a T-type inverter, in which the idea of space vector pulse-width modulation (SVPWM) is utilized by defining switching patterns in different sectors. In [30], an MPC with a fixed switching frequency based on the SVPWM has been proposed. However, the SVPWM block is included in the controller loop, which leads to system delay and sluggish dynamic performance. Although MPC methods have been upgraded to track different setpoints, modifications still are required based on converter topologies and desired factors.
This paper investigates the utilization of HBW control system for a single-phase 5-level hybrid SiC/Si ANPC topology with high switching frequency. The control system includes two different FCS-MPCs with unfixed and constant switching frequencies. In the first method to improve the THD of output voltage, some restrictions regarding the selection of the output voltage vectors are defined. With these restrictions, the waveform of the output voltage is changed between defined levels. Considering the switching frequency is not fixed in the first method, designing the filter would be challenging and leads to a large output current ripple. Therefore, an enhanced MPC with constant switching frequency is utilized, which is based on the idea of SVPWM [17] for each sector, a predefined switching sequence is defined. To regulate the NP voltage, the effect of different output vectors is studied, and a sub cost function is allocated in both methods. A prototype of the converter is used to experimentally validate the proposed control schemes, wherein 50 kHz switching frequency is implemented by an FPGA. In summary, the main contributions of this paper are as follows: 1) Proposing two high bandwidth MPCs for a 5-level highfrequency SiC/Si inverter. 2) Developing unfixed switching frequency MPC (adopted MPC) considering the converter restrictions and switching states to achieve an improved output voltage waveform. 3) Proposing a modified MPC with constant switching frequency based on the SVPWM idea for the considered structure to obtain staircase output voltage. 4) Embedding the NP voltage balancing algorithm in both proposed MPCs.

5) Digital model-based implementation of the proposed
MPCs through FPGA. The rest of the paper is organized as follows. The 5-level single-phase ANPC inverter structure and mathematical modeling are presented in section II. Section III presents the proposed model predictive control algorithms. The simulation and experimental results for both methods are demonstrated in section IV. Finally, section V concludes the study.

II. SYSTEM STRUCTURE AND MODELING
The general schematic of the system based on the single-phase hybrid active NPC is shown in Fig. 1. The system consists of a constant dc source (V DC ) as a supplier, the converter, an LC filter, and a load.
In the structure of the converter, eight power switches (S k , k = 1, 2 …, 8) and two dc-link capacitors (C p and C n ) are utilized. Five voltage levels at the output of the converter can be constructed by employing different combinations of switching states. To reach a hybrid switching frequency, eight switching states can be utilized, which are listed in Table 1. During the whole positive half cycle, S 5 and S 8 are conducting, and the conditions of S 1 -S 4 are altered to reach different output voltage levels. Meanwhile, S 6 and S 7 are in the on-state condition in the negative half cycle, and S 1 -S 4 are modulating with higher switching frequency. Therefore, the switching frequency of S 5 -S 8 is fundamental or 50 Hz in this study. Moreover, two different switch technologies, including SiC and Si MOSFETs, are employed due to devices switching frequencies.
Based on the magnitude of the reference waveform, the voltage vector diagram of a 5-level converter can be divided To develop MPC, the mathematical modeling of the converter, including the filter and the load in AC and DC sides, is vital. Based on the circuit of Fig. 1, the relation between the output voltage of the converter (v ab ), the current of the filter inductor (i c ), and the voltage across the load (v d ) can be written as follows: where L c and R c are the inductance and resistance of filter inductor, respectively. The relation between the currents of filter inductor, filter capacitor (i c ), and load (i f ) can be noted as follows: where C d is the value of the filter capacitor. Therefore, the converter output voltage and current can be shown in the statespace form as follows: For the DC part of the converter, the NP current (i o ) is equal to the current of the filter inductor (i c ), whenever small vectors are employed. The effects of small vectors on the NP voltage variations are shown in Table 2. Moreover, the voltage of upper and lower dc-link capacitors (v p , v n ) based on the current of dc-link capacitors (i p , i n ) can be found through the following equations:  where C p and C n are the capacitance value of dc-link capacitors. In addition, the NP voltage is indicated as:

III. MPC SCHEMES
The main objects of the control method are to appropriately set the output voltage of the converter (v ab ) so that the voltage across the load (v d ) can follow the reference voltage and to control the NP voltage variation. In this section, two different MPC controls are presented.

A. ADOPTED MPC
The cost function of adopted MPC for 5-level ANPC converter is defined as follows: where λ 1 and λ 2 are weighting factors to reduce the current ripple and to balance the NP voltage, respectively. The defined cost function is comprised of three subfunctions. The main subfunction is the first part, which tries to find the best vector for tracking the reference voltage. The purpose of the second part of the cost function is to reduce the current ripple at the filter inductor by comparing the output current of the converter with the filtered load current. The third subfunction of the cost function is employed to regulate the NP voltage. Each vector has a different effect on the value of cost function through (3), where v ab is replaced with the output voltage vectors. As mentioned earlier, the small vectors have different effects on the NP voltage. The dc-link capacitor voltages for the small vector can be obtained as follows: where T s is the discrete step time.
The flowchart of the proposed MPC is shown in Fig. 3. The flowchart is divided into two sections based on the value of the reference voltage. The reasons are 1) to keep the switching frequency of S 5 , S 6 , S 7, and S 8 at 50 Hz and to prevent any unwanted transitions during zero-crossing between positive and negative half cycle, 2) to decrease the computational time of the controller implementation. Besides, some restrictions are defined to have the functionality of multilevel output voltage. These restrictions can be found through the four subbranches in each section, in which, based on the previous output voltage vector, the subbranch is chosen (block 1). For example, when v ab (n) = V DC , the next applied vector can be the same vector or the vectors with half of the dc-link voltage (v ab (n + 1) = V DC or V DC /2). Otherwise, the output voltage of the converter changes from V DC to 0, which increases the current ripple at the filter inductor, the magnitude of harmonic contents, and THD of the output voltage. In each subbranch, the cost function (7) is calculated for considered output voltage vectors, where i defines V i as the output voltage vector that are listed in Table 1. In the next step, the output voltage vector with minimum related cost function is selected to apply (block 1). This state is shown as the best vector selection in the flowchart. Finally, the commands of switches are determined by defining the switching commands function (block 3). Besides, the employed output voltage vector is used to define the next output vector. Moreover, two subsections are employed for the transition during zero-crossing to apply a zero-voltage output vector (V 4 or V 5 ) in each section (block 2).

B. ENHANCED MPC WITH CONSTANT SWITCHING FREQUENCY
In the previous MPC, the switching frequency is unfixed, which leads to large output current ripple, and consequently, the current harmonics are distributed in a wide range of frequency. Meanwhile, employing the idea of SVPWM to reach a constant switching frequency can reduce the output current ripple and having current harmonics at switching frequency and multiple of it [17]. Moreover, increasing the switching frequency of the converter reduces the size of the passive components of the filter. Decreasing the size of the inductor and capacitor of the filter reduces the reactive power consumption of the filter and consequently reduces the phase difference between the input and output voltages of the filter. Therefore, it can be assumed the v ab and v d are in phase. Considering the voltage vector diagram of the 5-level single-phase converter, as it is shown in Fig. 2, for each sector, a predefined vector sequence is considered. The predefined vector sequences are listed in Table 3. In addition, the applied times of different vectors (t x , t y ) are shown in Fig. 2. It is worth mentioning that both available small vectors are employed with adjustable time duration (t y1 , t y2 ) in each switching sequence to control the NP voltage.
In this MPC algorithm, the cost function is defined as follows [17]: where v d (n + 1) * is the reference waveform and v ab (n) is the output voltage vector of the converter. Considering (9), the value of the cost function for small vectors of each sector is the same. These values are described as follows: The reference voltage can be applied through the vector sequence with a defined time duration as follows: v re f T s = v x t x + v y t y T s = t x + t y (11) where v ref = v d (n + 1) * , v x and v y are the voltage vectors related to the considered vector sequences for each sector. According to (11) the applied time duration of vectors can be calculated. For example, v x is set to be the full dc-link voltage vector (P), and v y will be the small vectors of HP + and HP − in sector I. Moreover, t y is divided between small vectors. Thus, the applied time of each vector is derived as follows: ⎧ ⎨ ⎩ t x = T s (1/CF x (n))/((1/CF x (n)) + (1/CF y (n))) t y = T s (1/CF y (n))/((1/CF x (n)) + (1/CF y (n))) t y = t y1 + t y2 (12) where t y1 and t y2 are the applied times of the first and second applied small vectors for each sector as it is described in Table 3.
To find the best vector sequence, another cost function is defined for each sector as (13) [17].
Therefore, the sector cost function with minimum value will be selected, and related execution times are applied.  Compared to [17], to control the NP voltage, another function with consideration of output current is defined as follows: where λ is a weighting factor in regulating the NP voltage.
Based on the voltage difference of upper and lower dc-link capacitors, the applied time duration of the small vector for each sector will be modified as (15) to keep the NP voltage constant.
The flowchart of the proposed MPC with constant switching frequency is shown in Fig. 4, which is divided into two sections based on the value of the reference voltage. In each section, three cost functions of (9), (13) and (14) are calculated. For example, when the reference voltage is positive, first the cost functions of four positive output voltage vectors (V 1 , V 2 , V 3 and V 4 ) are calculated based on (9). After that, the cost function of the two positive sequences of I and II are determined by using (12) and (13). The sequence with a lower value of CFS is selected through the best sequence selection function in the flowchart. After that, the cost function of NP voltage balancing of (14) is determined, and consequently, the applied time duration of each vector is calculated through   (15). Finally, the switches commands are determined in the last function.

A. SIMULATION RESULTS
In order to verify the ability of employed MPCs, two simulations for both the MPC algorithms are performed. The parameters of the system are listed in Table 4. The simulation results are shown in Fig. 5. Fig. 5(a) and (b) show the output voltage of the converter for adopted MPC and MPC with constant switching frequency. By comparing Fig. 5(a) and (b), it can be seen that there are fewer transitions between sectors when the MPC with constant switching frequency is applied. However, when adopted MPC is utilized, there are many transitions between sector 1 and sector 2 or sector 3 and 4. These transitions increase the current distortion and consequently increase the THD of the output current. This fact is shown in Fig. 5(c), (d), wherein the THD of current for constant switching is less than 1%.
Moreover, the Fast Fourier Transform (FFT) results of output voltage for both MPC are depicted in Fig. 5(e) and (f). Fig. 5(e) is related to the adopted MPC. As can be seen, the harmonics are spread in a wide range of frequencies. This leads to using a bulkier output filter. Fig. 5(f) shows the FFT result of MPC with constant switching frequency. Since both small vectors are employed in each switching cycle, the first major harmonics appear at twice the switching frequency (100 kHz). Thus, the filter is designed based on this frequency, in which the filter inductor is roughly 50% smaller than other MPC. In addition, Considering the sampling time of 10 µs, the maximum switching frequency at the output voltage of the converter can be 50 kHz for the adopted MPC. Therefore, the equivalent switching frequencies of the presented methods are not equal. By comparing the results of both MPC, it can be recognized that the MPC with constant switching frequency shows a better behavior in terms of converter current ripple and THD of the output voltage. Moreover, based on the FFT results, an LC filter with a higher cutoff frequency is required for MPC with constant switching frequency.
To show the behavior of the controller during transitions, a simulation is carried out for the MPC with the constant switching frequency and a traditional control scheme with a carrier-based modulator. In a traditional control scheme, a voltage control loop with a PR controller is designed to regulate the output voltage (voltage across the load), in which the PR controller provides a reference waveform for a modulator. In addition, the carrier-based modulation technique of [31], [32] is modified to control the NP voltage. The same simulation parameters are employed for both methods. In this simulation, the reference voltage is changed and the transient responses of two systems are captured, as are shown in Fig. 6. As it can be seen, both controllers follow the reference voltage with fast response; meanwhile, the MPC with constants switching frequency reaches to steady state shortly after the transition. However, for the PR controller, it takes a longer time to pass the transition.

B. EXPERIMENTAL RESULTS
The prototype of the converter with the designed filter is shown in Fig. 7, where SiC and Si MOSFETs are employed. The considered MPCs are implemented with the dSPACE's Micro-Lab Box ds1202, which the control part is carried out in dSPACE's microprocessor. Meanwhile, the FPGA is utilized to implement the switching sequences with consideration of the deadtime of devices. A dc-voltage supply (EA-PSI 81000-30) is used to regulate the dc-link voltage at 400 V.
The steady-state results for both MPCs are shown in Fig. 8. The output voltage of the converter, the current of the filter inductor, and the voltage across the load are shown in Fig. 8(a) and (b). As can be seen, the current ripple at adopted MPC is higher even though a bigger inductor is utilized. The voltages of dc-link capacitors are shown in Fig. 8(c) and (d). As can be seen, these voltages are regulated at the same level, which equals 200 V. Moreover, the peak-to-peak ripple voltage of dclink is 23 V, which is 5.7 percent of dc-link voltage (400 V).
The FFT result of the output voltages are shown in Fig. 9(a) and (b). For the MPC with the constant switching frequency, the major harmonic appears at 100 kHz, which is two times larger than the switching frequency. As mentioned before, the reason is that both two small vectors are utilized in each sector. Due to the difference in the applied time of small vectors, the odd multiple harmonics of switching frequency are presented in the output voltage with less amplitude than even ones. However, for the adopted MPC, the harmonics spread in the whole frequency range. Moreover, The FFT results of the voltage across the load for both methods are shown in Fig. 9(c) and (d). As can be seen, the filter reduces the amplitude of output voltage harmonics.
To verify the performance of the implemented MPC regarding the NP voltage balancing, an experiment is done for MPC with constant switching frequency. In this experiment, a load is added in parallel with the lower dc-link capacitor and a relay is utilized to connect and disconnect the load. The converter schematic with added load is shown in Fig. 10(a). Fig. 10(b) shows the dc-link capacitor voltages and the current of the added load. As it can be seen, despite connecting and disconnecting the load, still the voltage of the lower dc-link capacitor is regulated and fixed at the same level as an upper dc-link capacitor voltage.

V. CONCLUSION
In this paper, two different high bandwidth MPCs, including adapted MPC and MPC with the constant switching frequency, were developed for a high switching frequency singlephase 5-level hybrid ANPC inverter. Wherein SiC MOSFETs are employed to increase the switching frequency and to reduce the size of the filter. To control the NP voltage, the effect of each output voltage vector was studied. Moreover, a sub-cost function was applied to regulate the NP voltage. Both the methods were experimentally investigated by a laboratory setup. The simulation and experimental results show the ability of methods to control the voltage across the load and to balance the dc-link capacitor voltages during both steady-state and transitions. Comparing both methods showed the MPC with constant switching frequency has more advantages, such as better harmonic spectrum distribution and smaller filter size due to locating the main harmonics around twice the switching frequency.