Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs

This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. Delayed cross-coupling comparator is introduced in this work, which enhances the comparator regeneration while keeping the noise comparable. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove the proposed techniques. The post-layout simulated SAR ADC consumes only $6.71~\mu \text{W}$ and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fJ/convertion-step. Simulation results show the proposed speed-enhancement techniques improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.


I. INTRODUCTION
W ITH the scaling down of feature sizes in advanced CMOS technologies, the standard supply voltages are getting lower. In order to achieve high speed under low voltages, pipeline [1] and flash [2] analog-to-digital converters (ADC) are designed to achieve tens of MHz sampling rate under 0.5V. But their figure-of-merits (FoMs) are not competitive as compared to successive approximation register (SAR) based ADCs due to the simple architecture with no need for power hungry modules. Working at low power supply voltage, SAR ADCs have a wide range of applications in wireless sensor network, biomedical (EEG, ECG, EMG), environmental monitoring (temperature, humidity, pressure) and other fields. However, the working principle of SAR ADCs normally limits the sampling rate at hundreds of kS/s with supply voltages lower than 0.5V.
Conventional SAR ADC is composed of two boosted sampling switches, a differential binary-weighted capacitive DAC, a comparator and control logics. For an asynchronous SAR ADC, the total time for each conversion cycle is (1) where T samp is the sampling time of the ADC. Constant-V GS bootstrapping technique is commonly used for sampling switches, which keeps the on-resistance the same over the rail-to-rail input voltage range. The overdrive voltage of the sampling switch with constant-V GS bootstrapping technique is VDD-V TH . However, under nearthreshold supplies, the overdrive voltages become too low for MHz sampling. A cascade of clock boosting circuits [3] is employed to achieve higher switch-on voltage, but the falling edge of the boosted signal becomes slower, resulting in a slow turn-off of the sampling switch.
Comparator is the key analog block in a SAR ADC. The working speed of the comparator affects the comparison time (T comp [i]) in each SA cycle, and the noise performance of the comparator affects the resolution of the ADC directly. Speeding up a comparator with large input transistors leads to large kick-back noise to the capacitor array, which is more severe for small arrays under ultra-low voltages. Another approach is to enhance the positive feedback of the crosscoupling transistors. However, because the amplification time is shortened, the comparator noise is enlarged [4].
Two speed-enhancement techniques for near-threshold SAR ADCs are introduced in this work. The level-shifted boosting circuit is proposed to achieve sharp-edged sampling clock for megahertz rail-to-rail sampling. Delayed crosscoupling comparator is exploited to improve the comparison speed and, at the same time, keep the comparator noise low. In order to demonstrate the proposed techniques, a 0.35V 8b 12MS/s SAR ADC is designed, achieving 7.82b ENOB and 2.47 fJ/conv.-step FoM.
The rest of this paper is organized as follows. Section II introduces the level-shifted boosting circuit. Delayed crosscoupling comparator is presented in Section III. Section IV shows the architecture of the SAR ADC with the proposed speed-enhancement techniques. Post-layout simulation and comparasion with recent design are carried out in this section. Section V concludes this paper.

II. LEVEL-SHIFTED BOOSTING CIRCUIT
The performance of sampling circuits limits both the speed and linearity of the whole ADC. High switch-on voltage is generally preferred for linear sampling of a rail-to-rail input. Clock boosting technique is often employed to boost the switch-on voltage. Constant-V GS bootstrapping technique is widely used for sampling switches, since the overdrive voltage of the sampling switch remains the same with different input voltages, which doesn't introduce extra nonlinearity to the system. Since the overdrive voltage of the sampling switch with constant-V GS bootstrapping technique is VDD-V TH , the overdrive voltage is close to zero under a near-threshold supply voltage, which increases the switchon resistance by several orders of magnitude. Hence, the sampling speed with constant-V GS bootstrapping is limited under ultra-low voltages. A cascade of clock boosters [3] was introduced to boost the switch-on voltage several times, which ensures a sampling with 8-bit linearity.
Nevertheless, we found switch-off speed, or the falling time of the sampling clock, is the main limitation for sampling rate under low supply voltages. The relationship between the falling time of the sampling clock and SFDR & SNDR is analyzed in Fig. 1, where the sampling rate and switch-on voltage of the sampling clock are fixed at 12MS/s and 1V, respectively, and a 0.35V, 5.86MHz sine wave is used as the input signal. The simulation result in Fig. 1 indicates that SFDR and SNDR degrade when the

FIGURE 2. Schematics of (a) the conventional clock boosting circuit and (b) the proposed level-shifted boosting circuit; block diagrams of (c) three cascaded conventional clock boosting circuits and (d) two conventional clock boosting circuits cascaded with a level-shifted boosting circuit.
falling time of sampling clock increases. And a falling time less than 4ns is needed to achieve over 60-dB SFDR. Fig. 2(a) presents the schematic of a single stage of conventional clock boosting circuit [5]. When clk_in gets high, Vy is set to clk_in+VDD and clk_out is connected to Vy through M1. When clk_in is low, Vx is set high to switch on M2, which pulls clk_out to low. Since Vx is limited by VDD, the voltage of clk_out in Fig. 2(a) falls slowly under near-threshold supply. Fig. 2(b) shows the schematic of the proposed level-shifted boosting circuit. A level shifter is utilized to replace the inverter in the dotted box in Fig. 2(a). Signal clk_in in Fig. 2(b) is used to pre-charge Vz to clk_in+VDD. When clk_samp is high, Vp goes low and clk_out is connected to Vz through M7. When clk_samp is  Since the maximum output voltage of a single stage of Fig. 2(a) and Fig. 2(b) is clk_in+VDD, the switch-on resistance of the sampling switch is limited under nearthreshold supply. Therefore, cascade of boosting circuits is needed. Fig. 2(c) shows the block diagram of a popular solution with three cascaded conventional clock boosting stages. When clk_samp gets high, the output of the conventional clock boosting circuit goes high stage by stage. After three-boost-stage delay, signal samp1 rises to a boosted voltage. Similarly, when clk_samp gets low, the output of the conventional clock boosting circuit goes low stage by stage. Fig. 2(d) presents the proposed circuit with two conventional clock boosting stages cascaded with a level-shifted boosting stage. Fig. 3 shows the timing diagram together with simulation results. Signal pre_samp is employed to pre-charge the capacitors to high voltage in the boosting circuits. When pre_samp gets high, the output of the two conventional clock boosting stages goes high stage by stage. Then clk_samp is set high to pull the output, samp2, to the boosted voltage only after two-stage gate transmission delay. When clk_samp goes low, Vp is pushed to a voltage higher than supply. Large overdrive voltage of M8 pulls the output voltage to zero in a very short time. Then signal pre_samp goes low after samp2 gets to zero. From Fig. 3, the switch-on voltages of samp1 and samp2 are over 1 V, which ensures a small switch-on resistance. The falling time of samp1 is more than 10 ns. The falling time of samp2 from 0.9 maximum voltage to 0.1 maximum voltage is 1.8 ns, which is sufficient for a 0.35V 8b 12MS/s ADC according to Fig. 1. Fig. 4 shows the simulated spectrum of a 0.35V sampling circuit with the proposed clock boosting technique shown in Fig. 2(d). The performance with the conventional clock boosting circuit of Fig. 2(c) is also given as reference. The simulated sampling circuit is the same with the one in Fig. 1. With a 5.86MHz Nyquist input sampled at 12MS/s, 58.71dB SNDR and 64.24dB SFDR are achieved with the proposed clock boosting technique. As shown in Fig. 4, 10.76dB improvement on SFDR is obtained.

III. DELAYED CROSS-COUPLING COMPARATOR
Speed and noise are the key considerations for ultra-low voltage comparators. The comparison consumes the time of each SA cycle, and the input referred noise of the comparator affects the resolution of the ADC directly. In addition, there are tradeoffs between the speed and noise of the comparators. Fig. 5(a) shows the schematic of a typical P-latch comparator. M1, M6 and M7 are used as switches to enable and reset the comparator. M2 and M3 are input differential transistors. M4 and M5 are cross-coupled for positive feedback. The process of comparison can be viewed as four phases [4], [6], i.e., reset, amplification, regeneration and decision, as shown in Fig. 6. When clk is low, M1 is turned off, M6 and M7 are turned on. The comparator is in reset phase, Vop and Von are reset to high. Sampling phase starts after the rising edge of clk, where the voltage difference of Vop and Von is sampled and amplified to trigger the following regeneration phase. The speed of the comparison can be improved with larger pull-down current by increasing the size of the M1, and increasing the size of M2 & M3 in the same proportion to achieve greater transconductance. However, increasing the size of the input transistors results in higher kick-back noise to the capacitor array, which degrades the linearity.
As a direct approach, an additional cross-coupled pair, M8 and M9, can be introduced to enhance the positive feedback, as shown in Fig. 5(b). Right after reset, the NMOS cross coupled pair is in on-state and starts regeneration, which greatly reduced the duration of amplification phase. To show the influence of the changing part, the transistors marked with the same name in Fig. 5 are also sized the same for the simulation in Fig. 7. The result shows NP-latch comparator is much faster than the P-latch one. However, the extra crosscoupling circuit decreases the sampling time as well. Since the input signal is sampled and amplified in amplification phase, the input referred noise of the comparator is inversely proportional to the time of amplification phase [4]. Hence, the noise performance of NP-latch comparator is degraded. The simulation result proves the root-mean-square (RMS)   noise of NP-latch comparator is 1490 µV, whereas the noise of P-latch comparator is 350 µV.
The delayed cross-coupling comparator is proposed to decrease the comparison time without degrading the noise performance, as depicted in Fig. 5(c). Since M8 & M9 in Fig. 5(b) decrease the time for amplification phase and increase the comparator noise, the additional cross-coupling pair is delayed to work until the amplification phase ends. The timing of the comparator is given together with the simulation results in Fig. 7. The comparator is enabled when clk gets high, while clk2 is kept low during the amplification phase, disconnecting the extra cross-coupling pair from the comparator. Therefore, the equivalent circuit of Fig. 5(c) in amplification phase is the same with Fig. 5(a). clk2 gets high after amplification phase, then M8 & M9 are added into the circuit to enhance the regeneration. So the delayed cross-coupling comparator improves the speed of comparator without degrading the noise performance. In order not to degrade the noise performance, the rising edge of clk2 should be later than the amplification phase. While if clk2 is too late, the comparison speed would be affected. Hence, clk2 is generated by a voltage-controlled delay circuit from clk. The control signal can be adjusted manually in the simulation. When this value is set larger, the delay time is shorter, and the comparator is faster but noise performance gets worse. When this value is set small, the rising edge of clk2 arrives later, and the comparator's noise is reduced but the speed is limited. After a lot of simulations and comparisons, when the control voltage is set to 185mV, the optimal delay time on clk2 is 1.86ns, and the speed and noise performance of delayed cross-coupling comparator are optimized. From Fig. 7, the RMS noise of the proposed comparator is 400 µV, which is similar to the noise performance of the traditional P-latch comparator. It shows the proposed comparator can enhance the working speed while remaining the noise performance.
In order to show the improvement of the proposed delayed cross-coupling comparator, the sizes of M8 & M9 in the NP-latch comparator are tuned to achieve the same delay of the proposed comparator. The simulated noise and power are listed in Table 1. The average current is achieved under 125 MHz speed. Simulation results show the proposed comparator achieves similar power with NP-latch comparator, but the noise of the proposed one is much lower.

IV. ADC ARCHITECTURE AND SIMULATION
Sections II and III introduce two speed-enhancement techniques for near-threshold SAR ADCs. A 0.35V SAR ADC with those techniques has been designed with post-layout simulations. Fig. 8 presents the system architecture of the   proposed SAR ADC. It is composed of a split capacitor array [7], two sampling switches with the proposed level-shifted clock boosting circuits, the proposed delayed cross-coupling comparator and control logics. The split capacitor array is employed to avoid the common-mode reference voltage Vcm (0.5*VDD), because the low overdrive voltage for switching on Vcm affects the DAC settling time under ultra-low supply voltages.
The 0.35V ADC has been post-layout simulated in a 65-nm CMOS technology. Fig. 9 shows the layout of the  proposed ADC. The unit capacitance of the CDAC is 1 fF. Fig. 10 shows the 4096-points fast Fourier transform (FFT) spectrum result with a 5.86 MHz input sampled at 12 MS/s. The SNDR and SFDR are 48.8 dB (7.82 ENOB) and 67.39 dB, respectively. The simulated results of SFDR and SNDR versus input frequency are also presented in Fig. 10. The whole ADC consumes only 6.71 µW with DAC of 0.7 µW, comparator of 0.78 µW, clock boosting of 0.71 µW, and logic of 4.52 µW. With the Walden FoM definition, a FoM of 2.47 fJ/conv.-step has been achieved. Table 2 summarizes the simulated performance and compares the proposed work with previously reported sub-0.5V SAR ADCs with 8-11 bits of resolution. Fig. 11 plots the speed performance of reported sub-0.5V ADCs, which indicates the proposed speed-enhancement techniques have significantly increased the potential sampling rate of near-threshold SAR ADCs. He has been an Associate Professor with the Institute of Integrated Circuits and Systems, and School of Electronic Science and Engineering, University of Electronic Science and Technology of China, since 2017. His current research interests include analog-to-digital converters, biopotential amplifiers and acquisition systems, low-power analog, and mixed-signal circuits.
Dr. Zhou serves as the Reviewer for several international journals and conferences.