A 4H-SiC CMOS SPICE Level 3 Model for Circuit Simulations

In this letter, a compact DC SPICE model for 4H-SiC lateral metal oxide semiconductor field effect transistors is shown both for PMOSFET and NMOSFET. It is validated through experimental comparisons by varying channel sizes, temperature in the range between <inline-formula> <tex-math notation="LaTeX">${298}{K}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${573}{K}$ </tex-math></inline-formula>, and body voltage conditions. A new model of the threshold voltage is introduced in order to take into account the effects of the high interface defects density. Finally, an inverter logic gate is simulated at different temperatures and compared with experimental data and with BSIM4SiC simulation outcomes, where a maximum logic threshold voltage error of <inline-formula> <tex-math notation="LaTeX">${0}.{85}\%$ </tex-math></inline-formula> to the experimental data is shown compared to <inline-formula> <tex-math notation="LaTeX">${6}.{78}\%$ </tex-math></inline-formula> of BSIM4SiC.


I. INTRODUCTION
4H -SILICON Carbide, 4H-SiC, semiconductor devices are suitable for high temperature applications thanks to its intrinsic physical properties [1] and the operation of integrated circuits above 473K has been frequently shown.For example, 4H-SiC Bipolar Junction Transistor ICs operate up to 773K [2], but they need a multi-epitaxial layer stack [3], which limits the complexity of the circuits and makes the fabrication process expensive.Recently, a 4H-SiC Complementary Metal Oxide Semiconductor, CMOS, technology has been made available [4] and digital and analog ICs have been demonstrated up to 873K [5].Moreover, the possibility to integrate circuits with other devices, like UV sensors [6], opens to new application fields.
To design ICs, the device models have to accurately predict the electrical behaviors, but, up to now, only a few of 4H-SiC lateral MOSFETs models are available both due to the recent technology development and due to the high density of Si O 2 /4H − SiC interface defects.Indeed, the threshold voltage, V T H , and the channel mobility, µ C H , have a different dependency on the electrical parameters as well as on the temperature compared to the Silicon ones.In [7] a modified version of BSIM4 model, BSIM4SiC, has been proposed, instead [8] shows a surface-potential based model, named PSP, which takes into account the interface state defects.In this scenario, SPICE Level 3-based model can be a good trade-off between complexity and accuracy, but only a few of them are available in literature.For example, [9] reports the SPICE parameters only at room temperature and extracts V T H -values by using the linear extrapolation method, which is unreliable when the interface defects density is high [10]; instead, [11] shows a DC SPICE Level 3 model, but it is only for NMOSFETs for a fixed geometry of the channel and without temperature effects.
In this letter we propose a SPICE Level 3 Compact DC model for 4H-SiC lateral NMOSFETs and PMOSFETs operating under different bias conditions and temperatures.The geometry dependencies are taken into account as well as body effects through a semi-empirical model of V T H and experimental comparisons are shown with single devices and with an integrated CMOS logic circuit.The model is suited for analog and digital circuits and it is focused on strong inversion conditions and long channel devices.

II. PROPOSED SPICE MODEL
In Fig. 1 our DC SPICE model for a 4H-SiC lateral MOS-FETs has a Level 3 MOSFET, M 1 , a voltage controlled voltage source, E 1 , a current controlled current source, F 1 , and two switches.The total current, I DS , is as follows: where I DS,1 is imposed by M 1 [12], whose parameters are in Tab.I, instead I DS,2 by F 1 and has the following expression: In (2) ζ is a fitting parameter, which allows to introduce the reduction of I DS due to the channel mobility decrease when positive V S B are applied in the case of NMOSFETs [13].For V G S > V * T H , the gate-source voltage, V * G S , of M1 is imposed by E 1 , (SW 1 ON and SW 2 OFF) and is equal to: instead, V * G S is null when V G S ≤ V * T H (SW 1 OFF and SW 2 ON).Eq.( 3) improves the basic Level 3 SPICE model, because it describes the effects of the defects at the Si O 2 /4H − SiC interface on the overall electrical behaviours.Indeed, the V T H -dependency on the bias gate voltage, due to the trap charge density at the interface, either is a complex function, like Gauss hypergeometric function [14], or needs iterative approaches [15], making unreliable any V T H -extraction techniques as well as unfeasible any SPICE models.Instead, (3) considerably simplifies the complex dependency of V T H on the bias gate voltage and permits its easy implementation in SPICE.In Tab.I all the parameters of the model are reported and also valid for PMOSFET, where V G S , V DS , V S B and I DS are changed with V SG , V S D , V B S and I S D , respectively.It is worth to note that, although the model is the same for both transistors, the different effects of interface traps on devices characteristics are described through the different coefficients of Tab.I, where, for example, a linear dependency on V SG is found for PMOSFET whereas a quadratic one for NMOSFET.

III. RESULTS
Measured and modeled output characteristics of the MOS-FETs with different channel lengths, L ∈ [6; 10]µm, and widths, W ∈ [10, 100]µm, at room temperature and V B S = 0V are shown in Fig. 2.a)-c) and Fig. 2.g)-i), where the maximum errors of the model from experiments are of 9.7% for NMOSFETs and of 8.9% for PMOSFETs.The only discrepancy between experimental and model results is in the transition from linear to saturation regions, where there is an overestimation of the current of +9.7% for the 20/6 NMOSFET at V G S = 20V .This soft-transition is still unclear, but it could be ascribed to the reduction of the channel mobility due to the high longitudinal electric field, which induces the saturation of the carrier velocity, and, simultaneously, to the surface roughness scattering when high transversal electric field is applied [16].
In Fig. 2.d)-f),.j)-l),temperature and body effects on NMOS-FETs and PMOSFETs characteristics are reported as well as the trans-characteristics of Fig. 3.a)-b) also highlights the temperature effects.Indeed, the model describes the increase of the current with the temperature both in linear region (see Fig. 3.a)-b) at V DS = V S D = 1V ) and in saturation region (see Fig. 3.a)-b) at V DS = V S D = 20V ) and also the reduction with the increase of the body bias.The temperature dependency can be ascribed to the combined effects of V T H reduction and channel mobility increase due to the decrease of the occupied interface trap density and the prevalence of Coulomb scattering  [16], [17].Such behaviour is completely opposite to Silicon one and makes inadequate the classical SPICE parameters temperature dependence [12] for 4H-SiC MOS-FETs.For this reason, our model introduces new temperature dependencies, as reported in Tab.I: i) the channel mobility depends on (T /T 0 ) µ 03 , where µ 03 has positive values for both MOSFETs; ii) the reduction of V T H with the temperature has been described through a temperature dependence of α 0 , α 1 , and α 2 parameters of (3); iii) v max , ζ and θ also depends on the temperature.
In Fig. 2.d)-f) the body effect is evident for NMOSFET, also at different temperatures, where I DS reduces with positive V S B as expected [1], instead PMOSFET shows a weak dependence on V B S , as reported in Fig. 2.j)-l).Comparing our model with experimental curves in T ∈ [298; 573]K and V S B = [0; 12]V , I DS of NMOSFET shows an error of 6.6% respect to the 10% of PMOSFET at T = 573K and V B S = 12V (see Fig. 2.l), which is acceptable considering the low complexity of the model and the wide temperature range for the comparison.Moreover, it is worth to note that 4H-SiC PMOSFETs are Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.generally biased at V B S = 0V because their series connections are avoided due to the low µ C H, p and the high V T H, p values.In literature there are studies about the effects of the body bias on the PMOSFETs parameters, but further analysis are required because they are unable to fully describe the phenomenon: for example [16] shows that the surface roughness scattering mechanism reduces the µ C H, p by −50% under body bias conditions, which is too high in comparison to the −1.02% of I S D observed in our measurements, and, therefore, an enhancement phenomena is expected to counterbalance µ C H, p reduction.
To further validate our model, in Fig. 4 we compare the experimental results of [18] for a 4H-SiC CMOS inverter gate (W P /L P = 80/6 and W N /L N = 20/6) characterized along the temperature range T ∈ [298; 473]K , together with numerical simulations performed through a BSIM4SiC model [19].It is worth to note that we decided to choose experimental data from literature in order to generalize and to extend the applicability of the model.Beyond the good description of the characteristics in the whole voltage range, our model correctly predicts them for each temperature value.In particular, it is interesting to note that our model describes the temperature behaviour of the threshold logic voltage, V M , starting from 9.33 V at room temperature, increasing to 9.67V at T = 373K and, then, reducing to 9.58V at T = 473K , (see the inset b) of Fig. 4).Contrarily, BSIM4SiC model shows an incorrect monotonic temperature behaviour of V M as well as a minimum error of 2.79% at T = 373K , which is much higher than the maximum error of our model, equal to 0.85% at T = 298.15K .Furthermore, the high, N M H , and low, N M L , noise margin errors of the inset c) of Fig. 4 are, respectively, 3.26% and 1.79% at T = 298K for our model and, respectively, 13.62% and 5.23% at T = 473K for BSIM4SiC ones.

IV. CONCLUSION
A compact DC 4H-SiC MOSFET SPICE Level 3 model is proposed for strong inversion conditions, taking into account temperature, geometrical and body bias dependencies.Comparisons with experimental single devices and circuit, combined with simulation outcomes when higher order models are used, highlight a good trade-off between complexity and accuracy of the model.Indeed, due to the high density of traps at the interface, our model describes the unusual V T H -behavior with a quadratic equation easily implementable in a SPICE simulator.Moreover, although simulations of digital circuits are shown, the good description of the electrical characteristics in the saturation region and the absence of discontinuity of the curves permit a small-signal AC analysis at a low frequency range used in analogue circuit simulations.

Fig. 4
Fig. 4. a) Comparison between SPICE model and [18] of 4H-SiC CMOS NOT trans-characteristic.In the insets, comparisons of b) V M and of c) NM L,H between SPICE, BSIM4SiC and measurements.