On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

This paper proposes an original approach to separately characterize self-heating and substrate effects in Fully-Depleted Silicon-on-Insulator (FD-SOI) devices. As both dynamic self-heating and drain to source coupling through the back-gate and substrate of an FD-SOI MOSFET induce a frequency transition in the Y-parameters in a common frequency range, it is crucial to properly separate them for further modeling. The proposed novel method is based on the extraction of the back-gate and substrate networks from the S-parameters measured at the zero-temperature coefficient bias. It enables the accurate and unambiguous extraction of thermal impedance for different biases, thus providing the extraction of the device thermal resistance and capacitance for different power levels from S-parameters measurements.


I. INTRODUCTION
T HE downscaling of CMOS technology has been crucial for improving device performance and reducing manufacturing cost. However, aggressive scaling results in higher current and power densities, thereby increasing the self-heating (SH) effect and the lattice temperature (T c ). Fully-Depleted Silicon-on-Insulator (FD-SOI) transistors offer outstanding electrostatic control, very low mismatch, excellent analog and RF figures of merit [1]- [4]. However, due to the presence of the buried oxide (BOX), SH of more significance is present in FD-SOI MOSFETs than in their bulk counterparts [5]. Dynamic self-heating is known to induce a transition in the Y-parameters over frequency that is used in turn to extract the thermal parameters [5]- [13]. Furthermore, the drain to source coupling through the back-gate (B-G) node (or Si substrate under the BOX) also induces a transition in the Y-parameters in a similar frequency range [9], [14]. Although this transition was originally very pronounced in FD-SOI devices with thin BOX [9] contrarily to previous device generations [14], the introduction of a highly-doped region below the BOX strongly reduces the transition [5]. The transition associated to the coupling via substrate is thus usually neglected/ignored in these devices, which may however lead to misinterpretation and erroneous modeling of SH [5], [10]. To the best of the authors' knowledge, no method has been proposed to separately characterize each contribution, i.e. SH and B-G effect (also called substrate effect, SE), into Y-parameter frequency response. In this paper, we will (i) demonstrate that the SE partially overlaps SH forming a common, indistinguishable distributed transition from 100 kHz to 10 GHz, (ii) show that the dynamic SH effect vanishes at the zero-temperature coefficient (ZTC) bias point, (iii) use this bias point to extract the SH-free transistor electrical model including the B-G and substrate nodes, (iv) extract the frequency-dependent thermal impedance Z th (f) for different bias conditions, and (v) compare it to the conventional extraction procedure that neglects the transitions associated to the B-G node.

II. SELF-HEATING AND BACK-GATE NODE EXTRACTION A. Advantage of ZTC Bias for Unambiguous Extraction
An FD-SOI super-low threshold voltage nMOSFET from 22FDX® [2] featuring a gate length of 20 nm, finger width of 0.5 μm, 20 fingers and a multiplicity of 6 for a total width of 60 μm is studied. Its S-parameters are measured on-wafer from 100 kHz to 10 GHz using a vector network analyzer from Keysight, coupled with a probe station hosting a thermal chuck for additional dc I-V measurements at 300, 320, 335, 350, 370 and 390 K. The back-gate voltage (V bg ) is set to 0 V. The RF MOSFETs are probed using a Ground-Signal-Ground (GSG) configuration. A Short-Open-Load-Thru (SOLT) calibration is performed and dedicated open and short structures are measured to de-embed the transistor measurements down to the first metal layer.
The conventional method to extract SH parameters from S-parameter measurements [6]- [8] relies on the fact that the lattice temperature is able to follow a "slowly" (w.r.t. its thermal time constant) varying ac signal, but ceases to follow the ac signal if it is too "fast", leading to a step between the low and high frequency values of Y dd (Y 22 ) and Y dg (Y 21 ). This so-called dynamic SH effect has been rigorously put into equations for a general two-port device in [11]. In our case, the equations simplify into: with Y ddT and Y dgT being the admittances for the isothermal case, i.e. when the lattice temperature does not vary with the ac signal. Y ddT and Y dgT are by definition not affected by dynamic self-heating. T A is the ambient temperature. The inset in Fig. 1(a) shows the I d -V g curves for different ambient temperatures. Due to the threshold voltage reduction with increasing temperatures, I d increases with T A at low V g . Whereas, I d decreases with T A for large V g biases because of stronger phonon scattering decreasing carrier mobility. These two mechanisms compensate each other at the ZTC bias point [15], such that the I d associated to this bias does not change with temperature. For the studied device, the ZTC bias is V g,ZTC = 0.62 V for V d = 0.8 V and V bg = 0 V. Fig. 1(a) shows the variation of g d (f) computed as Re(Y dd ). The curve for V g = 0.54 V shows a monotonic decrease in g d (f) starting from ∼1 MHz related to SH, followed by an increase for frequencies above 100 MHz that cannot be described by dynamic self-heating (1a) and which is attributed to the SE. The SE is also present at the other biases. For V g > V g,ZTC , both substrate and self-heating effects contribute to a step increase in g d (f), such that the thermal resistance R th (and thus lattice temperature) would be overestimated if the SE were to be ignored. At the ZTC bias, the dynamic SH does not affect the ac curves and the observed transition ( Fig. 1, green data) is solely due to the SE. Similar trends are observed in the output capacitance C dd (computed as Im(Y dd )/ω) in Fig. 1(b). The ZTC bias point therefore enables the extraction of the small-signal parameters associated to the B-G and substrate nodes without any dependency on the SH effects. As the ZTC bias point is not specific to this technology [16]- [20] and has been experimentally verified down to cryogenic temperatures [21], [22], the proposed methodology can be widely applied.
By taking the real and imaginary parts of (1a), we can derive the equations describing the dynamic SH effect on g d (f) and C dd (f): From (2) and (3), it is plain to see that the low frequency values of g d and C dd (and the transition sign) depend on the sign of dI d /dT A , and is thereby governed by the two opposing mechanisms of mobility and threshold voltage reduction with increasing temperature [6], [7], [23]. The frequency transition in itself is due to a delay in the heat transport mechanism from device to heat sink, yielding a lattice temperature that is not able to follow instantaneous variations of an ac power at frequencies above the isothermal frequency.

B. Extraction of Substrate and Back-Gate Nodes Model
The substrate and B-G lumped circuit parameters (in green in Fig. 2(a)) are extracted from optimization for a best fit of the measured Y-parameters to the small-signal equivalent circuit in Fig. 2(a) in the frequency range from 10 MHz to 10 GHz, similar to [24]- [26]. The series resistances R g , R d and R s are extracted beforehand with Bracale's method [27]. The resulting fitting of Y dd (f) and measurements at the ZTC bias point is shown in Figs. 1(a) and 1(b) in solid (green) lines.

C. Thermal Impedance Extraction
Knowing the B-G model, the complex thermal impedance Z th (f) is extracted at other bias conditions than at ZTC. The values of some bias-dependent parameters (C gd , C gs , g m,i , g d,i , in blue in Fig. 2(a)) are updated accordingly. However, the parameters associated to the B-G and substrate nodes (in green in Fig. 2(a)) are assumed to remain constant with V g in the (strong) inversion regime. It is nevertheless important to emphasize that they are not assumed independent of V d and V bg , since for any applied V d and V bg there will exist a V g yielding ZTC conditions. The frequency dependent (due to SE) Y ddT (f) term is then computed using the updated small-signal equivalent circuit parameters for each bias.
Next, an n th -order thermal network representing Z th is used to fit the Y dd (f) data according to (1a). Both the imaginary and real parts of Y dd are used for fitting, although only fitting Im(Y dd ) gives very close results. The term dI d /dT A is experimentally obtained from dc I-V measurements at several T A (see inset of Fig. 1(a)). In our case, selecting n = 4 (cf. Fig. 2(b)) appeared to be sufficient to correctly model the distributed transition. The resulting thermal and electrical model is shown for different bias points and compared with the measured Y-parameters in Fig. 3.

III. RESULTS
We observe that a very good fitting is obtained across a very wide frequency range from 100 kHz up to approximately 10 GHz for the different bias points. The sign of the step (either positive or negative) is correctly reproduced in accordance with (2) and (3). To the best of our knowledge, it is  the first time that g d (f) and C dd (f) curves for V g < V g,ZTC with a negative step in g d (f) are shown and that the total R th is extracted from them. Although the physical origin of this negative step is known and explained in Section II.A, such curves have not been presented previously, since high biases -where SH has higher impact, and thus a positive step in g d (f)-are commonly used in self-heating characterization. With technology scaling down and power reduction, the voltage range below ZTC becomes of interest. Even if SH is lower in that range, it nevertheless has to be taken into account (in particular its frequency response). Fig. 4(a) shows the real part of the extracted Z th for different biases. All curves superimpose meaning that the frequency-dependent Z th (f) is power-independent (or almost), as expected at room temperature, thus confirming the consistency of the method. Though a roughly constant R th with power is extracted in this work, it is not necessarily the case for other devices or in different conditions, such as at cryogenic temperatures [28]. We also observe that Re(Z th ) becomes negligible only above 2.4 GHz (<1% its maximum value), therefore yielding an isothermal frequency above 2.4 GHz. This confirms our previous statement that SH and the SE cannot be easily distinguished in such devices as they appear in the same frequency range.
Indeed, Fig. 4(b) shows that extracting Z th without taking into account the B-G and substrate nodes, i.e. by using constant g dT and C ddT versus frequency as in [12], [13], can lead to a strong misestimation of Z th . Ignoring the existance of the B-G associated transition leads to an overestimation (underestimation) of the total R th (R th = i R th,i ) when V g > V g,ZTC (V g < V g,ZTC ), because its effect adds up (counteracts) with the SH effect, respectively, as shown in Fig. 5, which plots the extracted total R th for different V g , with (blue data) and without (pink data) accounting for SE. The R th is not extracted close to the ZTC bias point, because of the singularity (divide by zero) provided by the dI d /dT A term tending to 0 as V g tends to V g,ZTC , thus introducing a larger error.
While for large I d (V g ) bias conditions (as in [5], [10]), the SH effect dominates the transition and neglecting the B-G/substrate nodes leads to a minor (5%) error in the R th evaluation, accounting for SE (and its independent modeling) is crucial for low-power applications. An extensive comparison of the electrical characteristics of the model extracted with and without taking into account the corrected value of R th merits additional investigations, but is out of scope of this Letter. Indeed, neglecting the SE modeling can lead to an error as large as 60% in R th at lower I d (V g ) (red curves in Fig. 4b).
In contrast, the novel method achieves an excellent accuracy at intermediate power and still performs well at low power, with resulting errors below 5% and 20%, respectively. The small remaining error at low V g can be explained by a slightly bias-dependent Y ddT not accounted for. The corresponding temperature rise (T = R th .P) versus power (P) is displayed in the inset of Fig. 5. The extracted R th is roughly constant across the whole V g range and gives a median value of 202 Kμm/mW.

IV. CONCLUSION
In this paper, we propose a method to extract the thermal impedance from device measurements unaffected by the substrate network in the frequency range of interest for dynamic self-heating. The ZTC bias condition can be used to extract any dynamic self-heating-free small-signal model. It can therefore be directly applied to measurements without requiring a compact model or simulation to capture the transition not related to SH. The developed procedure enables the extraction of R th (P,T A ) from S-parameters at different bias conditions and could be of particular interest for measurements at cryogenic temperatures for which R th is not constant versus power.