Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays

This article presents a chip-to-chip (C2C) interface for constructing reconfigurable phased arrays to be used in fifth-generation (5G)/sixth-generation (6G) wireless systems. The C2C interface further facilitates building phased array panels by allowing the use of grid-based PCB routing, thus providing flexibility in the system design. An eight-element RFIC capable of handling two independent data-streams is fabricated using 45-nm CMOS technology. The RFIC incorporates four C2C interfaces operating at 27 GHz, two C2C interfaces operating at 9 GHz, and a complex baseband (BB) with single-sided bandwidth in excess of 400 MHz. The architecture is tested by flip-chip bonding two fabricated RFICs on an eight-layer Megtron 7 PCB. In this article, only the receiver path of the RFIC and the phased array is described. Performance of both the single RFIC and the combination using the 27-GHz C2C interface is demonstrated using conductive and over-the-air (OTA) measurements. OTA measurements are conducted using 5GNR FR2 OFDM waveforms with a signal bandwidth of up to 800 MHz. The measured RF to BB conversion gain for a single element is larger than 23 dB and the minimum measured noise figure (NF) is 6.2 dB. The nominal dc power consumed by the receiver per element per stream is 116.5 mW. The RFIC occupies a normalized area per element per data stream of 2.7 mm2. The RFIC is capable of supporting dual-polarized antennas or in a large-scale panel utilizing the same antenna elements to two independently weighted data streams as part of the hybrid beamforming architecture.

Abstract-This article presents a chip-to-chip (C2C) interface for constructing reconfigurable phased arrays to be used in fifth-generation (5G)/sixth-generation (6G) wireless systems. The C2C interface further facilitates building phased array panels by allowing the use of grid-based PCB routing, thus providing flexibility in the system design. An eight-element RFIC capable of handling two independent data-streams is fabricated using 45-nm CMOS technology. The RFIC incorporates four C2C interfaces operating at 27 GHz, two C2C interfaces operating at 9 GHz, and a complex baseband (BB) with single-sided bandwidth in excess of 400 MHz. The architecture is tested by flip-chip bonding two fabricated RFICs on an eight-layer Megtron 7 PCB. In this article, only the receiver path of the RFIC and the phased array is described. Performance of both the single RFIC and the combination using the 27-GHz C2C interface is demonstrated using conductive and over-the-air (OTA) measurements. OTA measurements are conducted using 5GNR FR2 OFDM waveforms with a signal bandwidth of up to 800 MHz. The measured RF to BB conversion gain for a single element is larger than 23 dB and the minimum measured noise figure (NF) is 6.2 dB. The nominal dc power consumed by the receiver per element per stream is 116.5 mW. The RFIC occupies a normalized area per element per data stream of 2.7 mm 2 . The RFIC is capable of supporting dual-polarized antennas or in a large-scale panel utilizing the same antenna elements to two independently weighted data streams as part of the hybrid beamforming architecture.

I. INTRODUCTION
F IFTH generation (5G) and the upcoming sixth generation (6G) networks promise to provide higher data rates and reliable, low latency, and power efficient wireless connectivity [1], [2]. In order to achieve these goals, scalable, reconfigurable, power efficient, and large phased arrays with multiple antenna elements are proposed [3]. Link analysis for both 5G [4] and 6G [5] indicates a need for high antenna gain i.e., a large number of phased array elements even for single links. Moreover, hybrid beamforming has emerged as a popular phased array transceiver architecture in terms of beamforming flexibility and power consumption for arrays supporting a multiplicity of orthogonal data streams in base stations. In other words, the next-generation phased array system should be scalable, support multiple beams, and be reconfigurable at runtime. This not only helps in improving the power efficiency, but it can also help in intelligently creating beam patterns with reduced sidelobe levels, thus reducing interference to other users [6]. Provided the motivation, these requirements have been addressed in the literature by creating phased arrays in the following three ways.
1) Symmetrical tree-like routing and combining at RF, IF, or baseband (BB) using passive or active combiners shown in Fig. 1(a) and used for example, in [15], [16], [18], [19], [20], and [21]. 2) Point-to-point routing with matched lines shown in Fig. 1(b) and used, for example, in [17] and [22]. The benefit of symmetrical tree-like routing is that it is easier to tile given the symmetrical nature, which further reduces the calibration complexity. At the same time, it incurs larger path loss compared to point-to-point routing.
Hybrid beamforming has been proposed as a solution to process many independent beams in phased arrays [32], [33], [34], [35], [36]. Depending on the context, very different approaches and architectures have been proposed from sub-array based to fully connected analog multiple-inputmultiple-output (MIMO) solutions. Large-scale solutions are typically based on multiple parallel and independent RF subarrays and beam-based processing is done in the digital domain with the limited field of view of each sub-array. MIMO-like fully connected, i.e., cross-coupled arrays, have been limited to a relatively small number of symmetrically combined signal paths in the RF domain or to slightly larger analog combining matrices within one chip. RF or analog-based hybrid beamforming has recently been proposed in chip-scale combining architectures in [24], [25], [26], [27], [28], [29], [30], and [31]. A common concern regarding these designs is that they are not easy to scale up and they require a sophisticated LO distribution network.
Based on the above discussion, the main conclusion is that in the current phased array designs scaling is addressed by employing either tree-like combining/distribution network or point-to-point routing. These methods, although assists in reducing the calibration complexity, however, make changing the number of elements for one stream difficult. Furthermore, for fully connected hybrid implementations, even though the number of elements participating in one stream can be changed easily, the existing implementations do not allow for scaling the architecture to the larger number of antennas. The main motivation of this research is to develop an antenna array architecture that not only allows dynamic reconfiguration of a large antenna array but also provides scalability, with the goal to provide a way to implement complex patterns supporting multiple beams flexibly, as proposed, for example, in [6].
Keeping these goals in mind, a phased array RFIC architecture is proposed and an RFIC is designed and fabricated utilizing multiple chip-to-chip (C2C) interfaces which are combined via grid-based routing. Symmetrically combining IF signals via C2C interfaces have been previously published in [21] and [23]. The proposed RFIC can be tiled in both vertical and horizontal directions on a PCB with antennas on the other side, thus, creating a panel with multiple rows and columns. The proposed architecture not only allows us to easily scale the panel but also to dynamically re-configure it by selecting antennas from any row or column for combining. The architecture also simplifies scaling in the case of hybrid beamforming, allowing C2C connections through specific interfaces at several frequencies and directions. Different routing strategies are illustrated and compared in Fig. 1 and Table I.
The proposed RFIC is designed and fabricated using GlobalFoundaries 45 -nm PDSOI technology. It contains four mmWave C2C interfaces, two IF C2C interfaces, and utilizes grid-based routing, thus simplifying the PCB design and allowing the selection of any antenna from any RFIC to form a desired beam shape as in [6]. The LO is routed in a daisy-chained manner, further reducing the PCB complexity. The daisy-chaining of LO is previously utilized in [18]. The fabricated RFIC supports signal combining at three different frequencies: RF, IF, and BB. In addition, it allows two different data streams to be handled simultaneously. Utilizing two of these RFICs, a phased array receiver is created and tested. In Section II, the system architecture is discussed in detail. Architecture and circuit design details of the implemented RFIC supporting this system architecture are described in Section III. Characterization results of the single RFIC and a two RFIC receiver phased array are presented in Section IV and the conclusions are drawn in Section V.

A. System Architecture
The block diagram of the proposed phased array system is shown in Fig. 2. The system consists of a total of M × N RFICs arranged in a 2-D grid of M rows and N columns. Each RFIC is connected to multiple antennas via its frontend (FE) antenna ports, and to its immediate vertical and horizontal neighbors via the C2C interfaces, shown in red and blue in Fig. 2, respectively. Here, the antenna can be a single patch antenna or a small sub-array driven by one FE. The horizontal C2C interface operates at mmWave frequencies and vertical at IF. Hence, this architecture does not employ a tree-like passive combining with on-PCB power combiners [15], [16], but proposes a more flexible row and columnbased combining method. The vertical and horizontal C2C interfaces could be designed to operate on the same frequency (mmWave or IF). However, isolation is improved on the PCB when vertical and horizontal C2C interfaces are operating at different frequencies. All C2C interfaces support simultaneous input and output signal flow.
Based on the number of logical streams that the system is configured to provide, multiple external BBs can be connected at different points in the M × N grid. Using the C2C interfaces, BB connections can be logically routed on the perimeter of the array. Fig. 2 shows a system with two external BB via RFICs U 1,1 and U M,N , thus, being able to support two independent data streams as an example. Furthermore, it also depicts one viable way to distribute the connected RFICs to form two streams (shown in red and green color).
Since each RFIC has been envisioned with IF and BB mixers for two-stage sliding-IF down conversion, the LO also needs to be routed to each RFIC. In each column, LO is distributed in a daisy-chained fashion. Depending on the floorplanning, the LO can enter the grid from a synthesizer either via the first row or the Mth row. Given the regularity of the  M × N grid of RFICs along with vertical and horizontal C2C connections, λ/2 spaced patch antennas, and daisy-chained LO. Also shown is one possible way to create two non-overlapping logical streams (marked red and green). Red and blue bi-directional arrows represent the vertical and horizontal C2C connections, respectively. Orange-colored uni-directional arrows represent the LO. structure, from a manufacturing standpoint, it responds well to scaling via tiling.
In this architecture, antenna combining can be achieved dynamically at four levels. At the first level, each RFIC locally combines signals from antennas connected to its FEs. The second level of combining involves the horizontal C2C interface. Here, the aggregated signal, after the local combining, can be coherently combined with the input signal of the horizontal C2C interface, which can be propagated further via the output port of the C2C interface. Thus, the second level of combining allows combination over a row in the grid. This second-level aggregated signal, after the frequency conversion, can then be used for a third level of combining using the vertical C2C interface. The combination via vertical C2C interface behaves similar to the horizontal combining. Thus, the third level of combining allows combination over a column in the grid. The fourth level of combining can be done either in analog or digital BB as proposed in [29]. This architecture provides the following advantages.
1) Flexibility of coherently combining antennas without requiring a tree-like symmetrical routing.
2) Dynamic combination of antennas from different rows and columns, thus, allowing changing of beam patterns and beam properties like inter-beam interference at runtime. 3) Avoiding the losses of passive combining by utilizing active combining.

B. Asymmetrical Combining
The second and third levels of combining, which this architecture proposes, utilize the on-PCB C2C transmission lines. Even though the RFICs are distributed in a regular grid structure, in order to reduce the losses of routing and passive combining, the routing is not done in a fully symmetrical tree-like fashion. Thus, for coherent summation over the row, while using the horizontal C2C interface, the extra time delay caused by the PCB transmission lines has to be compensated. Similarly, extra time delay has to be compensated for coherent summation over a column using the vertical C2C interface. Furthermore, as the LO is actively distributed in a column, there will be a phase difference between the LO signal received by the different RFICs in a column. The LO phase difference across a column can be compensated either by utilizing phase shifters in the LO path or by providing an additional phase shift to all the FEs in the particular RFIC.
In order to compensate for the excess chip-to-chip time delay in the second and third levels of combining, an active vector summing phase shifter (VSPS) is used. Moreover, utilizing a VSPS for compensating a time delay is a bandlimited operation and has some effect on the beam pointing accuracy of the beamformer when the fractional bandwidth is high enough [37], [38]. The extent of these effects is demonstrated in Section IV. It should be noted that the asymmetry makes the beam synthesis more complex and thus requires advanced beam management schemes in signal processing.

C. Dynamic Reconfigurability
Dynamic reconfigurability refers to the fact that the RFICs and thus antennas, can be combined dynamically. Fig. 2 shows the complete grid being split into two streams along the diagonal i.e., RFICs labeled U M−1,1 , U M−2,2 , . . . , U 2,N −2 , and U 1,N −1 , are part of the upper diagonal area for the stream marked with a green background. For a given number of BB streams, these boundaries are programmable and can be varied when needed. This functionality is achieved by pairing the C2C interface with a switchable many-to-many routing matrix. The routing matrix is in principle a collection of multiple active splitters and combiners. The only thing limiting the flexibility is the number and locations of BB inputs and outputs. This reconfigurability allows for tailoring of the vertical and horizontal resolutions of the beam at will.

III. RFIC DESIGN
In this section, the design choices and the internal structure of the implemented RFIC are described.

A. RFIC Architecture
A simplified block diagram of the implemented RFIC is shown in Fig. 3. It is a sliding IF architecture that contains all components from mmWave FEs to an analog BB. As seen, the RFIC contains several blocks including eight FEs (FE [1][2][3][4][5][6][7][8] which can be combined to form a max of two logical streams, a dual stream mmWave active combining network, a dual stream mmWave routing matrix (mRM), four mmWave C2C interfaces (mC2CL A-B and mC2CR A-B ), two IF C2C interfaces (iC2CU and iC2CD), a complex BB, an IF routing matrix (iRM), active and passive mixers, frequency multiplier, divider, and LO buffers for internal LO distribution and daisychaining.
Each FE has a TRX switch, PA, LNA, two VSPSs, and to support different operating modes, an active combining block, and an active splitter. On the receiver side of the FE, a singleended RF signal enters from the antenna port and goes to the TRX switch, which directs the signal toward a three-stage LNA. The second stage of the LNA converts the single-ended signal to a differential and the rest of the processing happens on this differential signal. Depending on the physical number of the FE, the LNA is followed either by an active splitter or a combiner. All odd numbered FEs (FE 1,3,5,7 ) have an active combiner and even numbered FEs (FE 2,4,6,8 ) an active splitter. The last block in the RX chain, before the signal is combined with other FEs using an active combiner is an active VSPS. This VSPS is responsible for beam-steering.
Similarly, at the transmitter side of the FE, a differential signal enters an active VSPS which is followed by either an active splitter or a combiner depending on the physical number of the FE. The signal enters a multistage differential PA whose last stage also performs differential to single-ended conversion, before feeding it to the TRX switch. As this article is focused on the receiver side, there is no additional description related to the TX chain.
The RFIC supports two operating modes for the combination of the local FEs. In mode I, odd-numbered FEs (FE 1,3,5,7 ) are combined to form stream A (red colored lines in Fig. 3) and even-numbered FEs (FE 2,4,6,8 ) combine together to form stream B (green colored lines in Fig. 3). In this mode, the cross-connection between the neighboring FEs is turned off. This mode is designed for handling dual-polarized antennas or in general for supporting two independent sub-arrays. Thus, the two independent mmWave streams can correspond to vertical and horizontal polarization data, for example. In this mode, the RFIC can handle a total of eight antennas or subarrays. In mode II, or hybrid mode, the TRX switch and LNA of the odd-numbered FEs (FE 1,3,5,7 ) are turned off and the cross-connection between the neighboring FEs is turned on. This allows to generate two differently oriented spatial streams from the same antenna, allowing the RFIC to handle four antennas or sub-arrays. These two modes are shown in Fig. 4.
After combining, the RX side of the two mmWave streams ends up at the mRM. The mRM also interfaces with the four C2C interfaces (mC2CL A-B and mC2CR A-B ) and the mmWave-IF mixers. Both mmWave streams are handled independently of each other in the mRM. A detailed signal flow diagram of the mRM for one stream is shown in Fig. 5. Description of the signal labels of Fig. 5 can be seen from Table II. All the combiners and splitters used in the mRM are active in nature and can be turned on or off independently via digital controls. The independent controls allow a plethora of combinations for the signal paths, but only a selected few of these combinations are listed below.   Table II. 2) swMode II: This mode is suitable for RFICs that are not on the edge of a panel. Here, the local signal is first combined with the input signal from any of the two mmWave C2C interfaces and the combined signal is routed toward the output interface of any of the mmWave C2C interfaces. Here too, the local BB is turned off. This mode differs from swMode I in that here the second level combining happens. 3) swMode III: This mode is useful for routing the combined signal toward the IF processing. In this case, the local signal is first combined with the input signal from any of the two mmWave C2C interfaces just like in swMode II. However, instead of going outside of the RFIC, this combined signal is routed toward the mmWave-IF mixer. 4) swMode IV: This is a debug bypass mode useful for testing. Here, the signal does not take part in any combination and just flows from the left or right input side (mC2C L/R IN) to the left or right output side (mC2C L/R OUT). After the mRM and the mmWave-IF mixers, the signal path enters iRM. The iRM is similar in functionality to mRM with The first level of frequency conversion happens via the mmWave-IF mixers, which are active double-balanced Gilbert cell-based mixers. The second level of frequency conversion happens via passive IF-BB mixers. Given the single stream handling in the IF domain, the RFIC has only one complex BB and one set of IF C2C interface (iC2CU and iC2CD).
The RFIC employs a sliding IF architecture. Every RFIC gets an external local oscillator (LO) signal of frequency 7.4-11 GHz ( f lo ), and doubles it internally via a multiplier to 14.8-22 GHz. The input RF signal is at 3 f lo , and the IF is at f lo . The internally generated 2 f lo is used to generate quadrature LO at f lo for IF-BB conversion via a divider. These mixing stages are enabled only when needed in the architecture.
The horizontal C2C interfaces have a VSPS at the output point for compensating the excess C2C time delay. The vertical C2C interfaces do not have any VSPS, thus, for coherent summation over different columns, combined row output has to be rotated using the VSPS in the FEs. Furthermore, to minimize the phase noise, there is no VSPS for the LO input. Thus, the LO phase difference also has to be accounted for via the FEs' VSPS.
B. RFIC Circuit Details 1) TRX Switch: The TRX switch utilizes quarter-wave transmission lines, which are implemented here using lumped components. Grounding shunt switches are used in order to improve the isolation. The design is similar to the front-end switch as shown in [39], but with single-ended topology and omission of series switches for simplicity. The schematic of the implemented TRX switch is shown in Fig. 6.
For the TX shunt switch, oxide breakdown is circumvented by stacking five transistors in series. In the off-mode, they generate a capacitive voltage divider and pass a 15 -dBm output signal without breakdown or additional distortion.   The simulated input compression point and loss of the switch in the receive mode are plotted in Fig. 7.
2) LNA: The schematic of the LNA is shown in Fig. 8. Input is matched for minimum noise with a series inductor (L 2 ) and degeneration inductor implemented with a transmission line (TL 1 ). Transistor width of 30 µm is chosen as a compromise between low noise and power dissipation. Component values are optimized to have a bandpass response from 24 to 29-GHz band. The LNA does not have a dedicated gain control, but adjusting the bias provides more than a 20-dB gain control range.
3) Vector Summing Phase Shifter: All of the phase shifters used in this RFIC are active in nature. The VSPS used here is based on the similar circuit presented in [40].
The VSPS used in the C2C interfaces and the FEs differ from each other in their output stage. As the VSPS in FEs drives internal active blocks, the output driver is a fixed gain differential amplifier. However, in the case of C2C interfaces, the output stage has to drive a 100 differential load, thus, a larger variable gain amplifier is used. Circuit diagram for the mmWave distribution network used for combining the receiver side mmWave RF signals from the FEs. Circuit for only stream A is shown.
The VSPS provides up to 0.5 • of phase resolution at maximum amplitude and about 10 dB of usable gain control range with a somewhat reduced phase resolution. 4) mmWave Active Distribution Network: The mmWave signals from the FEs are combined together first in the distribution network. Throughout the RFIC, signals are combined in the current domain. The technique used for the same is to first convert the voltage signal to the current one via a g m stage, transport it to the common point of combining via differential co-planar lines and do the summing and conversion to voltage domain via a folded-cascode type low-ohmic receiver. The signal combination for the four FEs happens in two stages. In the case of stream A, at the first level, FE 1 and FE 3 , and FE 5 and FE 7 are combined. These two combined signals are then combined with each other. The circuit for combining four sources into one output is illustrated in Fig. 9. A similar structure is used for stream B.
The g m stages are implemented using a standard differential amplifier with switchable bias controls. The bias control is used for turning off inputs that are not participating in the summation. The low-ohmic folded-cascode receiver performs resistive matching and isolation of the nodes at the same time. Co-planar lines are designed using the top two copper layers. They are built by repeatedly tiling the structures shown in Fig. 10. In order to keep the routing complexity manageable, a fixed BEOL metal layer is used depending on the routing direction i.e., the top copper layer is used for creating the coplanar lines that are traversing in the horizontal direction, and the penultimate copper layer is used for vertical routing. 5) mmWave Routing Matrix: The mRM is responsible for the second level of combining and moving the RF signals around to support reconfigurability. The simplified schematic is shown in Fig. 11. A single combiner is used to combine the differential RF currents coming from the FEs, right side  mmWave C2C interface, and left side mmWave C2C interface. Each path has a PMOS switch to isolate the unwanted path. These RF currents sum up at the folded cascadebased combiner, which then, in turn, drives three different g m stages which are routed toward the mmWave mixer, left side mmWave C2C interface and right side mmWave C2C interface.
6) IF Routing Matrix: The iRM is responsible for the third level of combining. It interfaces with mmWave-IF mixers, RFIC C2C interfaces, and the BB. The simplified schematic is shown in Fig. 12. A single folded cascade-based combiner is used to combine the differential IF currents coming from the mmWave mixers, up side IF C2C interface, and down side IF C2C interface. The g m stages providing these IF currents have independent biasing. After summation, the signal is routed toward local BB and IF C2C interfaces via g m stages.
7) mmWave Chip-to-Chip Interface: Each RFIC has four C2C interfaces operating in the mmWave frequencies and is arranged on the left and right sides of the RFIC. These are used for interfacing with other RFICs and thus play an important role in providing reconfigurability. Furthermore, to aid the testing capability of the C2C interfaces, a loop-back mode is implemented.
A C2C interface has differential inputs and outputs. At the input side, there is a common-source true differential amplifier with a tail inductor. The simulated differential gain of the input amplifier is around 15 dB. Input matching is done by a combination of a shunt inductor and shunt resistors. This is done to provide wideband matching and burn any reflected signal when the interface is off. The resistors, however, do degrade the NF a bit. On the output side, there is a VSPS which is used to compensate for the C2C propagation delay effects before combining neighboring RFICs. At the output of the VSPS, to provide coarse gain control, there are two independent common-source amplifiers with a transformer as a load. The secondary side of the transformer is connected to the output C4 bumps.

8) LO Distribution:
The RFIC gets an external differential LO signal via either a synthesizer (LMX2594) mounted on the PCB or a signal generator. The input LO is buffered using a tuned common-source amplifier and then split into two paths, with one path going out of the RFIC and the other going toward a multiplier. The LO signal going out of the RFIC is daisy-chained vertically. Internally, the LO is multiplied by a differential digitally controlled injection locked doubler that has a 3 dB tuning range from 14 to 20 GHz with 0 -dBm input power [41]. The doubled LO is routed to both mmWave-IF mixers and via a divide-by-two circuit to the IF-BB mixers. 9) mmWave-IF Mixer: A Gilbert cell-based active mixer is used to down-convert the mmWave signal to IF. The schematic for the same can be seen in Fig. 13. Both inductors, L m and L cm , suppress the even-mode harmonics of the LO and RF signals, improving IIP2.
10) Analog Baseband (Receiver): A simplified schematic for the analog BB is shown in Fig. 14. Besides the mixer for down-converting IF to BB, it also includes a frequency divider, LO drivers for the mixer, a vector modulator (VM), and a self-biased inverter-based transimpedance amplifier (TIA). The VM is present because multiple RFICs can be weighted and combined using the BB.
From IF to BB down-conversion, along with VM, is implemented via a constant-Gm VM topology [42]. Here, current combining via TIA is used instead of charge-sharing as utilized in conventional design. The low impedance node at   the TIA input further provides frequency range extension [43]. The TIA is implemented using self-biased inverter amplifiers with common-mode feedback (CMFB) [44], and its schematic can be seen in Fig. 15. Transistors with long channel lengths (L = 0.112 µm) are employed to achieve large TIA openloop gain. Both the feedback resistor (R FB ) and capacitor (C FB ) of the TIA are implemented in a programmable way to provide gain and bandwidth variability. In order to drive the large capacitive load of the VM, a g m stage along with a transformer is used. Two lumped capacitors of values 400 and 300 f F, along with variable switch-capacitors from 26 to 208 f F, have been added to the primary and secondary side of the transformer, respectively.
The VM is implemented by combining 15 identical slices. The schematic of a single slice is shown in Fig. 16. Each slice contains a self-biased pseudodifferential g m , a double-balanced passive mixer, and static reconfiguration switches steering the transconductor current in order to provide a phase shift. The VM slices are dc-coupled and the source and drain terminals of the mixer switches are biased at half of the supply via the self-biased TIA and g m stages. LO level shifter, as shown in Fig. 16, is used to increase the gate voltage of the mixer switches.
The I /Q clock generation is done via the current mode logic divider with PMOS load. It divides the multiplied-by-2 clock by 2 and generates the four phases with a 50% duty cycle. The 25% duty cycle clock is generated using the AND gate logic.

C. Receiver Partitioning
Simulated performance for the single receiver chain is shown in Fig. 17. Here, the signal is going from the input of the FE to the BB output. Connection points to and from the mmWave C2C signal path and IF C2C path is also marked. Simulated data for the gain, input compression point (IP 1 dB ), and NF for the FE are shown at two different bias configurations. It can be seen from the figure that the linearity for the single receiver chain is limited by the large FE gain. Furthermore, in the minimum gain case, the mixer and the downstream blocks become the bottleneck for linearity. Extrapolating from this data, the estimated IP 1 dB for combining four FEs will be in the range from −64 to −44 dBm. From the noise perspective, the large gain of the FE effectively dominates the NF.
Similarly, simulated receiver parameters of mmWave C2C interface and IF C2C interface are shown in Figs. 18 and 19, respectively. The gain of these interfaces is designed to be low and just enough to overcome the PCB path losses. Looking at the NF of the output end of the mmWave C2C interface, it can be seen that it is large. This is largely because of two reasons, the first one is the presence of a VSPS. The second reason is related to the signal combiner that is just before the VSPS. It is combining the signal coming from the local loop-back and the debug bypass from the mRM. Both of these paths are debug paths and at the combining end, share the biasing with the main path. Thus, even though the source g m stages which are providing the debug currents can be turned off, because of the shared biasing control, the combiner is still receiving noise from these paths. The output side of the IF C2C does not have a VSPS nor a debug bypass current. It has to be noted that the VSPS in the mmWave C2C interface can be moved Fig. 17. Simulated receiver parameters for the single chain when the mmWave signal is propagating from one FE to the BB of the same RFIC. Estimated IP 1 dB while combining four FEs will be in the range from −64 to −44 dBm.  Receiver parameters for the signal path between the IF C2C interfaces.
to the LO path without impacting the system functionality. However, keeping it here keeps the system logically organized. This design decision, however, forces a compromise in noise while helping in the testing of the prototype.
Large gain of the FEs, along with the limited linearity of the mixers, results in reduced dynamic range in case of high input power levels. As shown later in EVM variation measurements, with efficient gain control this problem can be overcome even for high-order modulations in the case of a single RFIC. However, when combining many antennas over several RFICs, limited dynamic range becomes a bottleneck. This may require a revised gain partitioning along with a re-design of the key building blocks based on tighter linearity specifications. Circuit design techniques such as current bleeding and derivative superposition [45] can be used to improve linearity. It should be noted that the issue of limited linearity when combining many antenna elements, is not just inherent to the presented architecture. It equally plagues the conventional corporate-fed arrays as it depends mostly on the number of antenna elements being combined.  Fig. 20(a). The overall dimensions of the RFIC are 4.4 × 8 mm. Dimensions of a single FE are 1.6 × 0.9 mm. Normalized area per element per stream is estimated to be 2.7 mm 2 , calculated similarly as in [24]. DC power consumed by the various blocks from 1 -V supply is shown in Table III. As seen from Table III, in terms of power consumption, combining multiple antennas to one BB by using a C2C interface is more efficient than external combining via multiple BBs. The normalized power consumption will further decrease as the number of antenna elements combined via the C2C interface increase.
The PCB used for measurements is shown in Fig. 20(b). It is an eight-layer board manufactured using Panasonic's Megtron7 substrate (ε r = 3.34). The cross section of the PCB along with the PCB layer usage can be seen from Fig. 21(a). The RFICs are flip-chips and are directly bonded to the PCB. Controlled collapse chip connection (C4) of size 73 µm with a minimum pitch of 150 µm are used. PCB footprint of the RFIC is shown in Fig. 21(b). Simulated isolation between different mmWave PCB ports was found to be in excess of 30 dB. The PCB has two RFICs U 1 and U 2 . Test PCB with two RFICs, U 1 and U 2 , connected using the mmWave C2C interface. RFIC U 2 is used specifically for verifying the C2C interface functionality. In order to differentiate between FEs connected to the two RFICs, the corresponding PCB ports are labeled with the RFIC number in the subscript. The RFICs are further connected to each other via their right and left mmWave C2C interfaces, respectively. All FEs of U 1 are connected to the subminiature push-on micro (SMPM) connectors. However, due to area limitations only FE 8 of RFIC U 2 is connected to an SMPM connector, while the other FEs are permanently terminated with a 50-resistor. For the same reason, the IF C2C interfaces and BB interfaces of only the RFIC U 1 are connected to external connectors. PCB ports marked mL A and mL B are connected to the left side stream A and stream B mmWave C2C interface (mC2CL A and mC2CL B ) of RFIC U 1 , respectively. Likewise, PCB ports mR A and mR B are connected to the right side stream A and stream B mmWave C2C interface (mC2CR A and mC2CR B ) of RFIC U 2 , respectively. PCB ports labeled iU and iD are connected to the upside and downside of the IF C2C interface (iC2CU and iC2CD) of RFIC U 1 , respectively. It has to be noted that the length of the PCB line connecting FE 8/2 is about 44 mm longer than the PCB lines used for connecting FE 1-8/1 to their corresponding FEs on U 1 . Furthermore, it is almost ten times longer than the RFIC-to-RFIC interconnect. This needs to be taken into account when beam pattern measurements are performed. Unless otherwise specified, the reference plane for all the measurements is set at the input of the PCB connectors, i.e., connector losses and PCB line losses are part of the measured results.

A. Conductive Measurements
Frequency responses are measured from different mmWave inputs both with fixed LO (BB response) and variable LO (RF response). Fig. 22(a) shows the high side BB gain a response from different inputs. The output is taken only from the I branch of the BB. A four-port VNA along with an external LO generator is used for the measurements. Here, the mRM of RFIC U 1 is operating in swMode III and RFIC U 2 is operating in swMode I, as defined in Section III-A. Furthermore, FE 8 of both U 1 and U 2 have been measured in normal mode (mode I) and hybrid mode (mode II). Fig. 22(a) shows that in all of the modes, there is roughly 47 dB of gain from input of the FEs to the output of RFIC U 1 BB. The solid lines show the gain when the VNA input port is on the FE 8 of RFIC U 2 and the dashed lines show the gain when the input port is connected to the FEs of RFIC U 1 . For both U 1 and U 2 , the gain difference between the two FE modes (mode I and mode II) is less than 1 dB. The gain difference between the two RFICs is less than 2 dB which can be corrected via either the gain control in the C2C interface or the LNA bias settings. Furthermore, there is around 17 dB of gain from both the mmWave C2C interface and from the IF C2C interface to the BB. The input frequency for the mmWave inputs is varied from 27 to 30 GHz. In the case of the IF input, the input frequency is varied from 9 to 12 GHz. The LO frequency is kept constant at 9 GHz. Fig. 22(b) shows the normalized gain for one of the FE inputs in order to showcase the bandwidth variation capabilities of the RFICs BB. It can be seen from the figure that the BB bandwidth can be varied from 80 to 430 MHz, depending on the bandwidth of the received modulated signal.
The RF response from different inputs down-converted to a fixed BB frequency of 50 MHz is shown in Fig. 23. The frequency for the mmWave input is varied from 24 to 30 GHz. Looking at the RF response from the mmWave C2C interface in Fig. 23(a), it can be seen that the gain difference between the left (from mL A to RFIC U 1 BB) and the right (from mR A to U 1 BB) side path is around 1.5 dB. The RF response for the IF C2C interface is presented in Fig. 23(b). The input is connected to the up-direction IF PCB port (iU) and is varied from 8 to 11 GHz. Besides the peak RF gain of 16 dB, the figure also shows the combined locking range of the frequency multiplier and divider, which is 8.1-10.7 GHz. RF response from FE 8/1 to FE 8/2 in both normal (mode I) and hybrid mode (mode II) can be seen from Fig. 23(c).
The measured noise figure (NF) at a fixed BB frequency of 100 MHz is shown in Fig. 24. The figure shows the NF for both FE 8/1 and FE 8/2 in both normal (mode I) and hybrid mode (mode II). Keysight UXA N9040B along with a broadband noise source (346CK01) is used for measuring the NF. The simulated losses of the PCB lines are calibrated. The minimum  NF value of 6.2 dB occurs at 26 GHz. Looking at the simulated NF presented in Section III-B10, there is a 1.2 dB difference compared to the measured results. A small part of it can be attributed to the inaccuracies in the measurement setup. Another reason is related to the simplifications done in the simulation setup.
Given the single-ended nature of the FEs and their large gain, there can be significant coupling between different FEs. Furthermore, based on the coupling mechanism and phase, its value can be dependent on the phase shift provided by the VSPS. To verify this, coupling between adjacent FEs (FE 1 and FE 2 , FE 3 and FE 4 , and so on) and facing FEs (FE 1 and FE 5 , FE 2 and FE 6 , and so on) is measured as a function of phase shift provided by one of the VSPS. The worst-case coupling measured is of the order of −30 dB.
In order to understand the combined behavior of noise, linearity, and gain of the input stage, multiple noise and compression measurements are done using different bias settings for the LNA. For these measurements, FE 2/1 of RFIC U 1 is the input port and differential output is taken from the mmWave C2C interface mL A . The combined results are Fig. 25. Gain, NF, and estimated dynamic range of the mmWave path as a function of its input compression point. A 500 -MHz signal bandwidth is used for the dynamic range calculations. Signal input is at the FE of RFIC U 1 and differential output is taken from the same RFICs mmWave C2C interface. A similar method as in Fig. 24 is used for the noise measurements. plotted in Fig. 25. The figure shows the measured NF, RF gain, and the estimated dynamic range for a 500 -MHz signal as a function of input 1 -dB compression point. The dynamic range is defined as P out −P noise , with P out being the output signal power as defined in (1), and P noise is the output noise power as defined in (2) [46]. P i1 dBm refers to the input 1 -dB compression point, G 1 dB refers to the gain at 1 -dB compression point, B is the bandwidth and NF is the noise figure P out = P i1 dBm + G 1 dB (1) P noise = −174 + 10 log B + NF + G 1 dB . ( It can be seen from the figure that the available dynamic range varies from 33 to 48 dB as the gain decreases from 31 to 5 dB. This is because of the increase in compression point with decreasing gain and thus higher input signal power can be fed. These curves can be utilized for designing gain control for the receiver. Comparing these numbers with the simulated results in Section III-B10, it can be seen that the values do agree with in a margin of 2 dB. It has to be noted that the measured path shown here, is not directly depicted in either Figs. 17 nor 18 and has to be calculated utilizing data from both Figs. 17 and 18. Given the relatively high power of the LO compared with other signals in a receiver along with the presence of a frequency doubler on the RFIC, LO leakage is measured at different ports of the RFIC. The different ports where LO leakage is measured are shown in Fig. 26 and the results are displayed in Fig. 27. Input LO of 9 GHz is fed from an external signal generator at a power level of 4 dBm measured at the PCB port. The strongest LO leakage is seen at the FE input port, with the 9 GHz LO being measured at a level of −47.5 dBm. No noticeable leakage is seen at the IF C2C ports and the leakage at mmWave C2C output interface is at a level of −62 dBm. Similar levels of LO leakage are also measured at the BB ports.  (c) At differential IF C2C input port. (d) At differential IF C2C output port. (e) At differential mmWave C2C input port. (f) At differential mmWave C2C output port. (g) At differential BB I port. (h) At differential BB Q port. The calibration plane is at the PCB connectors.
In order to understand the limitations of the different signal paths of the RFIC that are essential for reconfiguration requirement (shown in Fig. 28), gain and compression measurements are done. No input signal is fed to the FEs in these measurements. These results are tabulated in Table IV. Path A corresponds to the case where the RF signal from other RFICs goes through the mmWave C2C interface and is combined together with the local FE signals and is then downconverted to BB. Path B corresponds to the case of transferring the signal across the RFIC. Path C is equivalent to path B, however, operating in the IF domain via the IF C2C interface. Path D integrates one frequency conversion, from mmWave to IF. Path E corresponds to moving the signal from IF to BB. The target for the C2C interfaces is to have unity gain between Conductive modulated measurements are performed using the setup shown in Fig. 29. Fig. 30 shows the EVM variation with respect to the input power for different 5G NR waveforms. Different curves correspond to different bias settings for the LNA, i.e., different gain values. It can be seen from the figure that for a 100 -MHz wide signal, i.e., one component carrier (1 CC), the DUT can be configured to have an EVM of under 8% for an input power range from −60 to −25 dBm. Furthermore, for one fixed bias setting, there is a range of around 17-21 dB over which the received signal has the required fidelity. As expected, the power range decreases as the bandwidth of the modulated signal increases as seen from the traces of 400 MHz wide signal (4 CC), which has EVM less than 8% over an input power range from −55 to −27 dBm. For a 200 MHz wide 256 QAM signal, given the high dynamic range required, the available power range over which the EVM is less than 3.5% is from −47 to −32 dBm. Constellation diagrams for these different modulated signals are shown in Fig. 31. The EVM limits of 8% for 64 QAM and 3.5% for 256 QAM are obtained from the transmitter specification for the FR2 band [47]. These curves also demonstrate the optimum EVM window. It should be noted that the peak-to-average power ratio for the 5G NR waveforms is around 10.5 dB, around 5 dB higher when compared with the similar single-carrier waveforms. This along with the limited linearity of the DUT are the major reasons which limit the optimum EVM window.
In order to verify the efficacy of performing signal combination over the mmWave C2C interface, two FEs  Different curves correspond to different gain values of the LNA. EVM limit for different modulation schemes as defined in the 3GPP specifications [47] for the transmitter side is marked by a black dashed line. were combined using either a single RFIC or two RFICs, as shown in Fig. 32. The VSPS was configured for 27 GHz of operational frequency. Fig. 33 shows the measured results.  Normalized gain is plotted for both cases first as a function of the relative phase shift between FEs and then as a function of the frequency. In order to ease the analysis of the top half of Fig. 33, the traces are circularly shifted so that the minimum occurs at a phase shift of 180 • . It can be seen from the figure, that in both cases the signal amplitude increases by 6 dB when the signals are in phase. However, looking at the frequency response from the bottom half of Fig. 33, it can be noted that for the two RFIC cases, the frequency range over which two signals are coherent is considerably smaller than the one RFIC case. One possible explanation for this behavior is the long PCB line over which signal for FE 8/2 travels.

B. Over-the-Air Measurements
The setup for performing the over-the-air (OTA) measurements is shown in Fig. 34. At the transmitter end, an external amplifier (CA2630-141) along with a horn antenna (LB-28-15) is used. The horn antenna is mounted on a fixed tripod and is placed in far-field 2.7 m away from the DUT. At the receiving end, a 64-element antenna array is used [48]. It is made up of 16 unit cells, with each unit cell containing four linearly polarized patch elements arranged in a 2 × 2 configuration. Four FEs of the DUT are connected with four unit cells of the 64-element antenna array and are mounted on a rotating platform. Measurements using both continuous wave and wide-band modulated signals are conducted. The link budget for the OTA measurements is presented in Table V.
Two different scenarios are compared in these measurements. In the first scenario, the four-unit cells of the antenna array are combined at mmWave using a single RFIC (U 1 ). This combined signal is either routed to PCB port mR A via  mmWave C2C interfaces for calibration or down-converted to BB for measurement. FE 1,3,5,7/1 are used in this scenario. In the second scenario, three FEs (FE 1,3,5/1 ) from RFIC (U 1 ) are used and one FE (FE 8/2 ) from RFIC (U 2 ) is used for combining. FE 8/2 is operated in hybrid mode and routed to RFIC U 1 via the egress port of U 2 's mmWave C2C interface (mC2CL A ). The combination happens in RFIC U 1 and the combined signal is again either routed toward PCB port mR A via the The measured normalized beam patterns for both one RFIC and two RFICs with four antenna ports, i.e., 16 antenna elements are shown in Fig. 35. The different colored curves in the figure show the main lobe being pointed toward five different directions. Furthermore, in both cases, the beam patterns have roughly the same shape. Fig. 36 shows the EVM results for a 4 CC 64 QAM NR FR2 waveform. Here too, in both cases, similar EVM is achieved and the EVM is distributed spatially in roughly the same pattern. The measurements are done at a mmWave frequency of 27 GHz.
In order to visualize the beam pointing error which occurs when compensating time delay with phase shift, an 8 CC wide NR FR2 waveform is used for measuring the spatial distribution of EVM and the results are plotted in Fig. 37. It can be seen from Fig. 37(a) that in case of single RFIC combining, even with an 800 MHz wide signal, there is almost no difference in the beam pointing. That is, both the lowest and highest frequency CCs (CC 1 and CC 8) achieve their minimum EVM at roughly the same azimuth angle, which coincides with the azimuth angle at which the normalized beam pattern achieves its maximum. However, for the two RFICs case in Fig. 37(b), the individual CCs are pointing to different directions and the pointing error for CC 1 and CC 8 is  around ±5 • . Yet, the azimuth pointing angle for the average EVM for all the CCs still coincides with the azimuth angle of the normalized beam pattern showing no degradation in total signal quality. One must note that the input signal path lengths are very different between the two RFICs due to the test setup limitations. This introduces a larger asymmetry than anticipated in a complete phased array.
Comparisons with other relevant recent works are shown in Table VI. It can be seen from the table that the single element performance in terms of BB bandwidth and RF gain exceeds compared with the recent works. This work provides the most versatile capabilities for reconfigurability in largescale phased arrays at the cost of marginally larger normalized area and power compared with [28] and [31].

V. CONCLUSION
In this article, an architecture to enable a flexible and programmable organization of single antennas in a large antenna array was proposed. This was achieved with an RFIC with multiple C2C interfaces. The proposed transceiver architecture with the C2C interfaces enables extremely versatile mechanisms to configure large antenna array panels to support communication using multiple simultaneous beams. The RFIC was designed and fabricated using GF 45 -nm PDSOI technology, and its performance was verified via both conductive and OTA measurements. The receiver performance of the mmWave RFIC was measured. Gain control was implemented by changing the bias. For beamforming, phase shifting was performed at RF using an active vector summingbased phase shifter. Furthermore, a two RFIC test PCB was constructed to validate the concept of a dynamically configurable beamformer utilizing the mmWave C2C interface. Beam pattern measurements were conducted for a combination of four sub-arrays over the mmWave C2C interface. No additional pointing error for the main lobes was found compared with similar measurements using a single RFIC.
The Achilles heel of this work seems to be the relatively low linearity that limits the power over which minimum EVM is achieved, as seen in Fig. 30. This limitation stems from the combination of excessive gain at the FE, along with the limited linearity of the mixer and downstream blocks. This is further exacerbated by the lack of independent gain control, as the bias-based gain control impacts linearity at the same time. Furthermore, it can be hypothesized that the linearity of the mRM and iRM may also become a bottleneck when combining a large number of RFICs. Having said that, the limitations are in the implementation and are not inherent to the architecture and these imitations can be overcome via revised gain partitioning, careful circuit design, and using techniques such as current bleeding and derivative superposition.