A Foil Flip-Chip Interconnect With an Ultra-Broadband Bandwidth of 130 GHz and Beyond for Heterogeneous High-End System Designs

This paper presents an ultra-broadband, low-loss, flexible liquid crystal polymer substrate-to-substrate interconnect with a bandwidth of more than 130 GHz. The transition discontinuity was minimized by maintaining both the reference impedance and the electromagnetic field conformity across the transition from alumina substrate to flip-chip foil. Therefore, more than 600 $\mu$m long flexible flip-chip interconnects can be realized for bridging millimeter-wave sub-modules and enabling ultra-broadband heterogeneous system design with a measured return loss of above 20 dB. Furthermore, the interconnect can realize ramp interconnections between monolithic microwave integrated circuits or substrates with different substrate heights due to the flexible foil substrate. Minimum parasitic radiation at the transition is realized through a closely spaced signal-to-ground connection. Furthermore, the robustness of the proposed interconnect against lateral misalignment in the assembly is presented through simulation and measurement. An outstanding insertion loss of less than 0.3 dB per transition over a bandwidth of more than 130 GHz is shown.


I. INTRODUCTION
The heterogeneous integration and chiplet approach is a very promising packaging and assembly technology for realizing future high-performance systems that meet bandwidth requirements for high data rates communication or sensing resolutions [1], [2], [3], [4].The best implementation technology is used for each sub-module of the system, active components in the optimum semiconductor technology and passive elements, such as filters and couplers, based on glass or aluminum oxide [1].This improves the performance of the overall system compared to monolithic system-on-chip (SoC) designs [2], [3].Furthermore, heterogeneous system integration increases the yield of semiconductor manufacturing compared to SoC because smaller chiplets can be manufactured with higher repeatability than large-area SoC components [2].Moreover, better thermal management of the heat sink of every millimeter-wave (mmW) sub-module can be realized in the heterogeneous system assembly [2].However, a limiting factor in the design of heterogeneous systems is the packaging.Much more effort has to be put into the design of the interfaces and the module assembly.A heterogeneous system is realized by a cascade of several sub-modules, each connected by interconnects.Seamless connection of all submodules and, thus, maximum system performance can only be achieved with a high-performance interconnect.Therefore, previous studies have investigated the interface optimization to overcome bandwidth limitations of current available interconnect solutions [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12].The flip-chip approach is mainly used to interconnect sub-modules.In terms of matching bandwidth and robustness to parasitic effects, the flip-chip approach is usually preferable to the bond-wire interconnect.Nevertheless, we were able to demonstrate in [12], [13] that by properly aligning the substrates and optimizing the interface, an ultra-broadband bond-wire interconnect can be designed that eliminates the bandwidth limitation of existing bond-wire interconnects.
However, this is only possible if the bond-wires can be designed to be short and compact, to minimize the bondwire length and, thus, minimize the wire's inductive behavior.If this is not possible because, for example, the substrate heights of two sub-modules differ, the flip-chip approach can be chosen.Bump transitions from indium phosphide (InP) heterojunction bipolar transistor (HBT) to aluminum nitride (AlN) ( [4], [5], [6]) or from silicon-germanium (SiGe) BiCMOS to InP DHBT [3] have been shown to be realizable using flip-chip technology.In this approach, a MMIC is flipped onto another substrate.Especially when interconnecting substrates with different material properties, such as semiconductor materials with alumina or glass substrates, the thermal stress during the bonding must considered so as not to degrade the semiconductor technology [3].Care must also be taken to prevent cracking of the bump interconnect, especially if the substrates have different coefficients of thermal expansion (CTE mismatch).An alternative approach to the flip-chip arrangement, in which one element "floats" ([3], [4], [5], [6]), can be lateral arrangement of the modules to each other [2].This approach offers the benefit of top-up configuration, enabling direct access to each sub-module from above, such as when applying power supply.Additionally, each element mounted on the carrier allows for proper heatsink connectivity [12].An interconnection can be made with rigid bridges or flexible foil bridges [2].The flexibility of bendable bridges enables them to compensate for CTE mismatch during thermal expansion due to heat dissipation, and to overcome height differences between MMIC modules using a type of ramp interconnection.The bridging from module to module with a coplanar waveguide (CPW) on foil has already been presented in literature.In [10], a Kapton foil interconnect of up to 70GHz enabled signal transition from SiGe to alumina.SiGe BiCMOS system-in-foil was demonstrated in [11] and [14] up to 220GHz with polyimide foil and from 75GHz to 110GHz with liquid crystal polymer (LCP) foil.Compared to polyimide materials such as Kapton, LCP has a CTE of 18 ppm/K [15] in contrast to Kapton 20 ppm/K [16].An advantage of LCP over Kapton is its significantly lower water absorption rate of only 0.04% compared to Kapton's 2.8% [16].This property prevents environmental factors from affecting the dielectric loss angle of the film, making LCP the most superior material for flexible interconnects.[7] presented a broadband flip-chip transition with an LCP foil of up to 170GHz, but both the package and the dummy MMIC were made of LCP to demonstrate the approach and, thus, a homogeneous assembly setup was used.For heterogeneous system designs, the transition must be redesigned because the dielectric properties and layer stackup of MMIC and LCP are fundamentally different.In addition, the guided wavelength is significantly different between MMIC and LCP substrates.This increases the complexity of the interconnect circuit.
Therefore, this paper focuses on the optimization and characterization of an ultra-broadband, low-loss LCP-flexible bridge to interconnect high-permittivity substrates, such as alumina or MMICs, using a low-permittivity flexible foil substrate (see Fig. 1).This work demonstrates a mmWtransparent ultra-broadband interconnect approach with measured lowest insertion and highest return loss over a bandwidth of more than 130 GHz and high reliability within the assembly.The paper is organized as follows: Section II-A focuses on the layer stackup of both alumina and foil substrates.Furthermore, an ultra-broadband foil characterization is given (Section II-B), and a detailed interconnect design is described (Section II-C).A robustness analysis against lateral assembly misalignment and parasitic radiation is presented in Section II-D.In Section III, the assembly and flip-chip bonding process are described.The measurement setup and the characterization of the proposed design are shown in Section IV.Finally, the conclusion is given in Section V.

II. LAYER STACKUP, MATERIAL-CHARACTERIZATION AND FLIP-CHIP INTERCONNECT DESIGN
The layer stackup of the alumina and foil substrates used is described in detail in this section.The suitability of the foil substrate for mmW-applications at 100 GHz and beyond is also demonstrated before the design of the individual transmission line and flip-chip interconnect sections is presented.

A. LAYER STACKUP
In this paper, an alumina substrate from Kyocera [17] with a thickness of 4mil was used to demonstrate the interconnect performance.As mentioned in [12], the alumina serves as an ideal demonstrator substrate for mmW applications because of its low dielectric loss characteristics, tan(δ) = 3 • 10 −4 , and its high material's relative permittivity ε r of 9.63 ± 0.02 across a characterization bandwidth of up to 140 GHz.Thus, compact transmission line structures with a reference impedance of 50 can be realized.Furthermore, due to the similar dielectric characteristics of the alumina and MMIC technologies, the interconnect interface realized for aluminato-alumina can be easily transferred to MMIC layouts to realize an MMIC-to-MMIC interconnection.
The layer stackup and the top view of the flip-chip interconnect assembly are shown in Fig. 1.A grounded coplanar waveguide (CPWG) transmission line was used on alumina with a signal and gap width of 50 μm and 60 μm, respectively.The conductor height h cond,alumina is 4 μm and is made of gold.The galvanic vias connect top and bottom ground metallization and have a diameter of 70 μm.
A liquid crystal polymer (LCP) foil from Panasonic [15] was used as the flexible interconnect substrate.The foil's thickness is h pa = 50 μm.The conductor on foil is made of gold with a thickness of h cond, pa = 3 μm.A CPW transmission line without a backside metallization is used on foil.The foil's signal and ground traces within the area where the alumina and foil overlapped were plated with gold bumps.The height of these gold bumps are 15 μm to ensures reproducible flip-chip assembly and proper signal and ground connection (see the highlighted area in Fig. 1(a)).The transmission line and the transition to foil design are discussed in detail in Section II-C.The dielectric material properties of the LCP are provided in the data sheet at a frequency of 10 GHz.For the proposed ultra-broadband interconnect design, the suitability of the foil substrate for mmW applications of beyond 100 GHz must be proven first.This will be discussed in the next section.
Underneath the foil interconnect, the carrierboard must be removed, otherwise the CPW mode on the foil transmission line will parasitically couple to the carrier due to the about 100 μm alumina substrate height.In order to avoid this coupling and, thus, a distortion of the signal transmission, a groove was milled in the carrier.A groove depth t groove and length y groove of 200 μm and 640 μm, respectively, was chosen in the proposed assembly.The groove in the carrier not only prevents unwanted coupling paths but also enables easier trace crossing as illustrated in Fig. 1(c).The groove can be applied to IF/DC connections and to mmW traces, for example, alumina.In 3D-electromagnetic (EM) simulations, no significant coupling of the flip-chip interconnect and crossing transmission line could be determined due to a orthogonal field configuration of mmW and DC/IF traces.The possibility of crossing transmission lines significantly increases the flexibility, especially in heterogeneous system design.

B. ULTRA-BROADBAND MATERIAL CHARACTERIZATION OF THE FOIL SUBSTRATE
The complex permittivity values of alumina and the foil substrate are provided in the data sheet only at frequencies of up to 10 GHz.To evaluate the interconnect design and assembly technique, the suitability of the materials used, in this study alumina and the foil substrate, for mmW applications must first be ensured.The suitability of alumina for mmW applications was already demonstrated in [12], but that of the LCP foil remains to be shown.Special focus is given in this study to the frequency dependency of the relative permittivity ε r , especially for frequencies near and above 100 GHz, in order to detect anomalies in the LCP material at mmW frequencies.A Beatty standard was used to characterize the material and to prove its suitability.A Beatty standard, also called a "mismatch-thru" [18] or a "step-impedance line structure" [19], is a microstrip transmission line (MSL) structure that is used in the field of signal integrity and for material characterization.It is shown in Fig. 2. In this study, the increase in the width of the signal trace causes an impedance mismatch, since the line impedance is reduced from 50 to 31 .The distinct advantage of this characterization structure over a T-stub (see, e.g., [20] or [21]) is that no open or shorted transmission line stubs are used.This reduces the line discontinuity and the excitation of parasitic substrate modes or parasitic radiation at the stub's end, which could overlay and, thus, distort the actual measurement [12].Furthermore, the Beatty standard is very compact and, thus, a space-efficient characterization structure.To extract the frequency-dependent relative permittivity ε r the measurement was compared with the electromagnetic simulation in CST Microwave Studio [22].First, the actual dimensions of the manufactured Beatty standard were determined using a 3D laser scanning microscope.The measured length, width, and conductor height are 3997.1 μm, 240.9 μm, 3 μm, respectively.The width of the MSL feed is 110.1 μm.These measurements, as well as the edge geometry of the trace, are used as input parameters in the simulation setup.Furthermore, the surface roughness was measured with the 3D laser-scanning microscope.The average arithmetical surface roughness of the foil is (0.258 ± 0.03)μm and is considered in the simulation to include the effect of roughness on ε r [23].In Fig. 2(a), the material characterization standard with the feeding lines and the ground-signal-ground (GSG) probe pads is shown.The reference plane after thru-reflectline (TRL) calibration on the foil substrate itself is indicated.In Fig. 2(b), the electric field distribution with E-field maxima is shown at the resonance frequency of 140 GHz.Although a CPW on the foil is used for the interconnect (see Section II-C), an MSL structure is used in this qualification and suitability study.Even though the electromagnetic field distributions of MSL and CPW are different and the potential material anisotropies are considered differently in the characterization [12], MSL was chosen in this qualification study because its fabrication is much less complex than that of CPW.In MSL topology, small gaps do not have to be etched between the CPW's signal and ground layer, and the backside of the foil can be processed via solid-ground metallization.Thus, the qualification study of the LCP foil is focused on the substrate itself and not on complex CPW manufacturing.By including the actual structure shape and dimensions, as well as the surface roughness, the remaining difference between the simulation and the measurement is the relative permittivity ε r of the foil.The ε r in the simulation was iterated for each resonance frequency until the measurement and the simulation matched as closely as possible (see Fig. 3(a)).
As shown in Fig. 3(a), the resonance frequencies of measurement and simulation, as well as the frequency response to the lower and higher frequencies of the peak, agree very well within the limits of the measurement accuracy.Due to the uniform behavior of the measurement over a bandwidth of more than 140 GHz, the dielectric loss tangent tan(δ) = 0.002 according to the data sheet was kept constant within the scope of this LCP qualification and suitability study.The extracted frequency dependent relative permittivity ε r is ε r, pana = 2.94 ± 0.04 and is shown in Fig. 3(b).As indicated, the variations over frequency are minor.Furthermore, the data sheet value is plotted.The value extracted using our method is lower than the value given in the data sheet.The data sheet value was obtained using a cavity resonance method at 10 GHz.A direct comparison of the two methods at 10 GHz is not possible because no resonance peak occurs at 10 GHz within our characterization, but the first peak occurs at 20 GHz.However, the main focus of this characterization is to investigate the broadband complex permittivity behavior of the foil to verify its suitability for mmW applications.Due to the minor frequency dependency of ε r and the good correspondence of the measured and simulated frequency responses, this LCP mmW suitability study succeeds.Due to the very good agreement between the measurement and the simulation of the Beatty standard as well as the interconnect measurements (see Section IV), we used the ε r that we extracted using our method to design and optimize the interconnect.Furthermore, ε r, pana extracted with our method corresponds with the data provided in [7] and [14] at similar frequencies up to 170 GHz.In addition, we included the extracted surface roughness of the alumina and foil substrate in the interconnect simulation.

C. INTERCONNECT DESIGN
The flip-chip assembly is designed in three steps: (1) design of the CPWG on the alumina, (2) design of the transition from the alumina to the foil, and (3) design of the CPW on the foil.As already shown and discussed in [12] and [13], a broadband mmW-transparent interconnect with minimum reflections and maximum transmission can only be achieved if the EM field discontinuities are minimized along the transition.This includes keeping the EM field distribution as constant as possible along the entire transition to achieve the highest field conformity.Thus, the same reference impedance across the transition is ensured.In addition, the transition is designed to be compact, so that no geometric length is in the wavelength range and, thus, exhibits band-limited behavior.In the following sections the necessary transmission and transition designs are discussed in detail.

1) CPWG DESIGN ON ALUMINA
The main advantage of CPWG is the close spacing of signalto-ground traces, which ensures a locally concentrated and, thus, controlled field distribution on the high-permittivity alumina substrate.Therefore, the field leakage that could radiate parasitically at transmission line discontinuities is minimized.
The power flow and the EM distribution on the alumina CPWG are indicated in Fig. 4(a).CPWG has the advantage of having both signal and ground layers, that the foil interconnect substrate can contact, at the top of the alumina substrate.Especially for the proposed foil interconnect with several 100 μm length an uninterrupted and close ground reference next to the signal trace is essential to keep the reference impedance constant and to enable the proposed mmW-transparent interconnect functionality.In addition, dimensions such as signal width and signal-to-ground spacing are designed to be reasonably implemented in current MMIC technology.Thus, the design can be easily transferred to semiconductor processes in future interconnect designs.The CPWG signal width and the gap dimensions are shown in Fig. 5(a) and summarized in Table 1.

2) CPWG TO CPW TRANSITION DESIGN
The transition between the alumina substrate and the interconnect foil is key to optimize transition that minimizes EM discontinuities.The goal of the transition optimization was to maintain both the high field conformance and a consistent reference impedance of approximately 50 along the transition to minimize EM discontinuities.Simultaneously, the interconnect transition must be designed for manufacturability and contactability to ensure a robust and repeatable connection in the assembly.The overlap area of alumina and foil represents a sweet spot between manufacturability and robustness: on the one hand, sufficient overlap for reproducible joining, and on the other hand, enough compact for space-efficient integration of the interconnect interface on alumina or MMIC technology.To keep the impedance in the overlap area of alumina and foil as close as possible to 50 and, at the same time, to achieve high field conformity, the signal traces must be tapered (see magnified transition area in Fig. 5(a)).The power flow and the EM field distribution in the transition area are indicated in Fig. 4(b).To prevent any effect on line impedance due to the foil's dielectric properties on the alumina CPWG transmission line, the alumina's signal trace was tapered and the signal-to-GND gap widened.In addition, the CPWG signal width on alumina is wide enough to allow the flip-chip bonder to reproducibly place the contact bumps (see Fig. 1 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.for ground connection have a diameter of 40 μm and a centerto-center spacing of 70 μm.A rectangular contact bump for signal connection with a width of 30 μm and a length of 100 μm was used to ensure proper signal trace contacting within the overlap area.As described, the taper length y sig, taper was set to allow for reproducible joining of foil and alumina and, simultaneously, the best possible mmW performance.The alumina CPWG and foil CPW taper geometries, such as width, length, and signal-to-GND gap are identical (see Fig. 5(b) and Table 1, respectively).Thus, an alumina-to-foil interface has been developed that can be easily transferred to MMIC-to-foil technology because of similar transmission line dimensions and interface space requirements of alumina and MMIC technology.

3) CPW DESIGN ON THE FOIL
A coplanar waveguide transmission line is used on the foil.
The signal width has to be widened to enable a reference impedance close to 50 within the CPW on the foil.To keep the complexity of the foil manufacturing low, CPW was used instead of CPWG.This eliminates the need for vias and backside metallization on the foil.In CPW, the GND is next to the signal on foil, so no GND reference to the alumina substrate or to the assembly carrier is required.A narrow CPW gap x gap, cpw was designed, on the one hand, to realize 50 impedance, and, on the other hand, to transmit the EM field strongly concentrated within the signal-to-GND gap.This reduces the field leakage and prevents coupling into underlying circuits or parasitic radiation.Therefore, a robust, low-loss interconnect with minimized parasitic radiation is realized, which will be discussed further in Section II-D.The CPW length y foil exceeds 600 μm to demonstrate the interconnect's ability to bridge even much larger gaps between MMICs/mmW substrates.The interconnect can also be much shorter with no loss of performance.The power flow and the EM distribution on foil CPW are indicated in Fig. 4(c).In total, Fig. 4 shows the successive EM field distributions in different sectional planes, including the power flow along the entire structure.Due to the optimized signal routing within the CPWG, transition, and CPW a high EM field conformity with minimized discontinuities is achieved.

D. STUDY OF ASSEMBLY TOLERANCES AND PARASITIC RADIATION
The interconnect technology presented is intended to connect different mmW building blocks in a heterogeneous system design, thus enabling an entire system.The interconnect should be as mmW-transparent and low-loss as possible, to make the introduced discontinuity as low as possible, and the parasitic radiation at the signal transition must be minimized.In addition, it is even more crucial for the interconnect to be robust enough to be placed reproducibly within the scope of the assembly tolerances, without any major rejects.As mentioned in Section II-C, during the design, attention was paid to having a constant and close ground connection next to the signal trace along the entire assembly.Parasitic modes, especially parallel plate modes at the transition, can be suppressed by a tight ground connection next to the signal trace.To demonstrate the robustness of the proposed interconnect solution, a simulation study was conducted, in which a lateral offset, indicating a lateral assembly tolerance, was introduced.The effect of this lateral displacement is shown by the reflection and transmission coefficients in Fig. 6.Moreover, the inset in Fig. 6(b) illustrates the lateral offset in the simulation assembly.As proposed in [12], a return loss of 30dB in simulation allows for a sufficient margin for assembly tolerances.Thus, a lateral displacement of up to ±20 μ m without significant degeneration in performance (see blue ellipse in Fig. 6(a)) demonstrates the robustness of the interconnect solution regarding assembly tolerances.Even considering the maximum lateral offset, the transmission performance was not significantly degraded at frequencies above 120 GHz (see Fig. 6(b)).Moreover, the presented results show that no power is coupled into parasitic modes, which would be indicated by local dips in the transmission over frequency.In addition, the transmission behavior is not significantly affected by bending the flexible foil substrate when connecting two substrates with different heights.In simulation studies, height differences of up to 100 μm could be bridged without loss in performance.
In addition, a power loss analysis was performed to analyze the percentages of parasitic radiation relative to the metallic and dielectric losses.In CST Microwave Studio, the power at a waveguide port can be divided into two categories in the 1D results: accepted power, which is absorbed by the structure, and outgoing power, which is either reflected back or, in this case, mainly transmitted via the interconnect to the receiving waveguide port.The accepted power is divided either into losses in dielectrics, metals or into radiated power.The ratio of this power analysis is given as a percentage of the stimulated power and is shown in Fig. 7. Due to the CPWG feeding line length of 3mm in total and the foil interconnect length of more than 900 μm, the metallic loss is the main loss mechanism.The parasitic radiated power remains below 2% for all observed lateral offsets over the entire bandwidth of more than 130 GHz, thus being negligible and confirming an interconnect design with minimal parasitic radiation.At frequencies around 60 GHz there is a slight increase in radiation.This occurs in the overlap area of alumina and foil, but remains below 1% and is therefore negligible, but could be further reduced in upcoming work with CPWG transmission line on foil, which allows even better focused mmW waveguides on foil with lateral via fences and backside metallization and prevents parasitic radiation.

III. ASSEMBLY AND FLIP-CHIP PROCESS
In this paper a Finetech flip-chip bonding tool is used for the assembly.First, the alumina substrates are placed and precisely aligned with each other on the heating plate of the flip-chip bonder.Alignment marks, as indicated in Fig. 1(b), are used for the optical placement.Second, the LCP interconnect foil is picked up with a placement tool using a vacuum.
A layer of adhesive is applied onto the alumina substrate in the alumina-foil overlap area.The LCP foil is placed on and joint to the aluminum substrates.Within the flip-chip bonding, a lateral offset of the foil and alumina substrate below 5 μm can be achieved within the scope of this work.The assembled interconnection is placed on the carrier board with custom-built micro-manipulators.The alignment marks on the alumina (indicated in Fig. 1(b)) are used to place of the assembly on the carrier.The alignment precision of the alumina substrates on the carrier is less than ± 5 μm.

IV. MEASUREMENT SETUP AND CHARACTERIZATION OF FLIP-CHIP INTERCONNECT A. MEASUREMENT SETUP
The measurement setup for the characterization from 2 GHz up to 110 GHz is shown in Fig. 8.A network analyzer, frequency extender with 1mm coaxial cable, and GSG probes with 100 μm pitch are used.A second measurement setup with frequency extenders from 110 GHz up to 170 GHz and waveguide GSG probes with 100 μm pitch are used for the measurement from 110 GHz up to 135 GHz (shown in [12]).This two-stage measurement setup allows for the characterization of the proposed interconnect over a bandwidth of more than 130 GHz.In both setups, TRL calibration kit on alumina is used to achieve a reference plane on CPWG.Moreover, additional CPWG lines are manufactured next to the custom-made calibration kit for the extraction of the attenuation coefficient α using a multi line approach.

B. CHARACTERIZATION OF THE FLIP-CHIP INTERCONNECT
The measured and simulated reflection and transmission coefficients are compared in Fig. 9.The measured return loss (RL) is above 20dB over a bandwidth of more than 130 GHz, which confirms the achievement of a flip-chip interconnect assembly that causes minimum reflections.The measured |s 11 | and |s 22 | are approximately equal, which increases the measurement reliability due to the symmetrical measurement behavior [12].Moreover, the simulated and measured RL are in good agreement.Due to the excellent RL behavior in the simulation (RL >30dB), there was enough margin for achieving very good RL performance in the measurement despite the assembly tolerances, which justifies the optimization strategy.Fig. 9(b) compares the measured and simulated insertion loss (IL).As indicated in the figure's inset, the reference plane of this IL measurement is at the CPWG reference plane after TRL calibration, due to which the feed line losses are included.Because of the precise simulation of the conductor surface roughness (R q = 0.21 μm) simulation and measurement are in very good agreement.The interconnect does not introduce any additional frequency-dependent transmission behavior; on the contrary: only the attenuation increases toward high frequencies, as expected.
To extract the IL of the foil interconnect itself, the CPWG feed line losses have to be excluded.Thus, using a multi line method with eigenvalue extraction, the frequency-dependent attenuation coefficient α of the CPWG transmission line was extracted.The difference in the line length is above 5mm to minimize probe placement errors [24].The α is shown in Fig. 10(a), including a plot of the polynomial fit of the measured data in a least-square sense with error estimation for better data visualization and further data processing.Also shown is the extracted α of the simulation setup, including the surface roughness.High agreement of simulated and measured attenuation coefficients indicates that the loss phenomena have been properly considered and modeled in the simulation.The data are used to de-embed the interconnect IL, as shown in Fig. 10(b).A measured de-embedded IL of less than 0.7dB of the 640 μm-long foil interconnect represents a low-loss flexible foil interconnection.This de-embedded IL includes the double transition and the length of the foil itself.De-embedding the IL of the CPW foil section presents an isolated IL of less than 0.3dB at 135 GHz per transition, which further demonstrates the low-loss characteristics of the proposed interconnect assembly.
Several samples were assembled to investigate the robustness of the flip-chip interconnect to assembly tolerances.The reflection and transmission characteristics are shown in Fig. 11.All the modules exhibit a return loss of above 20dB and an insertion loss of less than 1.3dB (including the feed network).In particular, the spread of the measurement results across all the samples demonstrates the robustness of the interconnect and the insensitivity of the design to assembly tolerances.

C. FLIP-CHIP VERSUS BOND-WIRE INTERCONNECT
To demonstrate the necessity of the proposed flip-chip assembly technique for longer interconnects, the flip-chip assembly was compared with a bond-wire interconnect.[12] has shown that through proper loop and substrate arrangement, compact bond-wire interconnects with excellent broadband mmW performance can be achieved.However, if a longer distance has to be bridged between two mmW building blocks, this performance cannot be maintained, so alternative concepts, such as the presented flip-chip foil have to be applied.An experiment was performed to design a bond-wire interconnect that should bridge a substrate gap of up to 300 μm with maximal RL (RL > 20dB) and minimal IL over the entire bandwidth.The bond loop was chosen to be as small as possible (30 μm) to reduce the inductive behavior of the bond-wire.The combination of substrate gap and bond loop results in a bond-wire length of about 400 μm, thus shorter than the foil interconnect.The reference plane and the length of the CPWG feeds on alumina for the bond-wire setup are identical to those of the flip-chip assembly for the highest level of comparability.
The assembly setup, its cross-section with the bond loop specification and the measurement results are shown in Fig. 12.Three bonds are used in parallel to reduce the wire inductance of the signal trace.Furthermore, four GND bonds are assembled on each side of the signal bonds for highest EM-field conformity.The bond-wire was designed in the same manner as proposed in [12] for highest bond-wire interconnect performance for ultra-broadband mmW applications.
The return loss decreases significantly above 60 GHz, due to the increased inductive discontinuity at higher frequencies that the bond-wires introduce (Fig. 12(c)).A similar behavior can be observed for the IL (Fig. 12(d)); the bond-wire and flip-chip setup, have similar IL up to this frequency.Above 60 GHz, the RL decreases below 20dB and simultaneously, the losses increase significantly.This emphasizes the need to optimize the interconnect for the lowest possible reflections in order to maximize transmission.At 100 GHz the IL of the bond-wire interface is almost twice that of the flip-chip foil, so the motivation for the proposed solution is sufficiently evident, and, further bond-wire characterization at higher frequencies was not pursued.

V. CONCLUSION AND OUTLOOK
An ultra-broadband flip-chip interconnect with more than 130 GHz bandwidth for enabling mmW-transparent interconnections between two alumina substrates is demonstrated.Due to the flexible LCP foil substrate the interconnect can also be used if the substrate height of the two sub-modules differ.A measured return loss of 20dB across the whole bandwidth and an optimized flip-chip transition design towards highest field conformity results in a de-embedded measured insertion loss below 0.3dB.The measured results are summarized and compared with previous reported interconnects in Table 2.
Due to the exceptional interconnect performance, the added loss caused by the interconnect itself does not need to be factored into the link budget for heterogeneous system design.It has been shown by measurement that the proposed interconnect is insensitive to lateral assembly displacements during flip-chip bonding.In addition, the interconnect has a minimum of parasitic radiation.Its interface was also optimized in a space-efficient manner to make it easily transferable to MMIC design, which makes the interconnect useful not only for substrate-to-substrate interconnection, but also for substrate-to-MMIC interconnection.
To achieve more compact and shielded interconnects, further work will focus on CPWG as an alternative to CPW design on foil.This enables even better focused mmW waveguides with lateral via fences and backside metallization on foil, and prevent parasitic radiation.This allows even longer flexible foil interconnect substrates beyond 1mm length to be realized.The focus of upcoming work will be on manufacturability and via placement to realize flexible CPWG foil interconnects.

FIGURE 1 .
FIGURE 1.(a) Cross-section layer stackup of the flip-chip foil interconnect with geometric dimensions (not to scale).(b) Top view of the foil flip-chip interconnect assembly with CPWG alumina feedlines and alignment marks for placement.(c) Cross-connection within the carrier groove, enabling system design flexibility.

FIGURE 2 .
FIGURE 2. (a) Betty-Standard on foil with feeding line and GSG probe pads and (b) electric field distribution at 140 GHz.

FIGURE 3 .
FIGURE 3. (a) Measured and simulated reflection magnitudes with the respective relative permittivity values at each resonance frequency.(b) Extracted relative permittivity ε r of the used foil substrate.

FIGURE 4 .
FIGURE 4. Power flow and electromagnetic field distribution within (a) CPWG, (b) the transition, and (c) CPW on foil.The green color indicates high and blue low power intensity.
(a)) integrated on the CPW foil on the CPWG signal trace.The contact bumps 408 VOLUME 4, NO. 3, JULY 2024

FIGURE 5 .
FIGURE 5. (a) Back-to-back simulation setup with magnification of transition.(b) Geometries of the foil interconnect and the taper section.

FIGURE 6 .
FIGURE 6.(a) Simulated reflection and (b) simulated transmission for different lateral flip-chip alignment offsets.

FIGURE 7 .
FIGURE 7. Power dissipation analysis.Parasitic radiation of the proposed interconnect is negligible.

FIGURE
FIGURE Simulated and measured (a) reflection and (b) transmission of the back-to-back flip-chip interconnect (including the feed line loss).

FIGURE 10 .
FIGURE 10.(a) Multi line method for extraction of attenuation coefficient and (b) de-embedded insertion loss of the back-to-back foil interconnect (including the 640 μm-long foil).

FIGURE 11 .
FIGURE 11.(a) Reflection and (b) transmission of multiple assembled interconnect modules.

FIGURE 12 .
FIGURE 12. (a) Microscope top view of the bond-wire interconnect assembly.(b) Cross section of simulation setup for the bond loop specification, comparison of (c) measured reflection and (d) measured transmission of two bond-wire interconnects and flip-chip assembly.