Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Easy inter-connection is a crucial advantage of the single-chip power ICs, which makes power devices with multiple ports easy to improve carrier controllability without increasing process difficulty. Electrical characteristics of the power devices get further improved thanks to the advanced carrier controllability. In this paper, a silicon-on-isolator lateral IGBT (SOI-LIGBT) featured four hybrid gates is proposed to obtain outstanding carrier controllability in turn-on, turn-off and short-circuit conditions for the first time. Four hybrid gates include three planar gates (G1, G2 and G3) and a trench gate (G4), of which G3 and G4 are grounded gate to lower saturation current and suppress latch up. Low turn-off time <inline-formula> <tex-math notation="LaTeX">$(t_{OFF})$ </tex-math></inline-formula>, di/dt and improved short-circuit withstanding capability are obtained through providing different input signals to these gates. In the turn-on, G2 is pre-charged to a stable voltage equal to gate voltage <inline-formula> <tex-math notation="LaTeX">$(V_{G1})$ </tex-math></inline-formula> to suppress the high di/dt before <inline-formula> <tex-math notation="LaTeX">$V_{G1}$ </tex-math></inline-formula> starts to rise. In the turn-off, a P-type inversion is induced by the negative voltage of <inline-formula> <tex-math notation="LaTeX">${\mathrm{ G}}_{2}~(V_{G2})$ </tex-math></inline-formula>, which provides a low-resistance hole current path to extract the stored holes. In the short-circuit condition, G3 and G4 are both shorted to the ground to lower the saturation current and suppress the activation of parasitic NPN transistor, resulting in an improved short-circuit withstanding time <inline-formula> <tex-math notation="LaTeX">$(t_{SC})$ </tex-math></inline-formula>. Compared with the conventional SOI-LIGBT, <inline-formula> <tex-math notation="LaTeX">$t_{OFF}$ </tex-math></inline-formula> and di/dt are reduced by 43.6% and 53.08%, and <inline-formula> <tex-math notation="LaTeX">$t_{SC}$ </tex-math></inline-formula> is prolonged from <inline-formula> <tex-math notation="LaTeX">$3.04\mu \text{s}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$8.89\mu \text{s}$ </tex-math></inline-formula> at DC bus voltage of 400V.


I. INTRODUCTION
Single-chip power IC is popular for its significant advantage of easy inter-connection [1], [2], [3]. Many power devices featured multiple ports or integrating MOS and diodes can be manufactured to obtain better carrier controllability. Advanced carrier controllability, such as adjusting local carrier concentration, changing current path and enhancing or suppressing the effect of moving carriers, is the root of improving electric characteristics in power stage devices.
Recent years, many novel IGBTs with multiple ports or integrated devices have been reported to improve the carrier controllability in different transients. In the turn-on transient, better dv/dt or di/dt controllability can be achieved by controlling the hole concentration beside gate polysilicon [4], [5] or suppressing the effect of displacement current on gate voltage [6], [7]. In the turn-off transient, fast electron/hole extraction or decreasing stored carriers is crucial to achieve low turn-off loss (E OFF ). Short anode technology [8], [9] is a common method to accelerate the electron extraction by adopting a N+ region in the collector side, however, resulting in a snapback. Then, a small-scale circuit composed of MOSFETs or diodes is added to further control the extraction of carriers without snapback in [9], [10], [11]. SOI-LIGBTs with inserted dual or triple deep oxide trenches in the N-drift are reported in [12], [13], [14] to achieve a better trade-off between on-state voltage (V ON ) and E OFF by enhancing the conductivity modulation in the on-state and assisting in voltage sustaining in the off-state. In the short-circuit condition, the most failures of devices are attributed to the activation of parasitic transistor, and adjusting hole current path is an efficiency way to suppress the latch up. The most effective approach to prevent the latch up is lowering the saturation current (Isat) through employing series diodes or MOSs to extract holes in drift region [15], [16], [17].
In this paper, a novel four gates SOI-LIGBT with outstanding carrier controllability is proposed and investigated. In Section II, the structure and main key design parameters of the proposed SOI-LIGBT are illustrated. The mechanism of carrier controllability in the turn-on, turn-off and the shortcircuit conditions are discussed through TCAD simulations. In Section III, the improvement of electrical characteristics in the proposed SOI-LIGBT is verified through the double-pulse switching and short-circuit measurements.

II. STRUCTURE AND MECHANISM
The cross-section view and the key design parameters of the proposed SOI-LIGBT are shown in Fig. 1 (a). Four hybrid gates, three planar gates (G 1 , G 2 , G 3 ) and a trench gate (G 4 ), are adopted in the proposed SOI-LIGBT. Three planar gates are formed by one-step etching after the deposition of polysilicon. G 1 is responsible for the formation of the inversion channel. G 2 -G 4 play a role of improving carrier controllability, and G 4 also acts as an isolation trench. The length of G 1 , G 2 , and G 3 is L 1 , L 2 and L 3 , respectively. G 4 is filled by the polysilicon that is surrounded by 80nmthick sidewall oxide, and the polysilicon is connected to the emitter by interconnection metal. The distance from right side of G 4 to the left-side bird's beak is TO. The thickness and the length of the N-drift region are 18µm and 45µm, respectively, and the thickness of the BOX is 3.5µm. As shown in Fig. 1 (b), a conventional SOI-LIGBT with only one planar gate is fabricated for comparation. Fig. 2 (a) shows the schematic circuit for double pulse clamped inductive switching measurement and simulation. The input signals are transmitted to G 1 and G 2 through series resistors R 1 and R 2 (R 1 >>R 2 ), respectively. In this work, R 1 is set as 200?, and the R 2 is set as 1/100 of R 1 . G 3 and G 4 are shorted to the emitter directly. Inductive load of 5mH is used and a fast recovery diode is anti-parallel to the inductance as freewheeling diode. As shown in Fig. 2 (b), two different input signals (V G1 and V G2 ) of double pulse are applied to G 1 and G 2 . V G1 and V G2 have the same positive voltage of 15V, and the low-level voltages of V G1 and V G2 are 0V and ∼ −5V, respectively. Moreover, V G1 is delayed by ∼1µs than V G2 .
In the turn-on transient, for conventional SOI-LIGBT, holes injecting from collector will elevate the electric potential in the accumulation region (shown in Fig. 1 (a)), and the displacement current composed of these holes can overcharge gate, resulting in high di/dt and gate overshoot (in Fig. 3 (a)) [7]. As shown in Fig. 3 (b), the hole density in the accumulation region in the turn-on transient decreases significantly when G 2 is pre-charged. Pre-charged G 2 has constant electric potential of 15V in advance, which can repel hole. In addition, G 2 is the part most seriously affected by holes in the accumulation region. Owing to the nonconnection between G 1 and G 2 (shown in Fig. 1 (a)), G 1 is protected from the impact of G 2 . Therefore, the impact of hole displacement current on G 1 is further weakened. To further verify the repulsion of G 2 to hole, G 2 is shorted to G 1 for comparation in TCAD simulation. Compared with SOI-LIGBT with pre-charged G 2 , repulsion of G 2 to hole is weakened severely when G 1 and G 2 are shorted (red line).  Fig. 3 (a)). Moreover, whether G 3 and G 4 are grounded (green line) or connected to G 1 (blue line) has no effect on the repulsion of G 2 to hole of G 2 .
In the turn-off transient, V G2 falls firstly to negative voltage of −5V, and then G 1 starts to turn off as shown in Fig. 2 (b). Stored holes and electrons in the drift region are   extracted to the emitter and the collector electrodes, respectively. As shown in Fig. 4 (a), most of holes are extracted from along path1. Fig. 4 (b) illustrates the equivalent resistance distribution model and hole density distribution in the turn-off transient. The equivalent resistance of path1 composes of channel resistance (R ch ), accumulation region resistance (R acc ), drift resistance (R drift ) and buffer resistance (R buffer ). Negative V G2 induces a hole accumulation layer in the accumulation region, which reduces R acc significantly. The hole accumulation layer provides a low-resistance hole current path (path1), resulting in a reduced t OFF .
As shown in Fig. 5 (a) and Fig. 5 (b), G 3 and G 4 are shorted to the ground in the short-circuit measurement and 290 VOLUME 11, 2023  simulation. The injection effect in the accumulation region is weakened considerably due to the grounded G 3 . The Isat of the proposed SOI-LIGBT is lower than that of the conventional SOI-LIGBT when G 3 is grounded. In addition, holes from P+ collector are attracted to the grounded G 4 in the short-circuit condition as shown in Fig. 6. More holes flow along G 4 at same current rating, which can suppress the activation of parasitic NPN transistor. However, the attraction of G 4 to holes is greatly weakened when G 4 is connected to G 1 or floating (conventional SOI-LIGBT). Compared with the conventional SOI-LIGBT, the proposed SOI-LIGBT with grounded G 3 and G 4 obtains a significantly improved short-circuit withstanding capability.

III. MEASUREMENT RESULTS
In order to verify the improved carrier controllability of the proposed SOI-LIGBT with hybrid gates, devices are fabricated at TO = 13µm, L 1 = 3µm, L 2 = 1.1µm, and L 3 = 0.9µm on the 550V SOI Bipolar-CMOS-DMOS-IGBT platform, in which SOI-LIGBT and driver circuits can be integrated in a single chip. Photos of fabricated proposed and conventional SOI-LIGBTs are shown in Fig. 7 (a) and Fig. 7 (b). The SEM photo of four gates in the proposed SOI-LIGBT is shown in Fig. 7(c). Three planar gates are connected to pads through interconnection metal, respectively. G 4 is connected to emitter directly. The total device width of fabricated samples is 3600µm. In Fig. 8, a special printed circuit board is designed for double pulse clamped inductive switching measurement and short-circuit measurement. Two input signals provided by a signal generator (Tektronix AFG3102C) are applied to G 1 and G 2 . In addition, the driver chip to drive G 2 supports negative voltage, and the negative voltage is provided by a Keithley source meter. A commercial fast recovery diode is used as freewheeling diode in the double pulse clamped inductive switching measurement, while shorted in the shortcircuit tests. After each measurement, a fresh sample is used in the next measurement. It should be pointed out that driver circuits used in the printed circuit board and SOI-LIGBT can be integrated in a single chip, and thus the gate input signals can be provided easily.
As shown in Fig. 9 (a), the starting positions of avalanche of the conventional and proposed SOI-LIGBTs both locate at the bottom of the collector side, and the breakdown point is indeed far from hybrid gates in the proposed SOI-LIGBT. Thus, the conventional and proposed SOI-LIGBTs have the similar impact ionization rate distributions and breakdown voltage (BV). Fig. 9 (b) shows the measured and simulated off-state I-V curves of fabricated devices at the room temperature. Adopting separated gates in the proposed SOI-LIGBT has no effect on the BV. The proposed and the conventional devices obtain the same BV of 557V. Fig. 9 (c) shows the measured and simulated on-state I-V curves. The electron accumulation effect is weakened at V G3 = 0V, which results in a low Isat and an increased V ON .
Input capacitance (C iss ) and reverse transfer capacitance (C rss ) of the conventional and the proposed SOI-LIGBTs are measured at frequency of 1MHz. As shown in Fig. 10, the proposed SOI-LIGBT obtains reduced C iss and C rss at V CE = 280V thanks to the split gates. Fig. 11 (a) shows the definition of turn-off time (t OFF ), maximum reverse recovery current (I rrm ) and di/dt. The proposed and the conventional devices begin to turn off at V DC = 280V and I CE0 = 0.5A. t OFF is defined as the phase from the 10% of V DC (28 V) to the 10% of I CE0 (0.05 A). I rrm is defined as the difference between I CE peak and I CE0 . di/dt is defined as the current change per unit time. Curves of the conventional and the proposed SOI-LIGBTs in the turn-on transient are shown in Fig. 11 (b). Thanks to the separated gates and pre-charged G 2 , the effect of the displacement current composed of the holes in the accumulation region is significantly weakened in the proposed SOI-LIGBT. The proposed device exhibits a decreased di/dt and I rrm . Compared with the conventional device, the proposed device obtains 53.08% reductions in di/dt and 23.8% reduction in I rrm . Fig. 11 (c) shows the turn-off curves of the proposed and the conventional devices. The proposed device obtains a faster turn-off speed than the conventional device thanks to the low-resistance hole extraction path. As a result, the proposed device achieves 43.6% decrease in t OFF and 41.8% reduction in E OFF in comparison with the conventional device.
The fabricated devices are packaged to compare shortcircuit withstanding capability. As shown in Fig. 5 (a), the packaged devices are measured with no load, thus the DC bus voltage (400V) is applied to the collector directly. The connections of hybrid gates are shown in Fig. 5 (b). Fig. 12 shows the short-circuit curves of the conventional and the proposed devices. The proposed devices are measured at the conditions of G 2 is pre-charged (w/ pre-charged G 2 ) and shorted to G 1 (w/o pre-charged G 2 ). Short-circuit withstanding times (t SC ) of the proposed device measured with and without pre-charged G 2 are improved to 8.46µs and 8.89µs, respectively. In summary, integrated platform can further improve the electric characteristics of a single power device by integrating circuits or other devices easily.

IV. CONCLUSION
Integration makes multi-port devices easy to control and improve carrier controllability. A novel structure with hybrid gates is proposed in this paper. Carrier controllability is obviously improved in turn-on, turn-off and short-circuit conditions thanks to the separated gates and different gate input signals. Compared with the conventional SOI-LIGBT, the proposed SOI-LIGBT obtains 53.08% reduction in di/dt, 43.6% reduction in t OFF and 225% improvement in t SC . In addition, adjusting the length of G 1 , G 2 and G 3 or the gate input signals may further improve the transient electric characteristics in different conditions, and it will be investigated in our future work.