Demonstration of HfO2-Based Gate Dielectric With ~0.8-nm Equivalent Oxide Thickness on Si0.8Ge0.2 by Trimethylaluminum Pre-Treatment and Al Scavenger

We disclosed HfO2-based dielectric of superb electrical properties on p-type Si0.8Ge0.2 substrate using an interfacial layer (IL) formed by trimethylaluminum (TMA) pre-treatment and Al scavenger. Our results revealed that the interface trap density (Dit) value and the gate leakage current (JG) could be improved about 60 times and 100 times by tuning the gate electrode composition without sacrificing equivalent oxide thickness (EOT) performance. The mechanism underlying the <inline-formula> <tex-math notation="LaTeX">${\mathrm{ D}}_{\mathrm{ it}}$ </tex-math></inline-formula> improvement of the SiGe metal-oxide-semiconductor capacitors (MOSCAPs) might be owing to the Al metal scavenger and the minimization of the oxygen atoms diffusing to the high-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula>/SiGe IL, verified by x-ray photoelectron spectroscopy (XPS) analyses. In addition, the hysteresis levels of SiGe capacitors with various gate electrodes were measured to find out the optimized configuration of metal electrodes. This work demonstrated the Al scavenger effect from the aspects of both material and electrical properties and achieved an impressive EOT value of <inline-formula> <tex-math notation="LaTeX">$\sim 0.8$ </tex-math></inline-formula>nm for the capacitors fabricated on the SiGe substrate.


I. INTRODUCTION
As one of the high-mobility materials, SiGe is regarded as the most promising candidate for 3nm technology node and beyond, which possesses the lowest lattice mismatch with Si [1], [2], [3], [4], [5]. While different from Si substrates, SiGe substrates need a specific interface treatment to solve their interface issue, easily showing high interface trap density (D it ) due to surface Si and Ge atoms [6], [7], [8], [9], [10]. Therefore, our group studied the composition and quality of the Si 0.5 Ge 0.5 interfacial layer (IL) by tuning the various IL annealing temperatures and fabricated the Si 0.8 Ge 0.2 p-MOSFET with TMA pre-doping and NH 3 plasma IL treatment [11], [12]. The former research shows that the optimized IL annealing temperature might be 800 • C, and the 99.8% silicon oxide in IL could be obtained without relaxation and dislocation. The latter demonstrates that the IL of the SiGe device composed of Si-N and Al-O bonds could be the high-quality interface, exhibiting the low gate leakage current and high I on /I off ratio. However, IL thermal treatment and nitridation could not reach the equivalent oxide thickness (EOT) scaling less than 1 nm due to the thicker low-κ IL. As a result, to yield more drive current enhancement, the SiGe IL formation with low EOT and controlled leakage is highly desirable [13]. Recently, the SiGe gate stack composed of trimethylaluminum (TMA) interface treatment and in-situ high-dielectric Y 2 O 3 deposition was reported to demonstrate the EOT scaling down to 1 nm with ultralow D it , which could be attributed to the minimization of Ge-O bonds in SiGeO x ILs and the Y 2 O 3 thickness reduction [14], [15]. However, the EOT value needs to be improved to meet the International Roadmap for Devices and Systems (IRDS) targets [16]. Hence, the advanced SiGe gate stack utilizing the higher dielectric with low gate leakage current is urgently demanded.
On the other hand, our previous research reported that a high-quality SiGe interface could be achieved by inserting the barrier layer TiN metal and the oxygen-scavenging effect of the upper-metal Al [17]. Moreover, another group also demonstrates low-EOT performance through Ti scavenging effect [18]. However, the solid evidence of several studies about the high-performance according to the scavenging effect is deficient, which might be due to the complex analyses of the gate stack with metal-capped.
In this study, we successfully demonstrated the Al scavenging effect on the electrical characteristics of atomic layer deposition (ALD) HfO 2 -based Si 0.8 Ge 0.2 metal-oxidesemiconductor capacitors (MOSCAPs) using TMA pretreatment for IL formation [14], [17]. We further fabricated SiGe capacitors with various gate electrode compositions to investigate the oxygen-scavenging process of the SiGe gate stacks due to the Al scavenging effect. In addition, xray photoelectron spectroscopy (XPS) would be employed to confirm the SiGe interface transition during various capping conditions. The electrical results revealed that the SiGe capacitor with TMA IL treatment and Al capping exhibited an ultralow EOT value of ∼0.8 nm with a good gate leakage current.

II. EXPERIMENTAL DETAILS A. SIGE CAPACITORS FABRICATION
The experiments involved a 100-nm-thick in-situ boron-doped Si 0.8 Ge 0.2 layer that was epitaxially grown on (100) orientation p-Si wafer with a doping concentration of 1×10 15 cm −3 by low-pressure chemical vapor deposition (LPCVD, ASM Epsilon-2000 Reactor). After diluted HF eliminated the native oxides, the samples were immediately transferred to an ALD system. The SiGe gate stacks, including different IL and HfO 2 thicknesses, were established by various cycle numbers of TMA pre-treatment followed by cyclic ALD with tetrakis(ethylmethylamino)hafnium and H 2 O as precursors. A 50-nm-thick TiN was sputtered to form the reference electrode afterward. Moreover, to comprehensively investigate the effect of Al scavenger on the underneath SiGe gate stack, various metal compositions of Al and TiN were sputtered. Furthermore, a backside metal contact (Ti/Al) was formed to minimize the backside contact resistance. Finally, the followup post-metal annealing (PMA) at 300 • C for 1 min in N 2 ambient was performed for all SiGe samples.

B. SIGE CAPACITORS CHARACTERIZATION
The SiGe capacitors' multi-frequency capacitance-voltage (C-V) characterizations were measured at room temperature using an Agilent 4284A LCR meter. The hysteresis ( V FB ) was defined as the difference of Flat-band voltage (V FB ) extracted from the C-V curves measured at 500 kHz with opposite sweeping directions. Next, the D it value was extracted by the conductance method at a temperature of 300 K [19]. Finally, the EOT value was calculated using the Schred simulator on the nanoHUB website [20], which considers the quantum confinement effect in the SiGe substrate.

C. XPS SAMPLES PREPARATION
To investigate the effect of Al scavenger on the material composition of the underneath SiGe gate stack, XPS analyses were performed with an X-ray source of Al Kα (1486.6 eV). Moreover, to focus on the SiGe gate stacks, the XPS samples were soaked in APM (NH 4 OH: H 2 O 2 : H 2 O = 1:2:5) at room temperature for 25 minutes to remove the TiN metal and the Al metal above it [8].

A. OXYGEN-SCAVENGING PROCESS OF AL METAL SCAVENGER
Figs. 1 (a)-(d) illustrate the multi-frequency C-V characteristics and the schematic diagrams of the Si 0.8 Ge 0.2 MOS capacitors with different gate stacks and gate electrodes. For clarity, the samples were named by abbreviation according to their structures, as in Table 1. The purpose of varying the gate electrode structure and gate stack was to investigate the oxygen scavenging process caused by the presence of Al metal. To study the effect of metal engineering on the underlying gate stack, TiN of 50nm and Al/TiN of 25nm/25nm were deposited on different samples by sputtering. Moreover, an additional 10-cycle H 2 O precursor was inserted in the deposition of the gate stacks in the THT and THTA cases during ALD to introduce more oxygen atoms. The extracted electrical parameters of SiGe capacitors are listed in Table 1, noting that all the samples were subjected to the PMA at 300 • C for 1 min in N 2 ambient.
We observed that, first, the cases with Al/TiN gate electrodes (TTA and THTA) showed smaller humps at the depletion region, exhibiting better interface quality obtained through the scavenging process; the TTA case exhibited a relatively low EOT value of less than 1nm and a smaller D it value of ∼3.8 x 10 12 cm −2 eV −1 . Second, the THTA case showed more significant frequency dispersion at the accumulation region, which might result from the series resistance effect due to the Al oxide formed on top of the TiN metal [21]. More significant frequency dispersion also proved that the oxygen atoms in the gate stack would be driven through the scavenging effect. In contrast, the TT and THT cases without Al capping displayed the individual humps at the depletion region, implying the TiN metal was unable to induce the oxygen scavenging process and the high-κ/SiGe interface quality was sensitive to the oxygen atoms.
In order to figure out when the oxygen scavenging occurred during our processing, PMA was skipped for the TT and TTA samples. Figs. 2 (a)-(b) illustrate the corresponding multi-frequency C-V characteristics of the Si 0.8 Ge 0.2 MOS capacitors. We clearly saw that the TT case without the PMA process depicted distinct frequency dispersion behavior in the C-V curves that the low-frequency (1 kHz) CV curve did not merge with other curves at the gate voltage of −1V to 0 V, indicating the worse interface quality. In addition, a higher D it value of ∼1.4 × 10 13 cm −2 eV −1 of the SiGe MOSCAP was obtained showing the interface deterioration during TiN sputtering [22]. On the other hand, as the Al/TiN was adopted, the SiGe interface could be slightly cured owing to the elimination of oxygen atoms at the highκ/SiGe interface by scavenging process [23] as shown in Fig. 2 (b). Upon PMA, the capacitors then revealed better frequency dispersion in the C-V curves and lower D it values, which might manifest that the scavenging does happen during the PMA process [24], [25].
In order to further investigate the scavenging effect from the perspective of the material interaction at the SiGe gate stack by the XPS analyses, the overlying metal must be removed without affecting the underlying high-dielectric. Therefore, the soaking in APM solution (NH 4 OH: H 2 O 2 : H 2 O = 1:2:5) at room temperature for 25 minutes was implemented to dispose of the TiN and Al metals. Fig. 3   displays the XPS spectra of O 1s and Hf 4f of the 30-cycle HfO 2 /10-cycle TMA-IL/Si 0.8 Ge 0.2 stack structures before and after soaking in the APM solution, which was employed to confirm whether or not the APM liquid would substantially affect the properties of the HfO 2 dielectric. The results confirmed that the HfO 2 dielectric was not detectably attacked after immersing in the APM solution for 25 minutes. Consequently, we applied this approach to remove the gate electrodes of the samples for the XPS analyses.
As mentioned above, the oxygen scavenging action caused by Al metal occurred through the PMA process. On purpose to have deep insight into the material interaction of the Al scavenging effect, the annealed and unannealed stack structures of the Al/TiN/30-cycle HfO 2 /10-cycle TMA-IL/Si 0.8 Ge 0.2 were used for the XPS analyses with removing the gate electrodes first by the APM solution; the condition for the annealed on was 300 • C PMA for 1 minute. Figs. 4 (a)-(d) depict the XPS spectra of the Si 2p, Al 2p, Hf 4f, and O 1s core levels [26], [27], [28]. In the Si 2p spectrum, higher binding energy and intensity of the SiO x signal were observed for the annealed sample due to the Si oxidation during the PMA process [29]. On the other hand, the peak height of AlO x was higher for the annealed sample, indicating that the Al-O bonds would form during the PMA process owing to the lowest Gibbs' free energy at the high-κ/SiGe interface [12]. It is worth mentioning that the XPS results of Hf 4f and O 1s did not demonstrate the apparent differences, as shown in Fig. 4 (c) and (d). Therefore, we supposed that the scavenging effect would only occur at the high-κ/SiGe interface.   SiGe IL and scale down the EOT value. Note that all the capacitors were annealed, and the composite upper-metal Al/TiN of 25nm/25 nm was applied. The SiGe capacitor with 2-cycle TMA IL pre-treatment exhibited the highest accumulation capacitance (C acc ), i.e., an EOT value of ∼0.9 nm, as presented in Fig. 5 (b). As the cycle number of TMA pretreatment increased, the EOT value increased, which might stem from thicker SiGe IL formation (2-TMA, 3-TMA, and 10-TMA). However, when 1-cycle TMA pre-treatment was adopted, the SiGe capacitor displayed a much lower C acc since we thought the IL formation reaction was incomplete since only a few Al atoms were present and the IL was prone to be mainly composed of a lower-κ dielectric, for example, resulting from Si-O and Ge-O bonds. However, this seemed beneficial to the D it since the capacitor with 1-cycle TMA pre-treatment showed the lowest D it value. As the cycle of TMA pre-treatment increased, the D it value became larger accordingly. The underlying reason for the variation of the D it performance was probably because more Ge dangling bonds were left as more Al-O bonds formed, the Al-induced increase in D it [15]. Therefore, considering both EOT and D it performances, 2-cycle TMA pre-treatment was thought to be the best IL pre-treatment condition.

B. ELECTRICAL CHARACTERISTICS OF SIGE MOSCAPS
In overview, through Al/TiN capping, the oxygen atoms in the SiGe gate stack might be gathered up through the Al scavenging effect, which resulted in the high-quality highκ/SiGe interface; and 2-cycle TMA pre-treatment would make the low-EOT SiGe gate stack. However, it was verified that during the PMA process, the gate electrode of Al/TiN might also form the Al-O layer to block the oxygen inward diffusion and leave the oxygen vacancies unfilled, which would lead to hysteresis and reliability issues [17]. The hysteresis width could be a criterion to determine the number of the slow oxide traps and interface traps of the SiGe gate stack. When the hysteresis is large, it is likely due to the fuzzy high-κ/SiGe interface or many oxygen vacancies; meanwhile, when the hysteresis is small, it may be due to oxygen vacancies filled with numerous oxygen atoms. Too many oxygen atoms might also induce the SiGe reoxidation and deteriorate D it performance [30].
Figs. 6 (a)-(e) illustrate the hysteresis widths of the capacitors subject to the scavenging effect with various gate electrode compositions. As seen in Fig. 6 (a), the capacitor with only sputtered TiN of 50nm displayed a hysteresis width of 0.07 V and V FB of 0.07 V in the forwarding sweep. While the Al capping metal was involved, the SiGe capacitors, in Figs. 6 (b)-(d), with the gate electrodes of Al/TiN of 25nm/40nm, 25nm/25nm, and 25nm/10nm showed larger hysteresis values, which might be owing to fewer oxygen atoms emerging at the high-κ/SiGe interface via scavenging. As the thickness of the bottom-metal TiN decreased, the hysteresis became more significant, and the V FB value in the forward sweep shifted towards negative, which was thought to be related to more oxygen vacancies being generated due to a more effective scavenging process since the distance from the Al metal to the SiGe gate stack was shorter [31].
Meanwhile, Fig. 6 (e) shows the effect of increased upper-metal Al thickness (Al/TiN of 50nm/10nm) on the scavenging process. In our thoughts, the increased uppermetal Al thickness might bring about a more substantial scavenging effect making the hysteresis performance worse and generating more oxygen vacancies. Surprisingly, the smaller hysteresis width and the positive-shifted V FB in the forwarding sweep were observed; this trend was opposed to those cases shown in Fig. 6 (b)-(d). Therefore, we speculated that the thicker Al capped metal of the SiGe capacitor likely prevented more oxygen atoms diffusing from ambient to the high-κ/SiGe interface, as illustrated schematically of the inset in Fig. 6; the capacitor with thinner Al capped metal perhaps allowed more oxygen atoms appeared at the highκ/SiGe interface. Subsequently, when the PMA process was conducted, the number of generated oxygen vacancies at the high-κ/SiGe interface would originate from the number of oxygen atoms scavenged out. As a result, smaller hysteresis width and positive-shifted forward V FB were attained.
In addition to the hysteresis performance results, more extracted electrical parameters of the SiGe capacitors with various gate electrodes are listed in Table 2. Comparatively low EOT values of less than 1 nm of all the SiGe capacitors were obtained with various gate electrode configurations, implying the 2-cycle TMA treatment could result in thinner IL and a smaller EOT value. Moreover, the sample with only sputtered TiN exhibited the highest D it value, which meant the worst SiGe interface quality was obtained. When the Al capping was employed, the SiGe interface quality improved significantly. As the upper-metal Al thickness was fixed and the bottom-metal TiN thickness decreased, the D it value became minor owing to the more superior oxygen scavenging ability.
Furthermore, different from the hysteresis tendency of the SiGe capacitors with increased Al upper-metal, that with Al/TiN of 50nm/10nm exhibited the lowest D it value, which was supposed to be the fewest oxygen content at the high-κ/SiGe interface caused by the combination of more substantial Al scavenging capability and thicker Al-O layer oxygen diffusion barrier. Therefore, fewer oxygens could lead to lessened SiGe reoxidation. Also, the D it and J G values showed the same trend among all the samples indicating the J G might arise from the fuzzy SiGe interface, which could be cured through the oxygen-scavenging process. Furthermore, it was found that the D it values and the J G values could be improved about 60 times and 100 times around SiGe capacitors with various metal compositions, respectively, which had similar trends in our previous study [17].
Figs. 7 (a)-(c) depict the XPS spectra of Si 2p, Al 2p, and Hf 4f for the Al/TiN/HfO 2 /2-cycle TMA-IL/Si 0.8 Ge 0.2 stack structures with various gate electrodes compositions (Al/TiN of 25nm/40nm, 25nm/25nm, and 25nm/10nm) to demonstrate the effect of the scavenging on the material interaction with the entire gate stack. The XPS analyses were conducted on the samples after removing the top gate by soaking in APM, the same experimental procedure in Fig. 4. For the Si 2p spectrum, the peak positions of the samples with various top metal compositions were observed around the Si 2+ and Si 3+ signals with similar peak intensity. In addition, the peak positions of SiO x were observed at random binding energies, indicating that the scavenging strength might not affect the Si oxidation at the high-κ/SiGe interface.
On the other hand, Fig. 7 (b) displays the peak heights of AlO x binding energy of the samples; the peak height was lower when the bottom-metal TiN thickness was decreased. Therefore, we speculated that the oxygen atoms at the highκ/SiGe interface might come from two paths. One is inward diffusion from the ambient through the PMA process, which might be greatly inhibited via Al capping. Another is the oxygen atoms accommodated inside the TiN metal, which downward diffuse through the PMA process [17]. With thinner TiN, fewer oxygen atoms are contained, and thus those oxygen atoms diffusing to the high-κ/SiGe interface and forming the Al-O bonds are correspondingly fewer. The XPS results of Al 2p spectra seemed able to explain the improvement in D it , as shown in Table 2, as the TiN was thinner (Al/TiN of 25nm/40nm, 25nm/25nm, and 25nm/10 nm). Therefore, we thought that the high-quality high-κ/SiGe interface would be attributed to fewer Ge dangling bonds left because of the result arising from the formation of fewer Al-O bonds [15]. Besides, Fig. 7 (c) illustrates the XPS results of Hf 4f core levels, disclosing that the HfO 2 would not be influenced by the Al scavenging process during the PMA process. The finding of the XPS result clarified that the Al scavenging effect only affected the high-κ/SiGe interface but not the high-κ HfO 2 dielectric.
Furthermore, the normalized XPS devolution results of O 1s spectra are shown in Table 3. By looking into the difference in oxygen configuration, the scavenging strengths with different electrode structures could be clearly revealed. We found that the proportions of metal-oxygen, including Hf-O and Al-O bonds, located at 530.7 eV and 530.4 eV, were the least when the thinnest bottom-metal TiN thickness was applied (Al/TiN of 25nm/10nm), implying that the fewer Al-O bonds were formed [32], [33]. The XPS results also showed that the proportion of oxygen vacancies was increased with decreasing the bottom-metal TiN thickness [34], [35], which echoed the hysteresis width trend observed in Figs. 6 (b)-(d). Fig. 8 depicts multi-frequency C-V characteristics of the Si 0.8 Ge 0.2 capacitors with different HfO 2 (20-cycle, 25-cycle, and 30-cycle) thicknesses to demonstrate the feasibility of EOT scaling through TMA pre-treatment and Al capping. The optimized gate electrode of the Al/TiN of 50nm/10nm was applied for three SiGe capacitors with different HfO 2 thicknesses. We found the SiGe capacitors with thinner HfO 2 dielectric displayed relatively small humps at the depletion region and exhibited the low D it value of 7 × 10 11 cm −2 eV −1 , which might be due to the more substantial Al scavenger metal effect [36]. In addition, all the energy levels of minimum D it values of fabricated SiGe capacitors were near E-E v ∼0.29 eV. By tuning down HfO 2  thickness, a pretty impressive EOT value of 0.81nm was achieved with the increase in J G , resulting from the higher probability of direct tunneling [37].

C. SIGE MOSCAP OPTIMIZATION
Figs. 9 (a) and (b) present cross-sectional HRTEM images and Energy Dispersive X-ray Spectrometry (EDX) depth profiles of the SiGe gate stack with 20-cycle and 30-cycle HfO 2 depositions, respectively. We observed that the IL thickness of approximately 1.0 nm was formed for both gate stacks through 2-cycle TMA treatment. In addition, the thicknesses of the 20-cycle and 30-cycle HfO 2 depositions were 2 and 2.6 nm, respectively. Accordingly, the calculated dielectric constant of the TMA-treated IL and HfO 2 would be 8 and 23, respectively, meaning the EOT value could be improved through the dielectric constant of IL improvement by TMA pre-treatment.
Finally, Fig. 10 summarizes the benchmark of J G at V FB −1V or V th −0.7V versus EOT for the Si-cap-free highκ/SiGe stacks with Ge contents of SiGe from 20% to 50%. Among the high-κ/SiGe gate stacks with various Ge contents of SiGe reported [38], [39], [40], [41], [42], our advanced SiGe gate stacks composed of TMA pre-treatment and Al capping offered excellent EOT performance and relatively lower gate leakage current. The EOT of 0.81nm and 0.9nm with lower gate leakage currents were obtained by the HfO 2 thickness reduction.

IV. CONCLUSION
This study reported the Al scavenger effect on the HfO 2based gate dielectric on the Si 0.8 Ge 0.2 substrates with IL TMA pre-treatment. The aggressive EOT value of 0.81nm was obtained through the 20-cycle high-κ HfO 2 deposition. The D it and J G values could be improved about 60 times and 100 times by tuning the gate electrode composition without degrading the EOT performance. The XPS results revealed that the D it improvement during the various gate electrodes applied might be owing to the Al metal scavenger and the minimization of the oxygen atoms' diffusing to the high-κ/SiGe IL during the PMA process. Moreover, the high-κ HfO 2 dielectric might not be affected via the oxygen scavenging process. Besides, the hysteresis levels of SiGe capacitors were also tested to optimize the metal composition of Al/TiN, which XPS results could verify. This study thoroughly examined the SiGe capacitor with TMA pre-treatment and Al metal-capped. As a result, a simple gate stack structure of high-performance SiGe devices could be obtained by optimizing TMA pre-treatment and gate engineering.