Highly Efficient Reconfigurable Stateful Logic Operations Based on CuI Memristor-Only Arrays Prepared With a Solution-Based Process

The in-memory logic computing has been intensively studied as being considered as an important scenario to address the power-consumption issue posed by modern computers based on the von Neumann architecture. However, the realization of in-memory logic computing is generally based on memristors prepared by vacuum techniques and the implementation of logic operation requires multiple cycles of voltage pulses, which limits the computing efficiency. In addition, the logic architectures that cannot be mapped into large crossbar arrays restrict the level of parallelism. A CuI memristor is prepared by a solution-based process in this work. Based on the CuI memristor arrays, with delicately designed implement strategy, a set of logic operations can be implemented with one single cycle of voltage pulses, demonstrating the high efficiency. Moreover, all proposed logic architectures are able to be mapped to large memristor crossbar arrays directly, demonstrating the great potentials in computations with high degree of parallelism. Owing to the reconfigurable property, a one-bit full adder is realized by cascading the memristor-based logic gates.


I. INTRODUCTION
The separation of storage and computing unit in the traditional von Neumann architecture is no longer suitable for data-driven artificial intelligence applications [1], [2]. When performing various computing tasks, a large amount of data needs to be transferred back and forth between the computing unit and storage unit, resulting in high latency and high energy consumption [3]. With the integration of storage and computing unit, the in-memory computing architecture was proposed to avoid the data transfer and thus to greatly improve the computing parallelism and energy efficiency [2], [4], [5]. The concept of in-memory computing was first proposed in 1960s [6], but did not receive enough attention. With the advent of memristor technology, the in-memory computing attracts much attention again [7], [8], [9]. And then, many emerging memory concepts are studied to construct the in-memory computing architecture [10], [11], [12], [13]. The memristor has many excellent characteristics, such as nonvolatility, high switching speed, low power consumption and high scalability, making it widely used in logic operation, neuromorphic computing, and storage [14], [15], [16], [17], [18]. Using the two stable high and low resistance states of memristors to represent the logic inputs and outputs, the in-memory logic computing based on memristor arrays can address the issue about von Neumann architecture by conducting the computing in situ, exactly where the data are stored [19], [20]. Borghetti et al. proposes the IMP (i.e., imply) circuit based on memristors [21], and the rest of logic operations are realized through a combination of IMP and FALSE logic operations. Huang et al. proposes a reconfigurable stateful Boolean logic based on memristor, which realizes NAND and AND logic operations [22]. Kvatinsky et al. proposes the memristor-aided logic (MAGIC) [23], which only contains the memristor and does not require a load resistor. But only the NOR and NOT logic structures can be mapped to a large memristor crossbar array directly, limiting the capability of computing parallelism. Moreover, all these computing architectures are constructed based on oxide memristors which are prepared by vacuum techniques.
In this work, the memristor based on a Pt/CuI/Cu structure is fabricated with a low-cost solution-based process. Based on the electrochemical metallization (ECM) mechanism, the CuI memristor realizes the resistive switching (RS) behavior and exhibits a much larger set voltage than the reset voltage. Through constructing appropriate CuI memristor arrays without the need of load resistor and delicately designing the executing strategy, a set of Boolean logic operations can be implemented with one single cycle of voltage pulses applied to the arrays. It simplifies the executing steps and thus improves the computing efficiency. In addition, all demonstrated logic architectures in this work can be mapped to large memristor crossbar arrays directly, showing promising applications in the image processing with high degree of parallelism. Fig. 1a shows the complete fabrication process. Starting with the clean of 280-nm SiO 2 /Si substrates by rinsing the samples in acetone, isopropyl and de-ionized water respectively with ultrasound, the 10-nm Ti/ 20-nm Pt film was deposited by a e-beam evaporator. And then the bottom electrodes were defined by a DWL 66+ laser writer and formed by drying etching with an Oxford integrated ICP etch clustering system. The 115-nm CuI film was prepared with a solution-based process. The 1 M CuI precursor solution was prepared by dissolving CuI powder (99.5%, Sigma Aldrich) into a mixture solution of 2-aminoethanol (99.5%, Sigma Aldrich) and 2-metoxyethanol (99.8%, Sigma Aldrich) with a molar ratio of 1:1. After spin coating the CuI solution on the top of bottom electrodes, the samples were solidified at 100 • C and 160 • C in air for 1min and 10 min in sequence on a hotplate to solidify the CuI film. Thereafter, the samples were further annealed at 300 • C in the vacuum for 30 min to improve the CuI film quality. Next, the CuI film was isolated into islands by wet etching in 2% HCl solution. After that, a 30-nm Cu film was deposited on the CuI film by sputtering. The top 10-nm Ti/ 60-nm Au electrodes were prepared with a standard lift-off process. The 1 mol/L FeCl 3 : HCl = 1: 1 solution was adopted to etch the Cu film to form the isolated Pt/CuI/Cu memristors. Finally, the devices were encapsulated by SU-8 and the electrodes were exposed by the laser writer for the following electrical characterization.

II. EXPERIMENTAL DETAILS
A Park NX20 AFM was used to determine the film thickness and characterize the surface profile of CuI film. A Renishaw inVia Raman/PL spectrometer with a 325 nm He-Cd laser and a 1200 l/mm grating was adopted to acquire the PL spectra at room temperature. All electrical characteristics were measured with an Agilent 4156C semiconductor analyzer in ambient condition at room temperature. For all the measurements, the Ti/Pt bottom electrodes are grounded and the voltage bias was applied to the Cu top electrodes.

III. RESULTS AND DISCUSSION
Characterized by the AFM, Fig. 1b shows the surface morphology of CuI film prepared on the Pt film, exhibiting clear grains. The RMS roughness is 8.1 nm which agrees well with previous report about the crystallization profile of CuI. The photoluminescence (PL) characteristics is shown in Fig. 1c, in which the peak around 410 nm with an optical band gap of 3.02 eV is reasonably ascribed to the radiative recombination of free excitons [24], [25]. Fig. 1d shows the microscope image of CuI memristor array and the structure of CuI memristor. Fig. 1e shows the current-voltage (I-V) sweep acquired with a Pt/CuI/Cu memristor, exhibiting an obvious RS behavior. Previous work has demonstrated that the electrochemical deposition and dissolution of Cu conductive filaments (CFs) under the electrical bias contributes to the RS behavior. When the bottom Pt electrode is grounded, a positive voltage applied to the top Cu electrode induces the set process (filament formation) and the device is toggled to low-resistance state (LRS), i.e., ON state. The voltage at the turning point is defined as the set voltage V set . After that, a negative voltage can induce the reset process (filament rupture) and toggle the device to high-resistance state (HRS), i.e., OFF state. And the voltage at the turning point in this process is defined as the reset voltage V reset . Fig. 1e shows that the set and reset voltages are 0.7 V and −0.21 V respectively. The absolute value of set voltage is larger than the reset voltage by 3 times, as shown in the following discussion, is critical for the implementation of efficient logic gates realized with one single cycle of voltage pulses. In addition to the endurance, the cycle-to-cycle and device-to-device variations have been studied and reported in previous work [26]. To verify the nonvolatility of CuI memristor, the resistance of device at two states are read at 0.05 V consecutively after set/reset process. As shown in Fig. 1f, the residual on/off resistance ratio is still larger than 3 orders and the two states can be clearly identified after 17 hours, demonstrating the nonvolatility of CuI memristor.
Based on the CuI memristor array, in-memory digital Boolean logic operations can be realized. The logic inputs and outputs ("0" and "1" are to represent HRS and LRS states respectively) can be stored directly in the memristors to avoid the shuttle of data. Owing to the large difference between absolute V set and V reset for the CuI memristor, the voltage pulse V 0 can be delicately designed, 2V reset < V 0 < V set (V 0 = 0.5 V in this work), to implement the logic computation in CuI memristor arrays by one single cycle of voltage pulses [23]. As shown in Fig. 2a, a 1×3 memristor array is adopted to implement a set of logic gates. The initial logic inputs are represented by the resistance states of memristors p and q, and the memristor s will be always set to LRS (logic "1") before the logic operation. During the logic operation the resistance states of memristor s will be toggled conditionally to yield the correct logic output s' or s". The logic inputs are preserved throughout the computations. Fig. 2b shows the implement strategy to conduct the logic computation. Except the XNOR logic gate, all the other logic gates can be implemented with one single cycle of voltage pulses. Taking the NOR logic gate as an example, during the logic operation the voltage pulse V 0 with duration of 1.2 s is applied to the memristor p and q respectively at the same time while the memristor s is biased to be 0 V. As the V reset is −0.21 V for the memristor, it can be found that the memristor s will be toggled to HRS (logic "0") as if at least one of the memristors p and q is at LRS (logic "1"). Specifically, when logic inputs are 00 (i.e., the resistance states of memristors p and q are both at HRS), the voltage applied to the memristor s is lower than the V reset , so that the resistance state of memristor s remains unchanged (i.e., logic "1"). For all other logic inputs, the voltage applied to the memristor s is larger than the V reset , switching the resistance state of the memristor s to HRS (i.e., logic "0"). Thus, as shown in Fig. 2c, the CuI memristor array can be used to execute the logic computation and output the correct logic value for all 4 different logic inputs (00, 01, 10, 11). It should be made clear that the pulse width of 1.2 s is aimed to ensure a complete rectangle pulse, which is limited by the equipment. Therefore, it should be far from reaching the device performance limit. Similarly, the other logic gates can also be implemented by the same CuI memristor array by simply adopting different implementation strategy, as shown in Fig. 2b and 2c, demonstrating the reconfigurable property of CuI memristor array. The NOR and NAND gates are universal, that is, any Boolean logic operation can be implemented based on an appropriate combination of these gates, meaning that the CuI memristor arrays are capable of completing more complex computation tasks. Moreover, it can be found that the logic operations of multiple logic gates can be executed simultaneously in a single cycle when these logic gates are co-located in the same row or column, thus providing a high parallelism of logic operations inside a large memristor array. It suggests that all demonstrated logic architectures can be mapped to large memristor crossbar arrays directly. Owing to the ratio larger than 3 orders between the HRS and LRS, the different resistance states after logic operations can be identified clearly as shown in Fig. 2c, regardless of the variations for the HRS and LRS. However, the variations for the set and reset voltages may lead to the failure of implementation strategy for the logic operations. Taking the NAND gate for example, the voltage pulses cannot toggle the resistance state of memristor s to HRS (logic "0") sometimes when the inputs are "11", leading to the bit error. The bit error rate can reach 8% in 50 times of logic operations for the NAND gate when the logic inputs are "11". To address this issue a new device structure composed of CuI/CuIX bilayer can be explored in the future work. Doping the CuI with element X can change the crystalline structure, by which the formation of conductive filaments can be confined at the interface of CuI/CuIX to reduce the spatial and temporal variations and thus the bit error rate [27], [28], [29].
The efficient logic cascading can be achieved by integrating above logic gates composed of two or three memristors to realize more logic functions, such as one-bit full adder. For a one-bit full adder there are three logic inputs including summand a, addend b, carry-in c. The two logic outputs (sum s and carry-out c') can be obtained by the following two combinations of logic operations: Fig. 3a shows the circuit schematic of a one-bit full adder composed of two XOR and three NAND gates. To map the full adder into a CuI memristor array, a 1 × 10 CuI memristor array (M 1 , M 2 , . . . M 10 ) is prepared as shown in Fig. 3b. The first three memristors are adopted to store the initial logic inputs a, b and c. Fig. 3c shows the complete 9 logic steps to yield the carry-out c' and sum s which are obtained with M 8 and M 10 after step 6 and 9 respectively. Fig. 3d shows the experimental results for all 8 different inputs (000, 001. . . 111), demonstrating that the one-bit full adder can be accurately implemented based on the 1 × 10 CuI memristor array under the in-memory computing mode. The arithmetic and logical unit (ALU) is critical for the central processing unit (CPU), the implementation of logic gates and full adder based on CuI memristor arrays paves the way to construct an ALU based on CuI memristors and to realize the efficient in-memory logic computing processor.
Finally, the proposed in-memory logic method is compared with prior memristor-based in-memory logic methods, as listed in Table 1. This work can realize six Boolean logic operations, which is more than the number of basic functions performed in literature [21], [22], [23], [30], [31]. The proposed logic circuit can be reconfigured to execute diverse logic operations within the same logic cell, simply by altering the applied voltages compared with [21], [23], [30], [31]. The logic circuit of [22] can only be reconfigurable to realize two logic operations, i.e., NAND and NOR. The  logic configuration of this work can be integrated within a memristor crossbar array, while the logic configuration of [30] cannot. In [23], only NOR logic gate can be integrated into the crossbar array. Although the logic structures in [21], [22], [31] can also be integrated into the crossbar array, an additional resistor is required within each row or column of the array, increasing the circuit overhead.

IV. CONCLUSION
The memristor based on a Pt/CuI/Cu structure is fabricated with a low-cost solution-based process. The ECM mechanism contributes to the RS behavior of CuI memristor and a set of in-memory logic gates are constructed based on memristor-only arrays. Owing to the much larger set voltage than the reset voltage, with delicately designed implementation strategy the logic operations can be implemented with one single cycle of voltage pulses. Moreover, all proposed logic architectures can be mapped to large memristor crossbar arrays directly, demonstrating the great potentials in computations with high degree of parallelism. Finally, a one-bit full adder is achieved by reconfiguring the memristor array.