Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures

The paper presents a novel approach to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications.


I. INTRODUCTION
The threshold voltage (V T ) is one of the important parameters of the MOSFET for analog and digital circuits, separating the transfer characteristic (I D -V G ) into the weak, i.e., subthreshold, and the strong inversion regimes. Since V T is not a physical parameter, the definition of V T can vary from one technology to another [1]. For instance, in historical bulk MOSFET, V T is defined by the band bending condition where the surface potential is close to twice the Fermi level of the substrate [2]. However, such V T condition may not be appropriate for modern devices [1]. Instead, V T is determined at a gate voltage V G where the inversion charge density reaches a certain value, e.g., N inv,th ≈ 10 11 cm −2 [3], [4], such method is applied to multi-gate FinFETs [5] and double-gate SOI MOSFETs [4], [6], [7]. Additionally, in [8] and [9], V T of lightly doped FDSOI is defined as the voltage necessary for the carrier density to be equal to the doping level of the silicon channel.
The associate editor coordinating the review of this manuscript and approving it for publication was Marcelo Antonio Pavanello .
Nevertheless, electronics operating at cryogenic temperatures has a tight power budget due to limited cooling power, for example, 1 W at 4 K [11]. Hence, cryogenic integrated systems demand low-power dissipation. Although the subthreshold swing and mobility are improved at low temperatures [18], the increase in V T challenges the circuit designers. The advanced FDSOI MOSFET with an ultra-thin channel and a thin buried oxide layer (BOX), e.g., BOX thickness t box ≈ 20 nm [25], [26], is a promising technology that is ideal for low-power design. In FDSOI, one can efficiently  [4]. The shift in the V T due to cryogenic temperatures can then be lowered by the forward back bias (FBB), which is positive V B for nMOS and negative V B for pMOS. The V T expression accounting for the V B has been initially described by the classical Lim and Fossum model [27]. The more sophisticated models have been introduced to use the concept of N inv,th and to take the volume inversion and quantum confinement into account [4], [28], [29]. The existing V T (V B ) models require the pre-defined N inv,th [4], [7], [28], [29]. Such models can be well implemented in compact models and design process kits. Nonetheless, it is not intuitive for circuit designers how to tune the V T through V B . This kind of model has not yet been validated for cryogenic temperatures. The lack of the well-described V T -V B relation challenges designers in optimizing their systems. Therefore, this paper proposes an analytical expression for V T versus V B using a novel approach without pre-defined N inv,th . The derived model is validated with a commercial 22 nm FDSOI technology [30] at room and cryogenic temperatures.

II. ANALYTICAL MODEL OF BACK-GATE COEFFICIENT
Instead of modeling V T with the N inv,th definition like existing models do [4], [28], [29], the proposed model uses a novel approach by looking at the so-called back-gate coefficient η = dV T /dV B . The term η can be determined from the relation between the back-gate transconductance (G mb ) and front-gate transconductance (G m ), given by with I D the drain current. Because I D can be expressed as a function of V G − V T , ∂I D /∂V T can be replaced by −G m . To simplify the derivation, the subthreshold regime is assumed, where I D is given by [31] with q the elementary charge, µ 0 the low-field mobility, n i the intrinsic charge density, U T the thermal voltage (see Table. 1), V DS the drain-to-source voltage, W and L the channel width and length, ψ sf and ψ sb the front and back surface potentials. Due to the gate coupling, i.e., ψ sf (V G , V B ) and ψ sb (V G , V B ), the G m and G mb can then be expressed as where the slope factors are given by [31] n ff ≜ dV G dψ sf Capacitances, C fox , C box , and C ch , are given in Table. 1.
It should be noted that V G and V B are referenced to the source voltage, and ψ sf and ψ sb are the channel intrinsic level referenced to the Fermi level at source terminal. Taking (2) into (3) and then inserting (3) into (1) result in an analytical expression of η, given as η = n fb n ff −n bb θe θ − e θ + 1 + n bf θ − e θ + 1 n bb n bf n fb θe θ − e θ + 1 − n ff θ − e θ + 1 , where θ = ψ/U T and the term ψ = ψ sf − ψ sb is given by [31] where mf and mb are listed in Table. 1. The term mf − mb is the work function difference between the front and back gates. For instance, mf − mb ≈ −0.6 V for a conventional-well (RVT: regular threshold voltage) nMOS [30], where the mid-gap metal and the p-type backgate are implemented. Eq. (6) can be re-written as a function of slope factors, given by where the term 1/n ff − 1/n fb could be replaced by 1/n bb − 1/n bf thanks to (4). Additionally, (5) has asymptotes with respect to the value of θ = ψ/U T , given by − n ff n fb (n bb + n bf ) n bb n bf (n fb + n ff ) Comparison of the analytical model of η by (5) and the modified sigmoid expression η sigmoid by (10) with respect to the normalized surface potential difference θ .
Substituting the slope factors in (5) with (4) results in η in a form of capacitance as Eqs. (6) and (9) are helpful when the technology parameters, i.e., dielectric thickness and constants, are known. Conversely, (5) and (7) can be adopted by giving the extracted slope factors (4) from the front and back transfer characteristics. Therefore, the following derivations keep the form in terms of slope factors for convenience. The V T model can be derived by integrating (5). However, it leads to a complicated expression which can be replaced by the following sigmoid function where The term B does not have an analytical expression, and the first derivative of η,η, is not continuous at θ = 0. Hence, B is defined at θ → 0 + and has a value ≈ 0.333 for a 22 nm FDSOI technology. Finally, η sigmoid from (10) gives a good approximation of (5) as shown in Fig. 1, where the percentage error is calculated and is in a reasonable range.

III. THRESHOLD VOLTAGE MODEL
It is important to know how much modulation in V B , V B , is required to change the threshold voltage from V T 1 to V T 2 .
The difference in V T , V T , can be calculated by integrating (10), which yields with the terms The relation (13) is not a typical threshold voltage model that is a function of V B . Instead, (13) is based only on gate coupling and calculates how much V B is needed for reaching V T . Hence, the model does not pre-assume the threshold condition N inv,th , but requires a calibration point that is a set of V T 1 and V B 1 . With the given calibration point and the input V T 2 , the root of (13), i.e., V B 2 , can be computed by a nonlinear equations solver [32], [33].
One aspect of the further scaling on the FDSOI technology is the thickness of BOX [34], [35]. Fig. 2 presents the calculated V T versus V B by using (13) and 4, in which the scaling of FDSOI technology is highlighted by showing the various t box and t ch . It implies that implementing the ultra-thin BOX allows the efficient modulation of V T through V B . For instance, 1 V of V B yields V T > 110 mV for t box = 10 nm. However, it only allows V T ≈ 25 mV for t box = 100 nm. Conversely, the thinner t ch slightly declines the η, resulting in a gradual V T versus V B as shown by the red lines in Fig. 2.

IV. EXPERIMENTAL VALIDATION
This section focuses on the model validation from 300 K down to cryogenic temperatures by comparing the measurement on a long-channel conventional-well (RVT) nMOS by a 22 nm process [30]. Due to the p-type back gate lying on a deep n-well, it can sweep the back-gate voltage widely from negative to positive.
The room temperature V T is extracted from the transfer characteristics of a single-finger nMOS FDSOI MOSFET with 1 µm of the gate length and width at V DS = 10 mV VOLUME 11, 2023 56953 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  (5) and (10) are well compared to measurement. The asymptotes of (8a) are highlighted. The θ = 0 happens at V T − V B = −0.63 V due to −0.63 V of the front-back gate work function difference [18]. in [31], and the second derivative method is utilized to define the V T [1].
The cryogenic V T is taken from [18] by using the linear extrapolation method [1] because of the significant data fluctuation in the second derivative method. The investigated device is a two-finger nMOS FDSOI MOSFET with 1 µm of the gate length and total width at V DS = 1 V.
Since the manuscript focuses on the gate coupling that leads to the V B -dependent V T , the 1 µm-length devices are selected. Hence, the short-channel effects, particularly drain-induced barrier lowering (DIBL), are ignored. The V T is the same in linear and saturation modes.

A. VALIDATION AT ROOM TEMPERATURE
The modeling of η is validated by comparing with experiments as shown in Fig. 3, in which the η versus the voltage difference, V T −V B , is presented at room temperature. Significantly, η is not constant over a wide range of V B because of the strong gate coupling that is induced by the thin channel and BOX. In addition, the original model (5) and the simplified model (10) compare well against the measurement. It should be noted that the models are generated by using the extracted slope factors from [31], also listed in Table. (2), where the slope factors are extracted from the subthreshold swing with I D is at nA µm −1 . The successful validation reveals that adopting the back-gate transconductance (referring to (1)) and subthreshold drain current (referring to (2)) are sufficient to describe the non-linear back-gate coefficient.
In addition, the proposed V T expression is verified in Fig. 4. The expression (13) accurately models the relation of V T and V B , and it requires only one calibration set, i.e., V T 1 and V B 1 , the work function difference between front and back gates, and the slope factors. The selection of the calibration point does not matter, V T 1 = 0.35 mV and V B 1 = 1 V are chosen in Fig. 4, where the θ ∼ −0.77 is close to the asymptote θ → 0. The work function difference between front and back gates, mf − mb , is −0.63 V with the mid-gap implementation for the front gate and p-type silicon for the back gate. If the n-type silicon is used for the back gate, it would suggest mf − mb = 0.63 V. The slope factors are again taken from [31]. Since n bf = n ff /(n ff − 1) and n fb = n bb /(n bb − 1) [31], the model, in the end, requires only two slope factors, n ff and n bb .
Besides, the asymptotes given by (8) are presented in Fig. 4, and show a nice agreement with the measurement in the corresponding region. It is worth noting that the asymptote η θ→0 has the reasonable prediction around θ = 0, i.e., from V B = 0 V to 2 V, it has a value of −75.8 mV/V. Such simple asymptote (8b), for instance, can be used to adjust the V T within a range of around 150 mV. The dynamic range is sufficient to eliminate the threshold voltage mismatch. Furthermore, the asymptote (8b) may be utilized to compensate for the increased V T at low temperatures. The following section then focuses on verifying the derived model at low temperatures.

B. VALIDATION AT CRYOGENIC TEMPERATURES
It has been shown that a V T -V B relation can be established at RT through the FOX, BOX, and channel capacitances. It has recently been shown experimentally that the back-gate coefficient is nearly temperature-independent [14], [15], [17], [18], [20], [39]. It suggests that the back-gate coefficient at cryogenic temperatures is mainly ascribed to gate coupling. Moreover, the experimental fact reveals that the capacitances do not have a significant temperature dependency. 56954 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. Changes in work functions with respect to that at room temperature. Various p-type back-gate doping levels are compared. The band gap widening [36] and the temperature-dependent Fermi level [37], [38] are considered.  Table. 2. The change in work functions due to the temperature is estimated in   Table. 2 and parameters used in Fig. 6. The condition θ = 0 is pointed out by the dashed lines.
Conversely, the work functions, mf and mb , are sensitive to the temperature due to the temperature-dependent Fermi level, band gap widening, and incomplete dopant ionization. We assume that the work function of the mid-gap front gate is always positioned at the middle of the channel band gap, even at low temperatures. It means that the temperature effect on the mid-gap gate is ignored. Due to the implementation of p-type silicon as the back gate of the nMOS RVT device, we can write mf − mb = −( E g /2 − E f ,b ) with E g the band gap and E f ,b the back-gate Fermi level referenced to the valence band. The temperature dependency of mf − mb with respect to the value at room temperature is presented for various back-gate doping levels (N A ) in Fig. 5. The Varshni model describes the band gap widening [36], and the change in E f ,b is calculated by [37] and [38]. For example, the term mf − mb is decreased by 161 mV from room temperature down to 3 K as N A = 10 16 cm −3 .
Ultimately, Fig. 6 shows the model validation at 150, 77, and 3 K, where (13) successfully agrees to the experimental data with the given calibration points and the slope factors in Table. 2. As shown in Table. 2, slope factors slightly depend on the temperature. This might be due to the thinner FOX, BOX, and channel thicknesses at low temperatures. On the other hand, N A = 10 16 cm −3 is assumed to estimate mf − mb . Because the temperature varies the mf − mb , as presented in Fig. 5, it leads to that θ = 0 happens at the different V B , as highlighted by the dashed lines in Fig. 6. Additionally, the model at 3 K has an abrupt change at θ = 0, where V B ∼ 1.3 V. Such abrupt change is because η manifests as a rapid step function at deep cryogenic temperature as demonstrated in Fig. 7. A sharp transition located at θ = 0 for 3 K connects two regions, η θ →−∞ and η θ →∞ . We have mentioned in Sec. IV-A that η θ →0 , (8b), can simply estimate the V T in a V B range from 0 to 2 V for such RVT flavor. However, at deep cryogenic temperatures, estimating V T with the asymptote (8b) is not accurate anymore since η changes rapidly at θ = 0. Instead, η θ→−∞ , (8c), should be used for the region where θ < 0, and η θ →∞ , (8a), is for where θ > 0. For example, as the 3 K data shown in Fig. 6, we can lower the V T = 550 mV for V B = 0 V to V T = 500 mV for V B = 1 V with η θ→∞ = −50 (Table. 2).
However, the slope factor of a transfer characteristic at 3 K, annotated by n eq , reaches a value around ten [40] due to the subthreshold swing (SS) saturation [23], [24]. The SS does not linearly scale with the Boltzmann limit but is saturated at cryogenic temperatures due to the hopping conduction in the band-tail states. Therefore, the n eq = SS/(U T ln 10) is almost 10 times higher than the n ff in Table. 2. The incompatibility between n eq and n ff reveals that the hopping conduction does not affect the V T -V B relation. Conversely, since the saturated SS can be expressed at SS = n ff (W t /q) ln 10 with W t the band-tail parameter [24], we can then write n eq = n ff (W t /kT ). Besides, due to the SS saturation at cryogenic temperatures, the low-temperature slope factors in Table. 2 are not directly obtained from the saturated SS. Thus, the optimization is applied to fit the result in Fig. 6, resulting in the low-temperature slope factors as shown in Table. 2.

V. CONCLUSION
An analytical threshold voltage model of FDSOI MOSFETs has been derived and validated down to 3 K by the measurement on a 22 nm FDSOI technology. By expressing the gate VOLUME 11, 2023 56955 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
coupling effect on the back-gate coefficient through the slope factors, the proposed model does not require the pre-assumed threshold condition. Instead, it relies on a calibration point and slope factors. Such a simple analytical expression accurately predicts the threshold voltage as a function of the back-gate voltage at cryogenic temperatures. The proposed expression can be used to optimize low-power circuits by lowering the threshold voltage correctly. It is useful for designing circuits with a tight power budget, for instance, cryogenic electronics for quantum computing. He has been the driving force behind the creation of deep-submicrometer CMOS single-photon avalanche diode (SPAD) technology, which is mass-produced, since 2015, and is present in telemeters, proximity sensors, and medical diagnostics tools. He has authored or coauthored over 400 articles and two books, and he holds 23 patents. His research interests include 3-D vision, fluorescence lifetime imaging (FLIM), fluorescence correlation spectroscopy (FCS), near-infrared optical tomography (NIROT) to super-resolution microscopy, time-resolved Raman spectroscopy, and cryo-CMOS circuits and systems for quantum computing.