Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer

Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible <inline-formula> <tex-math notation="LaTeX">$4\times 1$ </tex-math></inline-formula> multiplexer and <inline-formula> <tex-math notation="LaTeX">$1\times 4$ </tex-math></inline-formula> demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible <inline-formula> <tex-math notation="LaTeX">$n\times 1$ </tex-math></inline-formula> multiplexer and <inline-formula> <tex-math notation="LaTeX">$1\times n$ </tex-math></inline-formula> demultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.


I. INTRODUCTION
A significant barrier to future circuit design is its high energy consumption. In 1961, Landauer proved that traditional irreversible gate leads to energy dissipation in circuit design [1]. Zhirnov et al. demonstrated that it would be impossible to remove heat from CMOS because of power dissipation [2]. According to Bennett's research, power dissipation can be prevented in circuit design by using reversible gates [3]. Recovering the input vectors from the output vectors in reversible gates is possible because the number of inputs equals the number of outputs.
Moreover, the output vectors are recoverable from the input vectors [4], [5], [6]. These circuits are also not permitted to have feedback or fan-out [6]. The inherent reversibility The associate editor coordinating the review of this manuscript and approving it for publication was Ludovico Minati . makes quantum technology a promising technology for future computer systems [7], [8].
Demultiplexer and multiplexer circuits are essential components of computers, arithmetic logic units, communication systems, memory systems, and converters [40]. This work proposes a new realization of quaternary reversible multiplexer and demultiplexer circuits. This paper aims to synthesize quantum quaternary circuits that are more efficient than the existing designs in the literature [40], [41], [42]. Moreover, we present the characteristics of the proposed circuits in terms of quantum cost, number of garbage outputs, and number of constant inputs, which are described as follows: Quantum cost is the number of quaternary reversible 1-qudit Shift gates and 2-qudit Muthukrishnan-Stroud gates exploited for implementing the circuit. Circuit designers try to decrease the quantum cost as much as possible [40], [45].
The number of garbage outputs refers to the unutilized outputs added to the circuit to make it reversible. Increasing the number of these outputs enhances the information loss in reversible circuits [40], [44].
The number of constant inputs refers to inputs that must be held constant at a value of either 0, 1, 2, or 3 to synthesize the specified logic function. Increasing the number of these inputs enhances the lines in reversible circuits [40], [43].
In quantum quaternary logic, circuits are synthesized by minimizing these important parameters for better efficiency. The proposed quaternary circuits have better quantum cost, number of garbage outputs, and number of constant inputs compared with the existing designs in the literature [40], [41], [42].
This paper is structured as follows. The basic concepts of quaternary Galois field and quaternary reversible gates are explained in Section II. Our proposed scalable realization of the quaternary reversible multiplexer and demultiplexer is presented in Section III. In Section IV, the evaluation of the proposed circuits and comparison results are discussed. Finally, the conclusion of this work is provided in Section V.

II. BASIC CONCEPTS
This section shows the background on quaternary Galois Field and quaternary reversible gates, exploited in the subsequent sections.

A. QUATERNARY GALOIS FIELD LOGIC
The algebraic structure of the Galois Field (GF4) in quaternary logic consists of the set of values Q = 0, 1, 2, 3}, the addition (⊕), and multiplication (⊙) operations, which are displayed in Table 1 and Table 2. These are associative and commutative operations. Moreover, multiplication is distributive over addition [46]. VOLUME 11, 2023

B. QUATERNARY 1-QUDIT SHIFT GATES
Any transformation of the qudit, in quaternary reversible logic, is represented by a 4 × 4 unitary matrix, as shown in Figure 1. Each unitary matrix in can be realized as a 1qudit Shift gate [40], [47]. They are 1-input 1-output gates having the mapping (A) to (P= Z transform of A), where the input is A, and the output is P. Figure 2 shows the graphical representation of quaternary 1-qudit Shift gates.
The relationship between the input and output of these 1-qudit Shift gates is illustrated in Table 3. These are elementary quaternary reversible gates that can be realized utilizing liquid ion trap quantum technology. Therefore, these gates have a quantum cost of 1 [49].

C. QUATERNARY 2-QUDIT MUTHUKRISHNAN-STROUD GATES
Muthukrishnan and Stroud [47] proposed a family of 2-qudit multiple-valued gates, which are realizable in liquid ion-trap quantum technology. The quaternary Muthukrishnan-Stroud (M-S) gate is basically a controlled 2-qudit gate with two inputs and two outputs that can be defined as: of the controlled input B if the controlling input A is equal to 3; otherwise, the output Q is equal to the controlled input B), where I V is the input vector, and O V is the output vector. Hence the inputs are A and B, and the outputs are P and Q [47]. Figure 3 illustrates the symbolic representation of the quaternary 2-qudit Muthukrishnan-Stroud gate. The quantum cost of this gate is equal to 1.

D. QUATERNARY 3-QUDIT CONTROLLED FEYNMAN GATE
The quaternary Controlled Feynman gate is a 3-input 3-output gate having the mapping (A, B, C) to (P=A, Q=B, R= B⊕C if the input A is equal to 3; otherwise, the output R is equal to the input C), where the inputs are A, B, and C and, the outputs are P, Q, and R [48]. Figure 4a displays the graphical representation of the quaternary Controlled Feynman gate. Figures 4b and 4c demonstrate different realizations of this gate using M-S gates. This gate has a quantum cost of 6. According to the second realization in Figure 4c, it is possible to remove the 2-qutrit M-S gate in the red box if the input B is not needed at the output Q. Thus, the quantum cost can be reduced to 5, and the output Q is equal to B+2 if the input A=3.

III. PROPOSED QUATERNARY REVERSIBLE CIRCUITS
In this section, we propose a scalable quaternary reversible 4 × 1 multiplexer, and we use it to design the quaternary reversible 16 × 1 and n×1 multiplexers. Moreover, we introduce the new scalable quaternary reversible 1 × 4 to design 1 × 16 and 1×n demultiplexers. We use quaternary 1-qudit Shift and 3-qudit Controlled Feynman gates. The aim is to reduce the overall quantum cost, the number of constant inputs, and the number of garbage outputs.

A. PROPOSED QUATERNARY REVERSIBLE MULTIPLEXER CIRCUIT
Before discussing our proposed quaternary reversible multiplexer circuit, we provide the basic definitions and properties 46594 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. of the quaternary multiplexer. A quaternary multiplexer with 4 m inputs, has mselect lines to select which input should be sent to the output. Let A be a selector equal to 0, 1, 2, or 3. In a 4 × 1 multiplexer, when A is equal to 0, 1, 2, or 3, the output equals I0, I1, I2, or I3, respectively. Table 4 shows the truth table of the quaternary 4 × 1 multiplexer.
The realization of our proposed quaternary reversible 4 × 1 multiplexer circuit is illustrated in Figure 5a. As shown in the figure, we used four quaternary 1-qudit Shift gates and four quaternary 3-qudit Controlled Feynman gates. In this realization, the main inputs are I0 to I3, and one 0 constant input is required. The selector is A, and the main output is O. The circuit produces five garbage outputs that are Q0 to Q3 and P. The output P is equal to the selector A, and the outputs Q0 to Q3 are equal to the inputs I0 to I3, respectively. In this circuit, when the selector A is equal to 0, the controlling value of the first Controlled Feynman gate is 3, and the output O is equal to I0. If A is equal to 1, the second Controlled Feynman gate is 3, and the output O is I1.
Moreover, when the selector is equal to 2 and 3, the output O is equal to I2 and I3, respectively. The realization of this circuit using quaternary Shift and M-S gates is shown in Figure 5b. In this figure, red boxes depict quaternary Controlled Feynman gates. Generally, four quaternary Shift gates and twenty-four quaternary Muthukrishnan-Stroud gates were used. Therefore, the quantum cost of the proposed quaternary reversible 4×1 multiplexer circuit is 28. It is worth mentioning that, in a multiplexer circuit, it is not necessary to restore the input I at the output Q. So, we can remove the red Muthukrishnan and Stroud gates in this realization. The quantum cost can be decreased by 24. In both suggested ways, the number of constant inputs is 1, and the number of garbage outputs is 5.
Our proposed quaternary reversible 4 × 1 multiplexer can be used to construct a 16 × 1 multiplexer. For designing this multiplexer, 16 inputs, two selectors, and one output are necessary. The truth table of this circuit is shown in Table 5. Only the selected input is gated to the output O for a given selector combination of A and B.  Figure 6a shows the logical architecture of the proposed quaternary 16 × 1 multiplexer using 4 × 1 multiplexer. As shown, five 4 × 1 quaternary multiplexers are required. In this design, the first inputs of the first-row multiplexers are activated when input B is equal to 0. Activation of the second inputs of multiplexers occurs when input B is equal to 1. If B is equal to 2 and 3, the third and fourth inputs of multiplexers are activated, respectively.
Moreover, the output of the first multiplexer is gated on the main output O when the selector A is equal to 0. If A is equal to 1, the main input is sent to the main output by the second multiplexer. When A is equal to 2 and 3, the output of the third and the fourth multiplexers are gated on the output O, respectively. Figure 6b illustrates the realization of the proposed quaternary reversible 16 × 1 multiplexer using a 4 × 1 multiplexer. The red boxes indicate our proposed quaternary reversible 4 × 1 multiplexer. In this circuit, there are five constant inputs, which are 0, and sixteen main inputs, which are shown by I0 to I15. The selectors are A and B. The main output is O, and the garbage outputs are P1, P2, O0 to O3, and Q0 to Q15. The outputs P1 and P2 are equal to A and B, respectively. Generally, the first realization of quaternary 3-qudit Controlled Feynman gates is used when inputs need to be restored. In this case, 20 quaternary Shift gates and 120 quaternary Muthukrishnan-Stroud gates are inserted in the circuit. Therefore, the quantum cost is 140. However, in multiplexer circuits, the inputs I0 to I15 are unnecessary as outputs, so it is possible to use the second realization of quaternary-controlled Feynman gates. Therefore, the second realization of quaternary-controlled Feynman gates can be used, and the quantum cost is 120.
We could also combine some gates in designing a quaternary reversible 16 × 1 multiplexer and present a circuit with a lower quantum cost. As shown in Figure 6c, an optimized multiplexer circuit can be realized. Eight quaternary Shift gates are used along with twenty quaternary Controlled Feynman gates. Due to the use of the second realization of Feynman gates, eight quaternary Shift gates and 100 quaternary Muthukrishnan-Stroud gates were used in total. This results in a quantum cost of 108. This innovative combination provides improvement over the first realization regarding the quantum cost. Moreover, in both realizations, the number of constant inputs is five, and the number of garbage outputs is 22.
Based on our proposed quaternary reversible 4 × 1 multiplexer, we proposed a generalized quaternary reversible n×1 multiplexer circuit, shown in Figure 7. Hence, our design is scalable. A quaternary n×1 multiplexer circuit consists of n = 4 m inputs, m selectors, and only one output. In this circuit, m rows of 4 × 1 multiplexers are needed. The first row requires 4 m−1 multiplexers, the second row requires 4 m−2 multiplexers, and the m row requires one multiplexer. Therefore, we can determine the number of 4×1 multiplexers needed to design our proposed n×1 multiplexer using geometric series formulas. The number of multiplexers is shown 46596 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.   by P in (2): The quantum cost of a quaternary reversible n×1 multiplexer is 24((n−1)/3), and it requires (n−1)/3 constant inputs and produces (3m + 4n−4)/3 garbage outputs. We can combine the quaternary 1-qudit Shift gates in each row according to the mentioned optimization approach in the last part. In this way, we have four 1-qudit Shift gates in each row. We also have 4 m−1 and 4 m−2 Controlled Feynman gates in the first and the second row, respectively. Moreover, in the last row, four Controlled Feynman gates are needed. Therefore, it can be concluded that in the proposed quaternary reversible n×1 multiplexer, 4((n − 1)/3) Controlled Feynman gates and 4m 1-qudit Shift gates are required, where n is the number of inputs and m is the number of selectors. Since   we used the second realization of the Controlled Feynman gate, the total quantum cost of this optimized circuit is 20((n−1)/3) + 4m.

B. PROPOSED QUATERNARY REVERSIBLE DEMULTIPLEXER CIRCUIT
A demultiplexer performs the opposite function of a multiplexer. A quaternary demultiplexer of 4 m outputs has mselect lines to send the input to the output. In a 1 × 4 demultiplexer, when the selector A is equal to 0, 1, 2, or 3, the output O0, O1, O2, or O3 is equal to I, respectively. Table 6 shows the truth table of the 1 × 4 quaternary demultiplexer.
In Figure 8a, we show the realization of our quaternary reversible demultiplexer circuit. Four quaternary 1-qudit Shift gates and four quaternary 3-qudit Controlled Feynman gates are exploited in this design. The main input is I, which requires four constant inputs, all of which are 0. The selector is A. O0 to O3 are the main outputs, and P and Q are the garbage outputs are equal to A and I, respectively. The first Controlled Feynman gate with a controlling value of 1 is applied when the selector is equal to 0, and the input I is sent to O0. This circuit applies the controlling value of the second Controlled Feynman gate when the selector A is equal to 1, and the input I is sent to O1. If the selector is equal to 2 or 3, the outputs O2 and O3 are equal to the input I, respectively. Figure 8b shows how the proposed circuit is realized using quaternary Shift and M-S gates. In this design, quaternary Controlled Feynman gates have shown by red boxes.
As a result, the quantum cost of the proposed quaternary reversible 1 × 4 demultiplexer circuit is 28. Considering that, in the multiplexer circuit, the input I does not need to be restored at the output Q, the red box can be removed, and the quantum cost is decreased by 24. In both cases, the number of constant inputs is four, and the number of garbage outputs is two.
We can also use our proposed quaternary 1 × 4 demultiplexer to construct 1 × 16 demultiplexer. In this kind of demultiplexer, one input, two selectors, and 16 outputs are needed. The truth table of this circuit is shown in Table 7. The input is gated to the selected output based on a given combination of selectors of A and B.
The logical architecture of the proposed quaternary reversible 1 × 16 demultiplexer, using 1 × 4 demultiplexer, is shown in Figure 9a. As can be seen, it requires five quaternary 1 × 4 demultiplexers. In this design, when the selector A is equal to 0, the main input is gated on one of the outputs in the first demultiplexer. One output of the second multiplexer is gated when selector A is equal to 1. In the third and fourth multiplexers, one output is gated if selector A is equal to 2 and 3, respectively. When the input B is equal to 0, the first input of the second row demultiplexers is activated. If the input B is equal to 1, then the second input of demultiplexers is activated. Moreover, when B is equal to 2 and 3, demultiplexers' third and fourth inputs are activated, respectively.
The realization of the proposed quaternary reversible 1 × 16 demultiplexer using 1 × 4 demultiplexer is shown in Figure 9b. In the figure, red boxes show our proposed quaternary reversible 1 × 4 demultiplexer. The main input is I, and it requires twenty constant inputs, which are 0. The selectors are A and B. The main outputs are O0 to O15, and it produces seven garbage outputs that are P1, P2, I, and from R0 to R3. The outputs P1 and P2 are equal to the selectors A and B, respectively. Generally, since input restoration is not necessary, the second realization of quaternary Controlled Feynman gates can be exploited. In this way, the proposed circuit includes 20 quaternary Shift gates and 100 quaternary Muthukrishnan-Stroud gates, and the quantum cost is 120.
We also could use a lower number of gates for designing the quaternary reversible 1 × 16 demultiplexer and present a lower quantum cost demultiplexer circuit. The realization of the proposed optimized circuit is shown in Figure 9c. As can be seen, twenty quaternary Controlled Feynman gates and eight 1-qudit Shift gates are used. Since inputs restoration is not necessary, the second realization of quaternary Controlled Feynman gates is used, and there are eight quaternary Shift gates and 100 quaternary Muthukrishnan-Stroud gates in the proposed design, so the quantum cost is 108. Compared to our first proposed quaternary 1 × 16 demultiplexer, we improved the quantum cost using this innovative combination. The numbers of constant inputs and garbage outputs for both realizations are 20 and 7, respectively.
In addition, our proposed quaternary demultiplexer is scalable. A generalized quaternary reversible 1×ndemultiplexer 46598 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  circuit, based on quaternary reversible 1 × 4 demultiplexer, is suggested. In a quaternary 1×n demultiplexer circuit, there are one input, m selectors, and n = 4 m outputs. Generally, m rows of 1 × 4 demultiplexers are needed. It is necessary to use one demultiplexer in the first row, four demultiplexers in the second row, and 4 m−1 demultiplexers in the last row. Figure 10 shows the logical structure of the proposed 1×n demultiplexer. We also can use the geometric series formula to determine the number of 1 × 4 demultiplexers that are needed to design our proposed 1×n demultiplexer. Using (3), we can determine the number of demultiplexers, represented by Q.
The proposed quaternary reversible 1×n demultiplexer circuit requires 4((n−1)/3) constant inputs and produces (n + 3m−1)/3garbage outputs, with a quantum cost of 24((n−1)/3). Based on the optimization approach discussed in the previous section, the quaternary 1-qudit Shift gates in each row can be combined. As a result, each row contains four 1-qudit Shift gates. There are four and sixteen Controlled Feynman gates in the first and the second row, respectively, and 4 m−1 Controlled Feynman gates in the last row. Therefore, it can be concluded that there are 4((n−1)/3)Controlled Feynman gates and 4m 1-qudit Shift gates in the proposed quaternary reversible 1×n demultiplexer, with n outputs and m selectors. Since we use the second realization of the Controlled Feynman gate, this optimized circuit has a total quantum cost of 20((n−1)/3) + 4m.

IV. RESULTS AND EVALUATIONS
In this section, we analyze our proposed realizations of quaternary reversible multiplexer and demultiplexer circuits and calculate the improvement rate with respect to the best results in the literature. We also compare the proposed circuits with the existing designs in [40], [41], and [42] in terms of quantum cost, number of garbage outputs, and number of constant inputs, which are the most critical parameters in reversible circuit design and are used to evaluate reversible circuits. Lower values of these parameters lead to a more efficient circuit design.
In the following parts, the first comparison is for our proposed quaternary reversible demultiplexer, and the second comparison is for our proposed quaternary reversible demultiplexer. According to Table 8, whereas both designs of quaternary reversible 4×1 multiplexer circuits have the same number of garbage output and constant input, the proposed circuit outperforms the existing design presented in [41] in terms of quantum cost because of its lower values for this parameter. Table 8 also illustrates that our proposed quaternary reversible 16 × 1 multiplexer circuit has great improvement in terms of quantum cost, the number of garbage outputs and the number of constant inputs compared with its counterparts in [40], [41], and [42]. Therefore, it can be concluded that our proposed design of the 16 × 1 multiplexer in this paper is also much more efficient than the previous designs in [40], [41], and [42]. Table 9 shows the comparison between our proposed quaternary reversible 1 × 4 demultiplexer and its counterpart in [41]. As can be seen, although both 1 × 4 demultiplexer circuits require four constant inputs and produce two garbage VOLUME 11, 2023 outputs, our proposed design has a quantum cost of 24, and the demultiplexer realization in [41] has a quantum cost of 58.
Owing to using lower values of quantum cost, our proposed quaternary reversible 1 × 4 demultiplexer is more efficient 46600 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.    than the existing design in [41]. The results given in Table 9 show that our proposed quaternary reversible 1 × 16 demultiplexer has 20 constant inputs, even garbage outputs, and a quantum cost of 108. It is obvious, by Table 9, that our proposed design has a less quantum cost, garbage output, and constant input than the previous designs in [40], [41], and [42]. Since reversible circuits are more efficient when these parameters are minimized, the quaternary reversible 1 × 16 demultiplexer in this study is more efficient than its counterparts in [40], [41], and [42].
It is to be noted that there is no overhead in the proposed designs. One of the advantages of the proposed designs is that they have no overhead. In addition, the proposed approaches have applications in designing arithmetic circuits (e.g., ALU).

V. CONCLUSION
A new quaternary reversible 4 × 1 multiplexer circuit, based on quaternary 1-qudit Shift gates, 2-qudit Muthukrishnan-Stroud, and 3-qudit Controlled Feynman gates, has been presented in this paper. The proposed 4 × 1 multiplexer has been exploited to design a quaternary reversible 16 × 1 multiplexer circuit. The proposed design is scalable for n×1 multiplexer. Moreover, we have introduced a new scalable realization of 1 × 4 demultiplexer to design our proposed quaternary reversible 1 × 16 and 1×n demultiplexers. The proposed quaternary reversible circuits in the present study significantly decrease quantum cost, the number of constant inputs, and the number of garbage outputs. Since designing a reversible circuit with lower values of these parameters leads to increased efficiency, it can be concluded that our proposed multiplexer and demultiplexer circuits are more efficient with respect to their existing counterparts. Our designs have no overhead compared to the existing designs to be reported. An interesting future work is the study of possible applications of our proposed circuits in designing complex systems.
VALENTINA CIRIANI (Senior Member, IEEE) received the Laurea and Ph.D. degrees in computer science from the University of Pisa, Italy, in 1998 and 2003, respectively. She is currently an Associate Professor in computer science with the Department of Computer Science, University of Milano, Italy, where she is co-responsible of the FALSE Laboratory. Her research interests include logic synthesis and testing for emerging technologies, the VLSI design of low power circuits, and circuit design for security protocols. She has authored or coauthored more than 100 research papers, published in international journals, conference proceedings, and books chapters.
TOMMI MIKKONEN is currently a Full Professor in software engineering with the University of Jyväskylä, Finland. In addition to his academic position, he has been a Principal Scientist with Nokia and a Visiting Professor with Sun Microsystems Research and Mozilla. His research interests include the IoT, software development methods, software architecture, and software engineering for quantum computing. He is the year 2017 Open World Hero, nominated by the Center of Open Source Software in Finland.

MAJID HAGHPARAST (Senior Member, IEEE)
is currently a Researcher with the University of Jyväskylä, Jyväskylä, Finland. He is an Associate Editor of the Cluster Computing (Springer) and Journal of Computational Electronics (Springer). He is also an Editorial Board Member of the Optical and Quantum Electronics (Springer). He has been a supervisor/an advisor of more than 150 M.Sc. and ten Ph.D. students. He is an invited referee for more than 30