A Five-Level Switched-Capacitor Based Transformerless Inverter With Boosting Capability for Grid-Tied PV Applications

Transformerless grid-connected inverters have attained a lot of research interest in renewable energy interface applications, due to certain promising properties like greater efficiency, light weight, affordable price, and tolerable power density. Among various types of transformerless grid-tied photovoltaic (PV) inverters, multilevel inverters (MLIs) are mostly popular due to their ability to transmit reactive power, small filter size for reducing total harmonic distortion (THD) and their common-ground (CG) configuration to mitigate the detrimental leakage current due to the parasitic capacitances of the PV array. Again, among different types of MLIs for PV systems, switched-capacitor (SC) based multilevel inverter topologies are the burning topic in current decades due to their single source requirements for producing multilevel output voltage. However, for mostly used single-phase five-level inverters, most of the existing SC based topology requires at least two SCs for power conversion. In this paper, a five-level transformerless inverter based on a single SC is proposed, requiring only seven switches, no diode, a single capacitor, and one dc voltage source. The proposed transformerless MLI also has auto-boosting capability. Notably, the number of power switches operating at high frequency is limited to three, which lowers down the switching losses of the inverter. Rather than a new single SC based five-level transformerless inverter topology, a control scheme is also presented to inject a precisely regulated current into the grid that can govern both the active and reactive power support modes. In-depth comparisons between the proposed and cutting-edge MLIs are also provided. All these claims are validated through MATLAB/Simulink and PLECS computer simulation environments. A laboratory-scaled prototype is also built and tested to support the simulated claims further and validate the effectiveness and feasibility of the proposed five-level transformerless inverter topology.


I. INTRODUCTION
DUE to the rising need for energy and the depletion of fossil fuels, renewable energy based solar and wind power systems have recently attracted a lot of attention [1]. To integrate renewable energy sources with the existing power grid, transformerless inverters (TIs) are considered as a promising The associate editor coordinating the review of this manuscript and approving it for publication was Ahmed F. Zobaa . technology due to their more compact size, financial viability, and higher efficiency [2]. In terms of TIs, leakage current is one of the most concerning issues, since there is no galvanic isolation between the input and output sides of the inverter. A stray capacitor is connected to the photovoltaic (PV) module in a conventional transformerless PV system. This capacitor produces a floating common mode voltage along with leakage current that poses a safety risk and causes electromagnetic interference (EMI) [3], [4], [5]. So, it is crucial to stop or suppress this leakage current since it can affect personal safety and result in worsened power quality. In order to combat the issue, several research works have been conducted which are not only suppressing the leakage current [6], [7], but also reducing the number of devices (power switches, capacitors, inductors, and diodes) [8], [9], [10], [11], [12], [13] in their proposed inverter topology for improved electrical and thermal efficiency. Most of these literatures reduce the leakage current via: • Coupling the grid neutral to the midpoint of dc-link bus; • Keeping the common mode voltage constant; • Establishing a common ground (CG) connection between the grid's neutral and the PV array's negative terminal.
By utilizing the first and second solutions, the leakage current could be suppressed on a tolerable scale [14], [15], but these solutions can't be used to set the leakage current to zero. Only the last solution, which is to utilize CG architecture, can set the leakage close to zero. However, CG architecture requires complex design to be implemented. If the common mode voltage of the inverter could be stabilized, the flow of leakage current could also be minimized.
Other than leakage current, the recent trend starts with utilizing MLIs in single-phase inverters due to their higher efficiency, reactive power injection capability, low harmonic profile, smaller filter bank, and so on. The existing MLIs can be stacked into three categories: cascaded H-bridge (CHB) [16], neural-point clamped converters (NPC) [17], and flying capacitor (FC) inverters [18]. For these types of MLIs, a huge number of semiconductor devices and isolated dc sources are required, which increases the control complexity, switching loss, gate driver design challenges as well as the price and size of the whole system.
As a solution to the drawbacks of the conventional MLIs, SCs are being utilized for various transformerless PV interfaced grid-tied systems. It creates a greater difference in terms of control scheme, voltage balancing, lower power devices count, and others rather than conventional MLIs. The SC based topology doesn't require any special control scheme to balance the capacitor voltage [19]. Again, some SC-based topologies [20], [21], [22], [23], [24] can boost the input dc voltage in a specific range. Actually, the SC creates a virtual dc source by charging the capacitor from dc bus and discharges SC in series or in parallel connecting with the dc source for a certain period of time. Thus, SC based inverter doesn't need any extra control scheme to balance the capacitor voltage compared than conventional NPC and FC based MLIs.
In [25], a SC based MLI has been proposed. The topology solves the problem of voltage balancing as well as by utilizing a large number of SCs, it can create higher level output voltages. But the topology is not flexible enough to deliver reactive power. In [26], another topology is proposed, but it suffers from voltage balancing problem due to using series capacitors in parallel with the dc voltage source. A noble SC based topology is proposed in [27]. The topology is truly based on SC and the topology also features voltage boosting ability with self-voltage balancing of the SCs. It also solves the problem of reactive power transmission. But only for five-level voltage output, the topology requires eight power switches, one diode and two SCs. As a result, the topology suffers from semiconductor device losses as well as poor power efficiency.
The topology in [28] features a five-level output voltage, but it also suffers from an increasing number of power semiconductor devices. The topology uses nine power switches for only five-levels of output voltage. It also increases semiconductor conduction as well as switching losses. A new type of SC based topology is proposed in [29]. It has the ability to output a five-levels voltage with only six power switches, one diode, and two SCs. Undoubtedly, it reduces power loss. The main disadvantage of this topology is its inability to boost-up the output voltage. As a result, a higher rated boost converter is required to boost-up the input dc voltage compared to a topology that has voltage boosting capability.
The topologies in [30] and [31], which have eight semiconductor switches, also suffer from significant switching and conduction losses. One of them also suffers from high leakage current problem, which is a huge safety concern in the case of TIs. Some recent literatures [32], [33] show some extraordinary results in terms of voltage boosting capability. But the limitation of using excessive power semiconductor switches remains true in these topologies. Moreover, these topologies need four capacitors for only a five-levels of output voltage. These increasing amounts of capacitor not only make the inverter circuit bulky but also increase the risk of capacitor failure and overall cost of the inverter.
Another well-balanced topology has been proposed in [34]. The topology utilizes six power switches, one diode, three SCs, and a single dc source. The topology also features active and reactive power supplying capability. A common ground architecture along with a simple control scheme for the topology is also proposed. But again, it uses three SCs for only five-level output voltages. Moreover, four of the six switches in the topology run at a higher frequency, creating higher switching losses. The topology in [35] has the same device count as the previous topology. It also comes with three SCs, which not only require bulky circuit design but also create a risk of capacitor failure in the long run.
A brief review of MLIs based on reduced switch for renewable energy interfacing is found in [36]. In the literature, SC based structure had also been addressed. In that SC based topology, it uses several SCs and H-bridge for voltage invitation. It reduces the efficiency and create voltage stress on power switches.
In [37], topology based on single switch capacitor have been addressed. It serves different type of purposes, i.e., voltage boosting, single SC, and lower power device count. But to control the inverter, a complex control scheme is needed to balance the floating voltage of the SC. Another single SC based topology was proposed in [38]. It utilizes, four power VOLUME 11, 2023 switches, single diode, and single SC. But it can create only three level of output voltages which is not the proper use of the single SC. Advanced version of this topology is presented in [39]. The topology utilizes four power switches, no diode and a single SC. But it still not capable enough to create multiple stages of output voltage. The topology is designed only for three level of output voltages.
The major drawbacks of the above-mentioned SC based MLIs are summarized as: • Not having proper protection against floating common mode voltage and leakage current.
• Not having active and reactive power supplying ability.
• Larger number of semiconductors switching devices count.
• Not having boosting ability and self-voltage balancing capability utilizing SC based topology.
• Increasing number of SCs only for five-level voltage output.
• Having some complex control technique to balance the capacitor voltage. Based on the preceding observations, it can be concluded that the mentioned topologies each have their own benefits and drawbacks for various grid-tied PV application scenarios. To address all of these issues and add new features to grid-connected PV applications, this paper proposes a new SC based transformerless inverter topology with minimum leakage current. By utilizing the SC, the proposed inverter is also capable of boosting the output voltage. The following are the key aspects of the proposed transformerless inverter topology: • Stable common mode voltage and low leakage current. • Minimum number of power semiconductor devices to reduce switching and conduction losses during power conversion.
• Only one SC is used for a five-level inverter.
• Self-voltage balancing and boosting capabilities.
• Simple closed-loop control strategy to precisely deliver active and reactive power to the grid. The rest of the content of this paper is organized as follow: Section II presents the proposed transformerless inverter including the circuit configuration, operating modes, and self-voltage balancing capability. The modulation technique, control strategy and design guideline of the transformerless inverter are provided in Section III. The simulated performance, experimental validation, and power loss along with thermal analysis are shown in Section IV. In-depth comparison between the proposed inverter topology and cutting-edge MLIs is carried out in Section V. Finally, concluding remarks are provided in Section VI.

II. PROPOSED TRANSFORMERLESS INVERTER
The primary goal of the proposed transformerless inverter is to suppress leakage current. A single SC is used to make the control and modulation strategy simpler. Additionally, the proposed transformerless inverter design includes built-in voltage boosting capabilities, making it a potential contender for transformerless grid-tied PV applications. Fig. 1 depicts the internal structure and circuit configuration of the proposed transformerless inverter. The proposed transformerless inverter consists of seven IGBTs as power semiconductor switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and S 7 ), one single SC (C 1 ) and a single dc source (V dc ). On the PV side, there exists PV arrays, MPPT, and dc-dc boost converter for delivering the maximum power and ensuring voltage stability. In the grid side, an inductor (L 1 ) along with a grid equivalent source (V g ) are presented. And lastly, the leakage current path is also shown in Fig. 1.

A. CIRCUIT CONFIGURATION
As depicted in Fig. 1, switch S 3 is responsible for charging the capacitor over a period of time. By utilizing capacitor C 1 , switches S 1 , S 5 , S 4 and the single dc source, 2V dc voltage can be accrued at AB terminal of the inverter. As a result, the output voltage is twice compared to the input voltage.
During the V dc , −V dc and zero state output voltage operations, the capacitor charges itself to its maximum limit. In the period of 2V dc and −2V dc operations, the capacitor discharges itself to the utility grid. It is notable that, the capacitor gets enough time to charge itself and discharges only 2/5 th of a full cycle. But two discharging periods are not continuous. After one discharging period being over, the capacitor charges itself back and discharges again in the next cycle. As a result, no extra control scheme is required to balance the output voltage of the SC.

B. OPERATING MODES
The appropriate switching states for the five-level operations of the proposed transformerless inverter, as well as the operation for charging and discharging of the capacitor, are shown in Table 1. Different operating modes of the proposed transformerless inverter are illustrated in Fig. 2. It also renders the capacitor's charging and discharging paths.

1) MODE 1
In this operating mode, shown in Fig. 2(a), the output voltage, V AB is twice the input voltage, V dc . During the operation, switches S 1 , S 4 and S 5 are in conduction mode, while other switches are in blocking mode. In this mode, capacitor C 1 is in a discharging state, establishing a series connection with the input dc voltage source, V dc . Due to same voltage level as input dc voltage source of the capacitor, total output voltage at terminal AB gets twice compared to input dc voltage. Mathematically, the output voltage, V AB can be represented as: During this operating mode, as depicted in Fig. 1(b), the output voltage, V AB remains the same as the input dc voltage, V dc . In this operating state, switches S 4 , S 5 , S 2 remain turned on while other switches, excluding switch S 3 , remais turned off. Switch S 3 creates a charging path for the capacitor. The current from the input dc source is divided into two sections and feed through the capacitor as well as output gird side at the same time. So, the voltage of the SC remains the same as the input dc voltage. Mathematically, the output voltage of mode-2, V AB can be represented as: During the third operating mode, as illustrated in Fig. 1(c), the output voltage, V AB is nullified as the output grid circuit is detached from the input source side. From Table 1, it can be clearly observed that, in this operating mode, only switches S 2 and S 3 remain turned on while the other switches are in turned off state. Switches S 2 and S 3 ensure that the capacitor is in a charging state while the other part of the circuit remains disconnected from the grid. So, the voltage of the SC remains the same as the input dc voltage. Mathematically, the output voltage of mode-3 can be represented as:

4) MODE 4
In the fourth operating mode, as shown in Fig. 1(d), the output voltage, V AB remains the same as the input dc voltage but in reverse polarity. In this operating mode, switches S 2 , S 3 , S 6 and S 7 remain turned on while the other switches remain turned off. As a result, the capacitor gets into a charging state while the input dc source supplies current to the grid as well as the SC simultaneously. In mode-4, the voltage of the SC remains the same as the input dc source voltage. Mathematically, the output voltage of mode-4, can be represented as: In the final operating mode, as depicted in Fig. 1(e), the output voltage, V AB is the twice of the input source voltage, V dc and the polarity is reversed. During this operating cycle, switches S 1 , S 6 and S7 are in turned on state while the other switches are in turned off state. This combination of switching sequences creates a current path for flow from the source to the load while making a series connection with the SC. As a result, the capacitor goes into discharging mode, and the total output voltage gets doubled as the input dc voltage. The capacitor delivers the same voltage level as input dc voltage obtained from the source in mode-4. Due to the switching sequences of switches S 6 and S 7 , the polarity of the output voltage gets reversed, thus delivering appropriate current to the grid. The inverter output voltage of this mode can be represented as: Thus, the modes described above get repeated periodically, ensuring the correct output voltage and frequency according to the requirements of the power grid for grid-tied operation.

C. SELF VOLTAGE BALANCING CAPABILITY
As seen from Fig. 2 and Table 1, the SC is connected to the dc source in parallel during mode-2, mode-3 and mode-4. From the mathematical equations (2), (3), and (4), it is also clear that the capacitor can be charged up to the input source voltage level. And only during mode-1 and mode-4, the capacitor discharges itself through the grid by connecting in series with the input dc source. Thus, the output voltage gets doubled compared to the input source voltage. That means the voltage of SC can be balanced automatically in a single fundamental period without the use of an additional complex control scheme, modulation technique, or external circuits.

III. MODULATION, CONTROL STRATEGY AND DESIGN GUIDELINE OF THE PROPOSED INVERTER
The gate signal of the switches of the proposed transformerless inverter is based on level shifted phase-disposition carrier pulse width modulation (PDCPWM). PDCPWM technique has been widely applied and preferred for the MLIs due to lower THD of output voltage, less computational burden and easier implementation in DSP and/or FPGA. PDCPWM requires four identical carrier signals and a single modulating signal to generate the gate pulses for the five-level output voltage. The gate pulses are produced after comparing the corresponding carrier signals with the modulating signal. On the other hand, a simple PI controller-based control scheme is used to validate the active and reactive power supply ability and grid-connected operation of the SC based proposed transformerless inverter.    Fig. 4. To produce the final gate signals of the proposed transformerless inverter, three additional comparators are also being considered to detect the shifting from the positive half cycle to the negative half cycle of the modulating signal. The modulation index for the operation is considered as 0.98.

A. MODULATION TECHNIQUE
From Table 2, the values of certain essential constants X K 1 , X K 2 and X K 3 can be found, which are used to determine the current position of the modulating signal during the shift of each triangle wave and the resulting three individual outputs named as Y a , Y b , Y c in Fig. 4. Additionally, four digital NOT gates, including one OR gate and one AND gate are required to design the PWM pulse generation scheme to obtain the gate signals of the proposed transformerless inverter. Fig. 4 is very self-explanatory and quite easy to understand as it deals with the basic digital logic gates. The binary expression for an individual gate signal can be represented as follows: where ''×'' and ''+'' correspond to the digital logic ''AND'' and ''OR'' gates, respectively. The corresponding gate pulses of (6)-(12) are depicted in Fig. 5. As the generation of the gate pulse strategy is based on PDCPWM and basic logic gates, the implementation of the gate pulses in hardware is not only simpler but also requires less computing power of the onboard processor of the inverter. It is mention worthy that, in hardware there requires a dead time between two opposite gate signals for the power switches of same leg which is not mentioned in this section as this section is based on ideal condition. Without a dead band, the current flowing path gets sorted and causes a catastrophic failure of the inverter. It is notable from Fig. 5 that only three of the power switches, S 1 , S 4 and S 7 run at higher frequency as same as the carrier frequency while the rest of the power switches run at line frequency switching speed as depicted in Fig. 5 (b), (c), (e) and (f). Switch S 6 and S 7 are practically VOLUME 11, 2023 FIGURE 5. Gate pulses of the power switches S1 -S7 (a-g) of the proposed transformerless inverter.   Fig. 2(c). Fig. 6 shows a simple dq reference frame-based control strategy to connect the inverter with the power grid with active and reactive power suppl capabilities. The controller is designed to push the desired amount of current to the grid at the time of unity, leading and lagging power factor operations. A phase locked loop (PLL) is integrated to determine the alpha and beta values of the voltage and current by sensing the grid voltage, V g and inverter current, I inv respectively. Then the corresponding alpha and beta values of voltage and current are fed to an αβ to dq reference frame converter. The output of the αβ0 to dq converters is used to determine the phase angle of voltage and current. On the other hand, a simple PI controller is used to determine the feedback angle of the controller.

B. CONTROL STRATEGY
In the main controller section, previously acquired V d , V q , I d , and I q along with wt are used to compare the instantaneous value to the reference one. C a and C r are used to control the active and reactive currents pushing to the grid. Here, f gird is the frequency of the grid, and V ind is the value of filter inductor connected in series with the grid. After the feedback angle is calculated, the value of dq frame is converted back to αβ reference frame, producing the required modulation signal, M . The modulation signal, M is then used to generate the gate pulses by utilizing the PDCPWM technique and some digital logic conversion schemes, which are already discussed in section III-A. The output of the dq to αβ reference frame, M * must be divided with the input dc voltage as to keep the amplitude of the modulation signal in between −1 to 1.

C. DESIGN GUIDELINE OF THE PROPOSED TRANSFORMERLESS INVERTER 1) SC DESIGN
The maximum discharge time interval of the SC as well as the voltage difference (V C1 ) across SC must be taken into account when choosing an appropriate value for the SC. The following equation can be stated by taking into consideration the capacitor's longest discharge time interval (δ, γ ): where, C 1 is the value of SC and i C1 (t) is the instantaneous current through the SC. Taking into account, P out as the maximum output power injected into the grid and then i C1 (t) can be directly applicable to the i g by determining the capacitor's discharge duty cycle. As a result, the equation for SC could be addressed as follow: where, V C in , g T , and D m are the input dc voltage, grid fundamental period, and the switching duty cycle at each discrete switching instant, respectively. Utilizing equations (13) and (14) the optimum value of SC could be obtained.

2) FILTER DESIGN
To determine the value of filter inductor L g , the average current, I g,avg , passing through the inductor must be taken  into consideration.
where, T S , v L g (t), i g (n) are the value of each switching period, instantaneous voltage across the filter inductor, and initial stored current at the very begging of each sampling period, respectively. Thus, the minimum required value of L g could be calculated by: where, V inv , f sw , and I g,max are the inverter output voltage, switching frequency, and maximum allowable ripple current across the filter inductor. Thus, by utilizing equations (15) and (16) the minimum value of filter inductor could be calculated.

IV. PERFORMANCE EVALUATION OF THE PROPOSED TRANSFORMERLESS INVERTER
The performance of the proposed transformerless inverter is evaluated both in simulation and in hardware experiments. The overall performance is evaluated in MATLAB/Simulink environment, and the power loss analysis is conducted in PLECS simulation software. A reduced scale hardware prototype of the proposed transformerless inverter is also built and tested in laboratory. The simulation and experimental parameters are provided in Table 3.

A. SIMULATIONS RESULT ANALYSIS
The output voltage of the proposed five-level transformerless inverter consists of five individual voltage steps. Fig. 7 (a), (d) and (g) show output voltages of the proposed transformerless inverter while varying the SC value as 1000µF, 2200µF and 3300µF, respectively. The difference is clearly visible, as the 1000µF capacitor holds the charge for less amount of time as compared to 2200µF and 3300 µF, respectively. As a result, in a half cycle, the SC voltage VOLUME 11, 2023 drops at a significant level utilizing 1000µF SC. The lowest voltage obtained from the 1000µF SC is 164V while the dc link voltage still exists at 200V for a rated output power of 2 kW for the proposed transformerless inverter.
The output current waveforms of the proposed transformerless inverter are shown in Fig. 7(b), Fig. 7(e), and Fig. 7(h) with SC = 1000µF, 2200µF, and 3300µF, respectively. The current THDs are recorded at 1.62%, 1.27%, and 1.03% for SC = 1000µF, 2200µF, and 3300µF, respectively. The capacitor voltages are shown in Fig. 7(c), Fig. 7(f), and Fig. 7(i) for SC = 1000µF, 2200µF, and 3300µF, respectively. The capacitor voltage ripple is lowest for SC = 3300µF. With the increase of capacitor value, the voltage ripple and current THD decrease. The lowest amount of injected current THD is recorded for SC = 3300µF. From Fig.7(i), it can be noted that, while utilizing 3300µF SC, the lowest voltage of the SC is found to be 195V which is absolutely acceptable as compared to 200V input supply. Thus, 3300µF SC is the best suitable for the proposed transformerless inverter. Fig. 8 depicts the dynamic response due to variation of input dc-link voltage while the inverter is running in islanded mode. In first stage, the input voltage drops about 50V from 200V peak and the inverter output voltage also drops twice as compared to the input dc voltage. The reason for the twice voltage drop is that the SC works as a virtual dc source which stores the same energy as the input dc source for a period of time. In this stage, the output voltage decreases to V 3 = 300V from the initial 400V dc-link of the inverter. Notably, a 3300µF capacitor is used while testing the dynamic response of the proposed transformerless inverter at islanded mode. The capacitor voltage ripple as depicted in the zoomed view of Fig. 8(a) is limited to 5V only. In the third stage, the input dc voltage jumps from 110V to 200V peak. At the same time, the capacitor voltage also reaches up to 200V peak to maintain the same voltage level as input dc voltage. The inverter voltage also gets double and finally reaches at 400V peak. The zoomed close-up view during the transition period is also shown is Fig. 8(b).   Fig. 9(b) depicts the capability to supply reactive power to the grid with the proposed transformerless inverter utilizing the presented control scheme.
During active and reactive power supply, the inverter is injecting 10A peak current into the grid. Fig. 9(c) is based on the transition from active power state to reactive power state. Using the presented controller, it is also possible to switch between active and reactive power states simultaneously. The response time of the controller is also low. It takes around 0.005 seconds to transition from an active to reactive power state. It is also possible to transmit different amount of power during unity, leading, and lagging power factor operations of the grid. Fig. 10 depicts the dynamic power control capability of the proposed transformerless inverter. Fig. 10(a) shows the real time reactive power flow. The reference power is set to be stepped at 1 second and 3 second. The inverter controller is keeping the output power at reference level which shows a moderate result. The controller needs approximately one fourth of a second to track down the reference output power precisely. Fig. 10(b) also shows a promising result in terms of active power supply. The transition is set to drop around 600W of active power and again catch up to the reference level, still maintaining the output voltage at a constant level.
The initial reference reactive power was set at around 1600W. At the start of the inverter, the total power at the output was zero. But after around 0.25 second from the start, the inverter catches down to the reference reactive power level by using the presented controller. It is notable that, in linear operation mode, the reference power is tracked down very smoothly. But on a sudden change of power, it takes some time to settle down the inverter to its tracking point. Overall, the controller is capable of supplying both active and reactive power into the grid utilizing the proposed transformerless inverter. Table 3 summarizes the simulation and experimental parameters of the proposed transformerless inverter. It is worth mentioning that in hardware, there are a few parameters that are not required in a computer simulation environment, i.e., dead time. In simulation, opposite switches change its state immediately. But in hardware, there need some time  to change the transition state of opposite switches. That's why dead-band is considered in the hardware implementation only. Fig. 11 illustrates the leakage current waveform of the proposed transformerless inverter. During Mode-1, Mode-4, and Mode-5, there exists a path to flow leakage current from grid to the PV array. On the contrary, during Mode-2 and Mode-3, the leakage current is totally suppressed. The RMS value of leakage current is found around 15.33mA, which is quite acceptable in terms of single-phase transformerless inverter. Fig. 12 depicts the voltage and current stress across individual switches of the proposed transformerless inverter. It is quite clear from Figs. 12 (a), (b), and (c) that, switch S 1 , S 2 , and S 3 are operating at V dc voltage whereas from Figs. 12 (d) -(g) it is clear that switch S 4 , S 5 , S 6 , and S 7 are operating at 2V dc voltage. The voltage and current waveforms of individual switches are considered at rated condition of the inverter. The current through the power switches is found 10A maximum at rated condition. As there is symmetry in voltage and current waveforms of the individual switches, the switch rating could easily be calculated for practical implementation.

B. EXPERIMENTAL VALIDATION
A reduced scale laboratory prototype is built and tested according to the experimental parameters of Table 3 to validate the performance of the proposed transformerless inverter. A photograph of the experimental test platform is shown in Fig. 13.
The proposed transformerless inverter consists of seven IGBTs, one capacitor, and seven gate drivers. 650V, 40A IKW40N65F5 IGBTs from Infineon Technologies were used to construct the inverter. The IGBT has its own anti-parallel body diode to prevent backward current flow. The TMS320F28335 DSP processor board is used as the main control board. The gate pulses from the DSP board get boosted up through the custom gate driver circuit designed specifically for the given IGBTs, utilizing TLP 250 optocouplers and B1212S-1W isolated dc-dc converters. The optocouplers ensure isolation between the low voltage DSP logic level circuit and high voltage gate side circuit of the IGBTs. A 15V dc supply is used to supply the gate driver of the IGBTs through lab bench power supply. A 4-channel oscilloscope (GDS-1104B) is used for capturing the experimental results. A 2.50µs dead time is considered for producing the gate signals of same leg IGBTs with a switching frequency of  8kHz. A programmable dc power supply is used here to provide the dc-link of the inverter. Fig. 14 depicts the experimental output voltage and current waveforms of the proposed transformerless inverter. The maximum output voltage for the reduced scale test setup is found to be 180V peak. For a certain linear load test condition, the peak of the current waveform is found around 5.20A. In Fig. 15, the capacitor voltage is shown along with the highest and lowest peaks of the switched-capacitor voltage. From Fig. 15, it can be observed that for a 100V input dc supply, the maximum SC voltage is around 93.6V and the lowest SC voltage is around 85.6V, respectively. The peak-topeak level of capacitor voltage fluctuates between 0V to 8V. The experimental result is relatively close to the simulated result. On the other hand, Figs. 16 and 17 show the gate pulses for the IGBTs of the proposed transformerless inverter, which seem the same as simulated waveforms of Fig. 5. It is noteworthy that the gate signals in Fig. 16 are running at a high frequency whereas the signal in Fig. 17 is running at a low frequency. The symmetrical gate pulses ensure the low power loss of the proposed transformerless inverter.
On the other hand, the experimental dynamic response of the proposed transformerless inverter is depicted in Fig. 18, which is the experimental validation of the simulated result of Fig. 8. In the first step, the dc input voltage drops from 95V peak to 80V peak. As a result, the peak of output voltage drops twice and decreases from 188V peak to 154V peak. In the second step, the dc input voltage drops by 45V again, and the output voltage peaks at around 64V. After that, the input voltage jumps back to 95V peak and so the output voltage also reaches around 185V peak. Fig. 19 shows the experimental validation of the reactive power supply capability of the proposed transformerless inverter. From the voltage and current phase shift of Fig. 19, it is clear that the proposed transformerless inverter delivers reactive power to the grid. The experimental validation matches the simulated results of Fig. 12, which provides the strong feasibility of the proposed transformerless inverter in terms hardware implementation.
Figs. 21 (a)-(c) show the experimental output voltage waveforms for SC = 1000µF, 2200µF, and 3300µF, respectively. Fig. 21 is the experimental validation of the simulated result of Fig. 7.
Leakage current flows due to unstable common mode voltage in the output terminal. Fig. 22 illustrates the experimental leakage current waveform of the proposed transformerless inverter. The experimental leakage current is found around 17.1 mA (RMS). The experimental leakage current waveform is quite similar to the simulated waveforms of Fig. 11.

C. POWER LOSS AND THERMAL ANALYSIS
Power loss and thermal analysis are considered the most critical factors for validating the inverter's performance. There are two types of losses occurring in a power semiconductor switch and they are the switching loss and conduction loss. But in high performance IGBT switches, there is an extra body diode to perform freewheeling operation. As a result, IGBT's anti-parallel diode loss must be addressed properly along with the loss of the IGBT switch. However, there exists a fast recovery diode that ensures significantly low turn-on diode losses, which can be neglected.
The overall conduction loss (P con ) for a single IGBT can be represented as:  where, v ce (t) , i c (t), v F (t) and i F (t) represent the instantaneous voltage across the switch, the instantaneous current through the switch, the instantaneous voltage across the body diode, and the instantaneous current through the body diode, respectively. By considering the seven switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and S 7 ), the overall conduction loss (P con total ) can be calculated as follow: Switching delays involving semiconductor devices result in switching losses, which are substantial sources of power VOLUME 11, 2023  loss. Switching loss happens when a switch's off-state voltage and current coincide with one another during state transition. The total switching loss (P sw ) can be expressed mathematically as follows: where, E on , E off and E rec are the switch turn-on loss, turnoff loss and diode turn-off loss in joule, respectively. These parameters should be taken from the datasheet of the specific switches while calculating the switching loss. The total power loss can be calculated as follow: P total = P con total + P sw (20) Figs. 23 and 24 show the loss distribution profiles of individual IGBTs and their corresponding body diodes. Overall loss analysis has been performed in PLECS simulation environment utilizing the above equations and lookup tablebased approaches. Datasheet of the corresponding IGBT, IKW40N65F5 is used to create the lookup table for calculating the turn on loss, turn off loss and diode loss, respectively.
The loss distribution profile of individual power switches has been considered for rated output power condition (2kW). It is clear from Fig. 23 that switch S 6 is facing most of the  losses in terms of IGBT only. The total loss of switch S 6 is found 2.13W while the lowest IGBT loss is found for switch S 3 which is only about 0.06W. As switch S 3 is used for only charging and discharging of the capacitor, it faces the lowest loss among all the power switches of the proposed transformerless inverter. Fig. 24 depicts the overall body diode loss of the power switches. It is notable that the body diode of switch S 5 encounters most of the power losses. It is also quite clear that diode switching loss is very low. which can be ignored for high power converters. For switching loss calculation, the periodic average impulse response has been considered as the pulse width is quite small as compared to conduction loss. For calculating conduction loss, the periodic average conduction  loss has been taken into consideration for each individual switch. Fig. 25 (a) is the conduction loss curves for IGBT and Fig. 25 (b) is the conduction loss curve for body diode of the IGBT. The curve is being generated by the datasheet provided by the manufacturer. The datasheet had been imported in PLECS simulation environment and then corresponding lookup table was generated. Hence, turn-on and turn-off losses for both IGBTs and diodes were also considered during loss calculation. Thermal impedance provided by the manufacturer datasheet was also taken into consideration so that the loss calculation could be more precise and more realistic considering hardware implementation.
For industrial concern, a deeper thermal analysis of individual switch temperature is also taken into consideration to ensure the longevity of the proposed transformerless inverter. Fig. 26 shows the heat distribution of individual power switches considering four fundamental periods. In thermal modeling scenario, steady state mode has also been considered of the proposed transformerless inverter. It is notable that, switch S 2 and S 3 remain in low temperature while other switches create some sort of symmetrical pattern in terms of their body temperature. It should also be taken into consideration that while conducting the thermal analysis, the inverter was running at its rated output power.
The overall thermal profile seems quite stable. The whole inverter temperature, including all power switches, was found around 45 • C which can be easily mitigated via utilizing a proper designed heat sink.  Fig. 27 is quite self-explanatory due to its simple graphical representation by covering total switching loss, total conduction loss, total diode loss, total IGBT loss, and total power loss, respectively. The total loss is found around 6.42W at rated output power. The total switching loss including body diode and IGBT is found 0.14W, 0.13W, 0.1W, 0.1W, 0.35W, 0.04W and 0.28W for switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and S 7 , respectively. The conduction loss of each IGBT including their corresponding body diodes is also found 0.15W, 0.09W, 0.04W, 0.08W, 2.2W, 2.2W and 0.4W for power switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and S 7 , respectively. It can be observed clearly that, switch S 5 and S 6 encounter maximum power losses. Switch S 3 shows the lowest total power loss distribution because it is used for only to create the charging path for the capacitor. No high frequency operation is done by using switch S 3 . As a result, the total power loss is the lowest for S 3 power switch. Finally, it can be concluded that the proposed transformerless inverter not only shows good power loss distribution but also offers feasible heat distribution, which may increase the lifetime of the power switches. Table 4 summarizes a brief comparative study among the cutting-edge MLI topologies and the proposed transformerless inverter. The comparative study has been conducted considering the number of semiconductor devices count, the number of capacitors used as SC, the number of output voltage level, output voltage boosting capability, leakage current suppression capability and peak output power efficiency. Bidirectional switches are considered as two individual switches in the device count section based on different literatures. From Table 4, it is clear that, different type of inverter topologies has been proposed to reduce semiconductor switches, leakage current, increase voltage boosting ability, increased efficiency and so on. Though some of the converters of [8], [20], [21], [24], and [45] introduced reduced switch topologies, there used extra diode to compensate the need of extra of switches. Again, some converters of [20], [28], [32], [33], and [35] proposed to have a lower number of switches and diodes, there need quite a few SCs to produce only a five-level voltage output. Moreover, some converters of [29], [30], [42], [43], and [44] gained balanced efficiencies but these are not capable of boosting output voltage instead of using SC. Some recent studies [31], [32], [33], [34], [35] have introduced inverter topologies of higher efficiency, but there required more switches and diodes than that of the proposed transformerless inverter. Again, most of the existing topologies of MLIs also need more than two SCs to produce five-level output voltage. Other types of converters of [30], [40], and [44] show some balanced results in terms of device count as well as efficiency. But they don't feature CG architecture. As a result, most of the existing transformerless inverters suffer from high leakage current issues, though they try to minimize the leakage current, which cannot be eliminated completely through their proposed design. From Table 4, the proposed SC based transformerless inverter consisting of seven IGBT switches outperform than those of the current state of the art topologies of transformerless inverter.   [34] shows a balanced overall efficiency. However, the efficiency goes down as the output power increases. The rated efficiency of [27] and [29] topologies are found to be 96.8% and 96.1%, respectively. But these rated efficiencies are found considering lower output power at 500W and 300W, respectively. The overall efficiency of [26] is quite balanced but it doesn't feature voltage boosting capabilities instead of having an SC based architecture. The topology of [9] achieves excellent efficiency, but it suffers from an increasing number of semiconductor switches (12 MOSFETs) for a five-level output voltage, and it also requires three SCs, two of which are connected in series, causing voltage balancing issues. The rated efficiency is found to be 98.3% at 1200W output power for the proposed transformerless inverter. Thus, the proposed SC based transformerless inverter can be considered as the best candidate for offering promising power conversion efficiency along with auto voltage boosting capability compared to other existing transformerless inverters.

VI. CONCLUSION
In this paper, a single-phase five-level SC based transformerless inverter is proposed for grid-tied PV systems. The proposed transformerless inverter has voltage boosting capability by utilizing only a single SC ensuring five-level output voltage. The common mode voltage of the proposed transformerless inverter is found quite stable and thus the leakage current is found around 15.33mA in simulation and 17.1mA in hardware validation. The overall power loss and heat distribution among all the power switches are also found satisfactory for the proposed transformerless inverter. The total power loss is found around 6.42W at rated power and the efficiency is found around 98.3% which is higher than those of the many existing transformerless inverter topologies. The injected grid current THD for the proposed transformerless inverter is found 1.03% for a SC of 3300µF which ensures improved power quality of the inverter while feeding PV power to the grid. However, due to the modularity of the proposed transformerless inverter, a generalized version of the inverter could be introduced with lower number of SCs for MLIs. Besides, more advanced complex control schemes and modulation techniques could be introduced for better optimization and precision as future research direction. Thus, the proposed transformerless inverter can be considered as the best choice to the industrial community for manufacturing high performance transformerless PV inverter where efficiency, leakage current issue, power losses and switch count are critical concerns. VOLUME  His current research interests include power electronics, power quality, electrical machines and drives, grid integration of renewable energy sources, and smart micro-grids. He received the Best Paper Award at ICECE 2022. He has been working as an Assistant Professor with the Department of ETE, RUET, since December 2021. He has authored and coauthored more than 50 technical papers and two book chapters. His research interests include power electronics, electrical machines and drives, power quality, renewable energy systems, artificial intelligence, machine learning, real-time hardware-in-the-loop (HIL) simulations, and smart micro-grids. He  S. M. MUYEEN (Senior Member, IEEE) received the B.Sc.Eng. degree in electrical and electronic engineering from the Rajshahi University of Engineering and Technology (RUET, formerly known as the Rajshahi Institute of Technology), Bangladesh, in 2000, and the M.Eng. and Ph.D. degrees in electrical and electronic engineering from the Kitami Institute of Technology, Japan, in 2005 and 2008, respectively. He is currently working as a Full Professor with the Electrical Engineering Department, Qatar University. He has been a keynote speaker and an invited speaker at many international conferences, workshops, and universities. He has published more than 250 papers in different journals and international conferences. He has published seven books as the author or an editor. His research interests include power system stability and control, electrical machine, FACTS, energy storage systems (ESSs), renewable energy, and HVDC systems. He is a fellow of Engineers Australia. He is serving as an Editor/Associate Editor for many prestigious journals from IEEE, IET, and other publishers, including IEEE TRANSACTIONS ON ENERGY CONVERSION, IEEE POWER ENGINEERING LETTERS, IET Renewable Power Generation, and IET Generation, Transmission and Distribution. VOLUME 11, 2023