Subthreshold Modeling of a Tunable CMOS Schmitt Trigger

In this article, the subthreshold characteristics of a tunable single input CMOS Schmitt trigger (ST) are modeled for the first time. The high-to-low and low-to-high hysteresis transition points are analytically determined as a function of the tuning voltages and the transistors’ geometrical parameters. The derived expressions allow to design the ST with desired hysteresis width in subthreshold region. Furthermore, the proposed model allows to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions also provide physical insight into the circuit behavior, by predicting the effect of supply voltage and temperature variations on the hysteresis width. The model is validated through simulations, and the maximum error between the analytical and simulated transition points is less than 5%. The model is also experimentally validated with an ASIC fabricated in AMS $0.35~\mu \text{m}$ CMOS process. The maximum error between the analytical and measured transition points is below 6%. The analytical model allows performance optimization in subthreshold region for low power applications.


I. INTRODUCTION
The first Schmitt trigger (ST) was invented by Otto H. Schmitt in 1938, and it was intended to model the nerve membrane behavior [1], [2]. Although the primary application was in the biomedical field, Schmitt predicted that its circuit could be employed in various applications, such as thermostating, oscillography, and light control. Indeed, today STs are extensively implemented in both analog and digital systems [3]. For instance, they are used in triangular/squarewave generators [4], [5], [6], resistance-to-frequency converters [7], [8], capacitive-to-frequency converters [9], modulators [10], [11], SRAMs and latches [12], [13], [14], and different sensing and measuring applications [15], [16], [17], [18], [19], [20], [21], [22]. STs can work in current or voltage mode and be inverting or non-inverting. They can have single or differential input and have tunable hysteresis [23]. Currently, researchers are focusing on analyzing and modeling the subthreshold operation of STs [24], [25], [26], The associate editor coordinating the review of this manuscript and approving it for publication was Paolo Crippa . [27], [28], [29]. This is mainly due to the supply voltage reduction trend, which represents a key design technique in the power consumption optimization of electronic systems [30]. Operation at low voltages results in energy efficiency in battery-powered circuits, where the power consumption limits the system lifetime. In systems powered by energy harvesters, the level of the required supply voltage often determines the startup mechanisms. Lowering power consumption is also particularly advantageous in IoT enabling technologies, such as wireless sensor networks, where thousands of electronic devices are typically employed [31]. Supply voltage scaling is therefore critically important, considering that the number of connected devices is expected to increase to more than 30 billion in 2027 [32]. On the other side, subthreshold operation implies that MOSFETs are biased in weak inversion, which results in more complex analytical models [33]. In 2007, Kulkarni et al. implemented a modified version of the classical 6-transistor CMOS Schmitt trigger in 0.13µm CMOS process to implement an SRAM cell for subthreshold operation [34]. In 2012, Lotze and Manoli analyzed supply voltage reduction by considering ST logic, and analyzed the operation of digital circuits with a supply voltage of 62mV [35]. In 2017, the same authors proposed an in-depth analysis of ST gates in subthreshold, by considering the optimum transistors sizing [31]. In the same year, Melek et al. determined the DC transfer characteristic of the classical 6-transistor Schmitt trigger (0.18µm CMOS process) in subthreshold [24]. They analytically determined the hysteresis width and the minimum supply voltage (2ln(2 + √ 5)k B T /q = 75mV at room temperature) for which hysteresis occurs. One year later, Melek et al. analyzed the same ST in amplifier mode [26]. They theoretically found a minimum supply voltage of 31.5mV (at 300K ) for voltage amplification. In 2018, Bastan et al. proposed a subthreshold pseudo-differential ST in 0.18µm CMOS process, which consumes 150nW when operating at 0.4V [36]. In 2020, Radfar et al. presented a differential ST circuit (0.18µm CMOS process) with tunable hysteresis based on body biasing [28]. The circuit has a tuning range of approximately 110mV , and it consumes 1.38µW with a supply voltage of 0.6V . One year later, a less power consuming (120nW , with supply voltage of 0.4V ) differential ST circuit (0.18µm CMOS process) has been proposed by Nejati et al. [29]. In 2021, Fernandes et al. analyzed the subthreshold operation of a 3-inverter CMOS Schmitt trigger [25]. They analyzed the transition from amplifier mode to hysteresis mode, and they implemented a relaxation oscillator in 0.18µm CMOS process supplied by only 62mV . In 2022, Sandiri et al. analyzed ST logic gates using Dynamic Threshold MOS (DTMOS) technique [37]. In the same year, we derived in [27], [38] an analytical model for the hysteresis voltage of the low power CMOS ST proposed by Al-Sarawi [39]. In this article, the subthreshold characteristics of the tunable single input CMOS Schmitt trigger proposed by Wang [40] in 1991 are modeled for the first time. The circuit under analysis is shown in Fig. 1(a) and is the first single input tunable CMOS ST modeled in subthreshold. In this article, the expressions for the low-to-high (V LH ) and high-to-low (V HL ) transition voltages, shown in Fig. 1(b), are analytically determined. These two voltages define the hysteresis width (V H = V LH −V HL ). The proposed analytical model allows the design of the ST with desired hysteresis as a function of the transistors' geometrical parameters and tuning voltages. Furthermore, it provides physical insight into circuit behavior by relating the supply voltage and the temperature to the transition voltages. Moreover, the analytical model can be used to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions have been validated through simulations and measurements by prototyping an ASIC in AMS 0.35µm CMOS process. The analytical model is derived in Section II. In Section III the model is validated at simulation level, and the expressions are verified against tuning voltages. The model accuracy is also verified by considering supply voltage, temperature and process variations. The circuit power consumption has been also analyzed. The experimental results are reported in Section IV, while the conclusions are in Section V. Overall, the aim of this paper is to provide a deeper understanding of the subthreshold behavior of the analyzed Schmitt trigger, which is a common block in different analog and digital electronic systems.

II. ANALYTICAL MODEL
The subthreshold drain current expression (EKV [41]) is where: • B, G, S and D refer to the bulk, gate, source and drain, respectively; • n n(p) is the NMOS (PMOS) slope factor; • φ is the thermal voltage (kT /q); • µ n(p) is the electron (hole) mobility; • C ox is the oxide capacitance; • W /L is the transistor width to length ratio; When V SB(BS) = 0V , then (3) is further simplified to In the circuit under analysis, the bulks of all PMOS are connected to V dd , while those of the NMOS are grounded.
To simplify further analysis, the hysteresis transition points are assumed to be independent of each other, i.e. the high-tolow transition point (V HL ) depends only on the NMOS tuning transistor (M 8 ), while the low-to-high (V LH ) one only on the PMOS one (M 5 ). This assumption has been verified analytically, and through simulations and measurements. V HL is analyzed first. At initial state when the input (V in ) is high, the output (V out ) is high as well, due to two cascaded inverters as shown in Fig. 2(a). As a consequence M 4 is off, while M 2,3,7 are conducting. M 8 conduction depends on the tuning voltage V n . The input voltage at which the output switches from high-to-low (V HL ) can be determined by finding the switching voltage of the inverter composed of M 1,2 , plus the contribution of M 7 . Assuming transistors in saturation region during the transition [23], the current through M 1,2,7 is found using Kirchhoff's current law as (5), the slope factors are approximated as n n ≈ n p ≈ n [43], and I 0,p1 is redefined as (5) is then divided by I ′ 0,p1 and rewritten as To solve (6), it is necessary to determine the drain-source voltage across M 8 , i.e. V int,n . The latter can be obtained by equating the currents in M 7,8 and solving for V int,n : As can be observed in (8), V int,n is linearly dependent on the thermal voltage, and so directly proportional to the temperature. Instead the dependence on the dimensions of M 7,8 and the tuning voltage V n is logarithmic. By substituting (8) in (6) the following equation is obtained: Next the following temporary variables are defined: Equation (9) can be then rewritten as in (13) and solved for the variable x: Finally by replacing all the temporary variables in (14), the analytical expression (15), as shown at the bottom of the next page, for V HL is obtained. Regarding the low-to-high transition voltage (V LH ), its expression is shown below that of V HL in (16), as shown at the bottom of the next page, and its derivation is complementary. Referring to Fig. 2(b), first V int,p is determined by equating the current in M 5,6 : Next the currents in M 1,2,6 are equated: Then, (18) is substituted in (19), and the resulting expression is divided by I ′ 0,p1 . Next the temporary variables are defined, and the expression in (16) is finally obtained. Both derived expressions, (15) and (16), are linearly dependent on the slope factor and the thermal voltage, and logarithmically dependent on the tuning voltages and the transistors' dimensions. The high-to-low transition point depends on M 1,2,7,8 and V n , while the low-to-high one on M 1,2,5,6 and V p . Therefore, the analytical model is based on the assumption that the hysteresis transition voltages can be independently adjusted.

III. SIMULATION RESULTS
The proposed analytical model has been validated through simulations in AMS 0.35µm CMOS process. All the simulation results refer to post-layout simulations. The simulated NMOS threshold voltage is V th,n = 515.8mV , while the PMOS one is −731.3mV . The supply voltage has been initially fixed to V dd = 0.45V to guarantee subthreshold operation. As can be observed in (15) and (16), the M 1 aspect ratio (included in I 0,p1 as defined in (2)) is at the denominator of the terms inside the logarithms; this implies that a wider PMOS transistor will lead to a higher V LH and V HL . Therefore, the PMOS have been sized 20/1, while the NMOS 1/1, to obtain a larger hysteresis during the measuring phase. When computing I 0,n(p) , the extracted slope factors n n(p) = 1.25(1.3) are used. Instead, when computing the other terms in (15) and (16), the average value (n ≈ 1.28) is considered [43]. This last approximation is required in order to solve (5). The NMOS extracted transconductance parameter (β n(p) = µ n(p) ·C ox ·W /L) is 162.26µA/V 2 , while the PMOS one is 1.01mA/V 2 . The simulated V LH ,HL are extracted by sweeping the input voltage from 0V to V dd , and vice versa. In Fig. 3(a), the analytical and simulated V HL as a function of V n are shown. As can be observed, the analytical model resembles the simulated behavior. The same holds for V LH , which is shown in Fig. 3(b). The transition voltages are evaluated for V n(p) < 0.3V , because for higher tuning voltages V out does not toggle (i.e. no high-to-low transition), while V LH is almost constant, for the given design. It has been verified through simulations that the hysteresis transition voltages are strongly independent of each other, i.e. V HL(LH ) does not vary with V p(n) , as assumed by the proposed analytical model. To evaluate the error between the two curves, the maximum absolute and relative errors between the analytical (V HL(LH ) ) and simulated (V HL(LH ),sim ) transition points are defined: HL is 2.2mV while LH is 2.4mV . Instead, δ HL is 1.3% while δ LH is 0.8%. Relatively to the supply voltage ( HL(LH ) /V dd ), the maximum errors are below 0.5%. The error between the curves is mainly attributed to the considered approximation n n ≈ n p ≈ n. The analytical model has also been verified by considering different designs, shorter channel lengths (e.g. L = 0.35µm) and narrower transistors, and the maximum error resulted to be in the same order of magnitude of that of the reported design. The derived expressions have been validated by also considering data provided by the datasheet of the AMS 0.35µm CMOS process. Results similar to those obtained with the extracted ones have been obtained, i.e. errors in the same order of magnitude. Although the proposed analytical model has been validated with a relatively old CMOS process technology, the same EKV model has been used to correctly model STs in 0.18µm technology [25], as well as analyze circuits in lower technological nodes (e.g. 90nm and 65nm) [44], [45].

A. SUPPLY VOLTAGE, TEMPERATURE AND PROCESS VARIATIONS
To verify the accuracy of the model, different simulations have been performed by considering supply voltage, temperature and process variations. In Figs. 3(a) and (b), the maximum error occurs when V n(p) = 0V . Therefore, in the following the tuning voltages have been fixed to zero volts. In Fig. 4(a), the ST transfer characteristics are depicted for different supply voltages. The error associated to V HL is maximum for V dd = 0.4V , while that associated to V LH for V dd = 0.5V . Nevertheless, the maximum error relative to V dd is below 3% in the analyzed V dd range. The simulations have been performed with steps of 50mV in V dd , but only the extrema are reported, where the error is maximum. For supply voltages below 0.4V , the circuit does not toggle correctly for certain tuning voltages. In Fig. 4(b), the ST transfer characteristics are depicted for different temperatures (V dd = 0.45V ). The circuit is sensitive to temperature variations, and for both transition points the maximum error occurs at T = 373K . Nevertheless, the relative errors are 4.8% and 3.7% for V HL and V LH , respectively. Finally, Monte Carlo simulations have been performed in order to observe the deviation of the analytical transition voltages from the simulated ones, when considering both process and mismatch variations. The number of iterations was set to N = 2000. The histogram associated to V HL is shown in Fig. 4(c). The nominal V HL is 0.162V . The mean and standard deviation are 0.155V and 0.049V , respectively. Regarding V LH , its nominal value is 0.294V , while the mean and standard deviation are 0.278V and 0.097V , respectively. The analytical V HL and V LH are within one standard deviation.

B. MINIMUM SUPPLY VOLTAGE AND HYSTERESIS
The proposed analytical model can be used to estimate the minimum supply voltage for which hysteresis occurs. As can be observed in Fig. 4(a), when the supply voltage is decreased, both transition voltages decrease as well. Eventually, when the supply voltage is decreased to a certain value, the high-to-low transition will not occur. However, the lowto-high transition will still occur. In Fig. 5, the analytical high-to-low (V HL ) and low-to-high (V LH ) transition voltages are plotted as a function of the tuning voltages, for different supply voltages. When V DD = 0.5V , a hysteretic behavior is guaranteed only for V n < 0.37V , because for higher tuning voltage the analytical V HL becomes negative, i.e. it is not defined. This means that when sweeping the input voltage from high to low, no transition in the output voltage is observed. When the supply voltage is 0.3V , the high-tolow voltage is above zero volts until V n ≈ 0.17V . When V dd = 0.1V , both analytical curves are below zero volts, i.e. no transition is observed for whatever combination of V n and V p . It should be remarked that the minimum supply voltage for which hysteresis occurs also depends on transistors' dimensions. For the given design, the minimum supply voltage for which hysteresis occurs is approximately 0.15V , i.e. when V dd = 0.15V , V LH is defined but V HL is below zero volts for whatever V n . All the presented analysis has been verified through simulations.

IV. EXPERIMENTAL RESULTS
An ASIC in AMS 0.35µm CMOS process has been fabricated through EUROPRACTICE MPW to experimentally validate VOLUME 11, 2023  Fig. 6. Due to technology rules, the PMOS transistors are fabricated with two gates, each with a 10u width stripe. The voltages have been measured through a KEYSIGHT InfiniiVision DSOX3024T, by applying a 1Hz triangular wave at the input of the circuit. The analytical and measured V HL as a function of V n are shown in Fig. 7(a). The model resembles the measured behavior, although for increasing V n , the measured V HL is less linear. The same holds for the low-to-high transition point, shown in Fig. 7(b). For small V p the measured V LH is less linear than the analytical one. The maximum absolute error ( HL,meas = |V HL,meas − V HL |) between the analytical and measured V HL is 5mV , while the relative one (δ HL,meas = | HL,meas /V HL |) is 3.1%. Regarding the low-to-high transition point, the maximum absolute error is 16mV , while the relative one is 5%. The difference between the analytical and measured transition points is attributed to circuit parasitics and process variations (e.g. change in the slope factor). As can be observed in Figs. 7(a) and (b), both V HL and V LH are maximum for V n(p) = 0V and minimum for V n(p) = 300mV . The maximum hysteresis width (V H ,max ) occurs when V n = 0.3V , and V p = 0V , as can be observed in Fig. 8. V H ,max,meas is 253mV , while the analytical one is 276mV , i.e. the maximum error between the measured and analytical hysteresis voltages is 23mV . It has been verified through measurements that the hysteresis transition voltages are strongly independent of each other, i.e. V HL(LH ) does not vary with V p(n) , in agreement with the analytical model assumptions. The maximum operating frequency is 20Hz for the implemented design. Therefore, the circuit is suitable for low frequency applications, e.g. low frequency waveform generators. The circuit power consumption is mainly due to the switching currents during the transitions. Due to the very small amplitude of these currents,  they could not be measured precisely. Therefore, the circuit power consumption has been analyzed through simulations only. When switching from low-to-high, the maximum power consumption occurs when V p = 0V (i.e. M 5 is on), and the switching current has a peak value of 416pA. Instead, when switching from high-to-low, the maximum power consumption occurs when V n = 0.3V (i.e. M 3 is on), and the switching current has a peak value of 423pA. When the same circuit is simulated with the nominal supply voltage for the considered CMOS process (3.3V ), the maximum peak current has a value of 259µA and 287µA, during the lowto-high and high-to-low transitions, respectively. Therefore, when the circuit is operated in subthreshold region, the power consumption improves by five orders of magnitude with respect to the case in which the transistors are biased in strong inversion.

V. CONCLUSION
In this article, the subthreshold characteristics of a tunable CMOS Schmitt trigger have been modeled for the first time.
The analytical model relates the hysteresis transition voltages to the transistors' geometrical parameters and tuning voltages, allowing the design of the circuit with desired hysteresis width in subthreshold region. Furthermore, it allows optimization of the circuit operation by including the supply voltage and the temperature dependencies in its formulation. The proposed analytical model is based on the assumption that the high-to-low and low-to-high hysteresis transition points are strongly independent of each other. This assumption has been verified both at simulation and experimental level. Supply voltage, temperature and process variations have been considered. Moreover, a simple method for the estimation of the minimum supply voltage for which hysteresis occurs is reported. The maximum error between the analytical and simulated transition points resulted to be less than 5%. The model has also been experimentally validated with an ASIC in AMS 0.35µm CMOS process fabricated through EUROPRACTICE MPW. The maximum error between the analytical and measured transition points is below 6%. The power consumption has an improvement of five orders of magnitude, while the maximum operating frequency is limited to 20Hz, for the given design. Overall, the proposed analytical model provides a deeper understanding of the circuit subthreshold operation for low power and low frequency applications.