Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction

AlGaN/GaN Fin-shaped field-effect transistors (FinFETs) with nano-sized Fin width (<inline-formula> <tex-math notation="LaTeX">$\text{W}_{\mathrm {Fin}}$ </tex-math></inline-formula>) from 20 nm to 230 nm are characterized using low-frequency noise (LFN) measurement. All devices exhibit 1/<inline-formula> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> noise shape with Hooge mobility fluctuations (HMF) at subthreshold region and carrier number fluctuations (CNF) at accumulation region. However, the lowest normalized drain current noise spectral densities (<inline-formula> <tex-math notation="LaTeX">$S_{Id}/I_{d}^{2}$ </tex-math></inline-formula>) are obtained in the narrow Fin device (<inline-formula> <tex-math notation="LaTeX">$\text{W}_{\mathrm {Fin}}$ </tex-math></inline-formula> = 20 nm). This is due to significant contribution of bulk channel without the 2-dimensional electron gas density (2DEG) channel and two sidewall metal-oxide-semiconductor (MOS) channels. It is also noticed that the lowest trap density (<inline-formula> <tex-math notation="LaTeX">$N_{t}$ </tex-math></inline-formula>) and a large separation in CNF noise model clearly indicate to the volume accumulation effect caused by bulk conduction in narrow device. The Hooge constants (<inline-formula> <tex-math notation="LaTeX">$\alpha _{\mathrm {H}}$ </tex-math></inline-formula>) extracted by HMF noise model for the narrow device are one-order higher than those of the wide Fin device, which tells that the narrow device suffers from the strong phonon scattering in the bulk channel. From the product of (<inline-formula> <tex-math notation="LaTeX">$S_{Id} \times $ </tex-math></inline-formula> frequency (<inline-formula> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula>)) versus <inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm {d}}$ </tex-math></inline-formula> curves, the volume accumulation phenomenon is also clearly observed in narrow Fin device.


I. INTRODUCTION
AlGaN/GaN heterojunction makes the enhanced carrier confinements at the interface between AlGaN and GaN layer, which improves the device performances for high-frequency electronics and light-emitting diodes (LED) applications [1], [2], [3], [4]. The conventional planar AlGaN/GaN-based heterojunction field-effect transistors (HFETs) have a large 2-dimensional electron gas density (2DEG) of 10 13 cm −2 with high electron mobility of 2000 cm 2 /V·s. It enables them to exhibit the normally-on operation with negative threshold voltage (V th ) for high current device application [1]. On the other hand, GaN metal-oxide-semiconductor FETs (MOSFETs) presents the relatively low mobility of The associate editor coordinating the review of this manuscript and approving it for publication was Z. G. Zang . 300 cm 2 /V·s, but the normally-off operation, which is very suitable for power switching application [5], [6].
On the other hand, GaN-based nanowire FETs have several applications, such as low-power electronics and flexible devices due to their superior material properties, such as high piezoelectrical properties, large effective mass, and low permittivity compared to the Si, GaAs, and all oxide semiconductors [7], [8], [9]. Recently, several groups reported about the non-planar AlGaN/GaN-based Fin-shaped FETs (FinFETs), which consists of two channels; one is top 2DEG channel formed at AlGaN/GaN heterojunction and the other is two MOS channels on oxide/GaN sidewalls [10], [11], [12]. The fabricated AlGaN/GaN FinFETs showed superior device performances, such as the excellent off-state performances and broaden transconductance (g m ) with the reduced current collapse, due to the coupling effect of two channels and the improved gate controllability. In addition, Fin width (W Fin ) dependent physical models for AlGaN/GaN FinFETs were proposed in order to verify the experimental data from the literatures [10], [11], [12] and derive the equation of V th and drain current (I d ) for 2DEG and MOS channels [13], [14].
Our group has already reported on the low-frequency noise (LFN) analysis in AlGaN/GaN nanowire FinFETs in order to find the dominance of the channel conduction mechanisms (2DEG versus MOS conduction) and also calculate the trap density (N t ) [15], [16]. These fabricated Fin devices showed the carrier number fluctuations (CNF) regardless of W Fin and N t of 2.4 × 10 21 /4.3 × 10 21 cm −3 ·eV −1 for the narrow/wide Fin device [15]. This reduced N t in narrow Fin device proved to be the significant volume accumulation effect, which is similar with the volume inversion phenomenon in Si FinFETs [17].
However, there are no detailed noise examinations about the bulk channel in AlGaN/GaN FinFETs. Moreover, the volume accumulation behavior in the bulk channel are not conducted and thus are needed to discuss. In this paper, we investigate the detailed W Fin dependent I d -V g and noise characterizations in order to observe the dominant contribution for various channels according to the W Fin and prove the existence of bulk channel in the proposed device. These detailed noise analyses provide the accurate noise models and device reliability to the analog circuit designers and device engineers for future low-power logic applications.

II. EPITAXY GROWTH AND DEVICE FABRICATION
The detailed epitaxy growth and device fabrication were depicted in our previous reports [11], [12]. However, the brief explanations are following. The Al 0.3 Ga 0.7 N/GaN (30 nm/80 nm) heterojunction with 1-nm thick AlN interlayer was grown on 3 µm-thick GaN/sapphire substrate using metal organic chemical vapor deposition ( Fig. 1(a)).
For device fabrication, Fin arrays were patterned on the AlGaN/GaN epitaxial layer using a polymethyl methacrylate (PMMA) by electron-beam lithography and then mesa isolation was formed by dry etching using Cl 2 gas. After then, surface treatment with tetramethyl-ammonium hydroxide chemical solution was following in order to smooth the etched sidewall surface of Fin arrays [6]. A 20 nm-thick Al 2 O 3 gate oxide was then deposited using atomic layer deposition (ALD) machine. After the source/drain area opening, the ohmic metal (Ti/Al/Ni/Au) was deposited and directly annealed by rapid thermal process. Finally, the gate metal was deposited.
W Fin are varied with from 20 nm to 230 nm and Fin height (H Fin ) is 200 nm with the number of Fin (N Fin ) of 36. The gate length (L g )/gate-to-drain distance (L gd ) are 2/5 µm. The fabricated devices consist of top 2DEG channel at AlGaN/GaN heterostructure ( Fig. 1(b) and Fig. 1(c)), two sidewall MOS channels at Al 2 O 3 /GaN interface, and bulk channel in the center of GaN Fin, as previously described ( Fig. 1(b) and Fig. 1(d)). The schematic cross-sectional device structure and transmission electron microscopy (TEM) image were shown in Fig. 1(a) and Fig. 1(e).  When W Fin is relatively wide, the 2DEG channel in the device is significant, which results that the device presents the normally-on operation with negative V th . As decreasing W Fin , the V th shifts to positive and also I d decreases due to the depleted 2DEG channel caused by the fringing electric field of the wrapped gate metal in AlGaN/GaN FinFETs [10], [12].

III. CHARACTERIZATION RESULTS AND DISCUSSION
In addition, two sidewall MOS channels with positive V th become the dominant channels of device and thus contribute to the positive V th shift of the proposed devices (as shown in the energy band diagram of two sidewall MOS channels of Fig. 1(d)). From computer-based simulation in the literature [13], the calculated V th of the sidewall MOS channel is expected to be approximately 0.3 V caused by the sidewall depletion regions. The bulk current through the neutral channel in the center of the GaN Fin (bulk channel) can be further shifted the V th to the positive direction depending on the W Fin . Although the existence of three parallel conduction paths, there are no showing a change in slope in I d -V g curves because of the limited positive gate voltage sweeping up to 1 V caused by the quality issue of gate dielectric layer and/or the high electric field at the corner of Fin structure.
On the other hand, all Fin devices exhibit the excellent off-state leakage current and steep subthreshold slope of almost 60 mV/decade with near ideal value, thanks to the wrapped gate metal in 3D Fin structure, as shown in Fig. 2(b). The combination effects for the simultaneous turn-on of the 2DEG channel and accumulation channel at very smooth GaN sidewall surface lead to the superior subthreshold properties in the devices [18], [19]. To analyze the W Fin dependent characteristics in the proposed devices, the low-frequency noise (LFN) measurements are investigated using fully automatic noise system (Synergie-concept, NOISYS7) at room temperature [20]. The measured conditions are the frequency (f ) of 4 ∼ 10 4 Hz at V g = −3 ∼ 1 V (from deep-subthreshold to accumulation region). In order to minimize the noise fluctuations caused by the high electric field, the drain voltage is set to be 0.1 V (linear region), rather than the large voltage of over 5 V (saturation region). Fig. 3(a) exhibits the normalized drain-current noise spectral densities (S Id /I 2 d ) as a function of frequency at V d = 0.1 V and (V g -V th ) = 0.25 V, showing clearly 1/f dependence for varying Fin widths. This noise behavior can be explained by CNF noise model (McWhorter's model) [21], [22]. The CNF noise model is attributed to the fluctuations caused by the electron trapping/detrapping between the oxide/barrier layer and the channel and thus can be expressed as following equations [21], [22], where g m is transconductance and S Vfb is the flat-band voltage fluctuations including q is the electron charge, kT is the thermal energy, λ is the oxide tunneling attenuation distance (∼ 0.137 nm), N t is the volumetric oxide trap density, WL is the channel area, and C ox is the gate dielectric capacitance per unit area. On the other hand, the one of the possible explanations for 1/f noise is attributed to be due to the Hooge mobility fluctuations (HMF) using the following equation [23], [24], where α H is Hooge parameter. The significant contribution for the HMF noise mechanism is due to the mobility fluctuation in the channel induced by the carrier-phonon interactions and their scattering.
To investigate the main contribution of the noise models for the AlGaN/GaN FinFETs with various W Fin , the S Id /I 2 d are plotted in Fig. 3(b) according to the I d . The fabricated devices exhibit the decreasing S Id /I 2 d values at subthreshold region, which are clearly confirmed to the dominance of the HMF noise model. On the other hand, the S Id /I 2 d at strong accumulation region are exponentially decreased, which can be explained by CNF mechanism. It is also interesting that all devices have almost same S Id /I 2 d values at strong accumulation region, but the lowest S Id /I 2 d values for the device with W Fin = 20 nm are observed at subthreshold region. The reason for the lowest noise levels for the narrow Fin device at I d < 10 −5 A is because of the volume accumulation effect in the bulk channel [15], [17]. In the narrow Fin structure, the accumulated carriers in MOS channels are repelled from the interface toward the center of the body, causing the narrow Fin device to have reduced noise [15], [17]. In addition, when the Fin width becomes very narrow (W Fin <∼ 50 nm), the Fin device has no 2DEG channel due to the partially strain relaxation of AlGaN layer and the sidewall depletion effect induced by the fringing gate electric field, as described before [11]. In our device with narrow Fin structure, the most of currents flow through the volume of the Fin, not the surface region near Al 2 O 3 gate insulator because of the maximum gate voltage of 1 V. 3D numerical simulation of AlGaN/GaN FinFET in the range V g < 1 V was supported to this phenomenon in our previous papers [18], [25]. On the other hand, the relatively large Fin devices exhibit the enhanced noise levels due to the complex channel conductions.
In order to compare the trap density (N t ) between the narrow and wide Fin devices, S Id /I 2 d values are matched with (g m /I d ) 2 and then the S Vfb value can be obtained in Eq. (1) (Fig. 4(a) and 4(b)). These S Vfb values are divided into two drain current levels to better fit with the S Id /I 2 d values because two different noise models are involved according to the I d . The obtained S Vfb value for the relatively low drain current is 9 × 10 −9 V 2 /Hz, whereas for high current level in the narrow Fin device is 7 × 10 −10 V 2 /Hz. On the other hand, the corresponding S Vfb values for wide Fin device are 3 × 10 −9 V 2 /Hz and 7 × 10 −10 V 2 /Hz, respectively. When the effective C ox considers the deposited Al 2 O 3 oxide layer at Al 2 O 3 /GaN interface and the S Vfb values for the high current levels are applied in Eq. (2), the corresponding N t are calculated to be 3.6 × 10 19 cm −3 ·eV −1 for the narrow device and 5.2 × 10 19 cm −3 ·eV −1 for the wide device. The lowest N t value in the narrow device also proves to less charge trapping in the bulk channel due to the volume accumulation effect. It is also noticed that the S Id /I 2 d at low current levels for the narrow Fin device has a large separation from the values of (g m /I d ) 2 × S Vfb2 (red color) ( Fig. 4(a)). On the other hand, a small deviation between S Id /I 2 d and (g m /I d ) 2 × S Vfb2 is observed in subthreshold region, as displayed in Fig. 4(b). When W Fin is decreasing, the separation between S Id /I 2 d and (g m /I d ) 2 × S Vfb2 is oppositely increased. This tendency is consistent with noise results in Si-based FinFETs [17], which reflects that the mobility fluctuations in the narrow Fin device are more prevailed. The reason for the dominant HMF according to the decreased Fin width is because the carriers in the channel of the narrow Fin structure are more localized in the center of body. This is believed to be due to the volume accumulation in the narrow device, as mentioned before. Fig. 5 plots and compares the Hooge constant (α H ) for the narrow and wide devices according to the drain current. The α H for two devices can be calculated using Eq. (3) until the relatively low drain current of 10 −7 A because the HMF is pronounced at subthreshold region. The extracted α H values for the narrow Fin device are obtained to be 0.5 ∼ 20, which is approximately one-order higher than those of the wide Fin device. The reason for the large α H values of the narrow Fin device is believed that the device increases the phonon scattering in the bulk channel. On the other hand, the wide device mitigates the phonon scattering due to the superiority of the 2DEG channel with high quality. Furthermore, in order to analyze the volume accumulation in AlGaN/GaN FinFETs, the product of S Id × f according to the I d for narrow and wide Fin devices are plotted in Fig. 6.
S Id × f of both devices depends on the I 2 d . However, there is no observation of hump, but linearly decreasing of the S Id × f at high current for narrow Fin device. This noise behavior is contributed to be due to the bulk conduction caused by the volume accumulation of narrow Fin device. On the other hand, wide Fin device exhibits a decreased S Id × f and hump at large drain current, which indicates to the surface conduction due to the dominance of 2DEG channel [26], [27].

IV. CONCLUSION
AlGaN/GaN FinFETs according to the W Fin are characterized through noise measurements. S Id /I 2 d values for the smallest device (W Fin = 20 nm) are the lowest compared to those of the other devices, which reveals to the volume accumulation effect in bulk channel of the narrow Fin device. The calculated N t with the lowest value and a large separation in CNF noise model tell to the significant volume accumulation effect caused by bulk conduction. In addition, when compared to the product of S Id × f dependent on W Fin , it is clearly observed to the volume accumulation effect in the narrow Fin device. Using these noise results, the fabricated AlGaN/GaN FinFET with nano-sized W Fin is mainly governed by the bulk conduction in center of GaN Fin, rather than top 2DEG channel at AlGaN/GaN heterostructure and two sidewall MOS channels at Al 2 O 3 /GaN interface. From these observations, the Fin width in the AlGaN/GaN FinFETs should be optimized and designed for low-power logic device and analog circuit applications.