Investigation on Multisampling Deadbeat Current Control With Time-Delay Compensation in Grid-Connected Inverter

The control of voltage source converters (VSCs) is now implemented on digital microprocessors. This digitalization has the drawback of time delay in the control loop. The goal of this research work was to investigate improvements that can be obtained from the combination of model-based and model-free time-delay compensation approaches. Deadbeat control (DBC) from model-based techniques and the method of moving the control variable’s sampling instants, or the pulse-width modulation (PWM) updating instants, from model-free time-delay compensation techniques, were put together as the proposed new method of time-delay compensation in this study. These controllers were thoroughly examined in terms of control algorithm design, system stability analysis, and sensitivity analysis of plant parameter perturbations. In addition, thorough Simulink-based computer simulations were conducted in this work to assess the performance of each controller. The proposed method compensated about $80~\mu \text{s}$ as compared with the time delay compensated by the conventional single-sampling method. This research work was limited to simulations only; hence, conducting experiments to further validate this research work could be a direction for further research.


I. INTRODUCTION
Over the last sixty years, the field of power electronics has progressed. Static converters can now effectively transform electric energy to fulfill the needs of a wide range of applications and they are the technology that allows renewable energy to be integrated into electric grids. As a result, power electronics will be crucial in the renovation of existing electric grids. Grid codes are updated on a regular basis by system operators to ensure power quality and grid security. As a result, power converter manufacturers must build reliable The associate editor coordinating the review of this manuscript and approving it for publication was Inam Nutkani . devices with short-time-delay controllers in order to compete in the market.
There are a number of power quality problems at present, which can be classified into natural and man-made. Natural causes of poor power quality are mainly faults, lightning, storms, and equipment failure. Man-made causes are mainly related to loads or system operations. One of the most significant issues with power quality is the presence of harmonics, which can be caused by a variety of loads that operate in a nonlinear fashion. These loads can range from more traditional ones, such as transformers, electrical machines, and furnaces, to more modern ones, such as power converters, switched-mode power supplies (SMPS), AC voltage controllers, and so on [1]. It is commonly known that distributed generation, in spite of the advantages it offers, results in harmonic issues as a direct result of power converter interfaces. From the inverter side, passive filters, such as L, LC, LCL, and LCCL filters and so on, are used to limit the harmonic injection, while active filters (AF) are used for harmonic and reactive power compensation between the inverter and the grid or between the grid and nonlinear loads. A comprehensive discussion on recent AFs used was presented in [2]. In [3], the authors proposed harmonic mitigation using the phase shift. According to the authors, this technique has the ability for harmonic self-cancellation.
In recent research works reported in [4], [5], and [6], the major emphasis was on converter control techniques. This control strategy incorporates cascade control, which may either be the inner loop or outer loop control, or both, being applied in a single system. The inner loop control usually adopts current control because the inner current loop is much faster in controlling system dynamics than does outer voltage or power loop control. As a result, the current control loop, also known as the inner control loop, plays a very significant role in enhancing the overall performance of a control system. However, typical current controllers that are used in the inner control loop, such as the proportional-integralderivative (PID) controller in the synchronous frame, are often constrained by the amount of useful bandwidth that is available in the controller [7], [8].
The control of grid-connected inverters is now implemented digitally on a microprocessor as a result of the advances achieved so far in digital signal processing. Although, some problems have been reported in the literature regarding the digital implementation, which limits the performance of the system. Among them are the occurrence of time delay in the control loop, the existence of a ripple component at the sampling frequency, harmonics in the output, and restrictions on the useable bandwidth, which are limited to a fraction of the sampling frequency [11]. However, for various practical reasons, digital controllers have reported strong benefits that exceed the disadvantages described, to the point that digital controllers are more desired, particularly in grid-connected inverter applications. As a consequence of this, research on digital controllers, such as DBCs, is now receiving more attention than it did in the past, as stated in [10].
Before delving into the topic, it is very necessary to have a solid understanding of the factors that lead to the inclusion of time delay in the inverter's control loop. The delay is primarily caused by the zero-order hold effect associated with digital pulse-width modulation [12], the controller computing time [13], and the sampling and updating of the voltage and current values to be controlled [14]. Therefore, when there is a significant amount of time lag in the control loop, the controller is unable to function effectively. This might result in a controller with a decreased transient response, significant overshoot, and a narrow control bandwidth. This impact may cause the controller's performance to deteriorate, as well as instability.
Therefore, the consequences of time delay may be mitigated by using compensators in certain situations. A large number of time-delay compensation approaches have been suggested in the recent literature, most notably in [15], where the authors used dual sampling and updating as well as a proportional resonant controller to eliminate the computational delay in the control loop. A good result was achieved in this research work; however, this method can be enhanced further by adopting a higher number of sampling and updating. There is a detailed explanation of this topic in [9], where the authors reviewed and classified all the compensation techniques for time delay. Additionally, the authors hypothesized that combining two of the best compensation techniques, which are the technique of shifting the sampling and updating instants from the model-free approach and the DBC technique from the model-based compensation approach, can be a new improved method to give better results. These two techniques have been reported separately in the literature to have an outstanding performance, where the DBC with double sampling and updating was researched in [16].
Deadbeat current control has the advantages of achieving zero steady-state error, fast dynamic response, and time-delay mitigation [9], [10], but the downsides of this controller are its aggressiveness to control actions, sensitivity to model accuracy, and inherent one-period delay. These drawbacks reduce its potential of achieving fast current tracking and resilience to disturbances. In the literature, a state observer has been used to lessen the controller's sensitivity to model accuracy, while the technique of shifting sampling and updating instants has been used to mitigate the time delay associated with the controller. However, to the best of our knowledge, no studies have looked into the issue of the aggressiveness of this controller. Additionally, among the methods of shifting sampling and updating instants for time-delay mitigation, the single-sampling single-updating (SS-SU) and the doublesampling double-updating (DS-DU) methods are associated with a one-period time delay and a half-period time delay, respectively [16]. On the other hand, while the multisampling multi-updating method eliminates the residual time delay associated with SS-SU and DS-DU, it introduces some nonlinearities, requiring the use of an anti-aliasing filter in the feedback path. The filter added re-introduces a phase lag, which compromises the dynamic benefits obtained by the MS-MU method [17]. Hence, a method that uses a tuning polynomial to lessen the aggressiveness of the DBCC, models the controller with a time delay to reduce its sensitivity to model accuracy, and uses quadruple sampling and updating to reduce the inherent time delay was proposed in this study. The proposed method eliminates the need for the anti-aliasing filter used in MS-MU and provides an improvement in timedelay mitigation as compared with that of the DS-DU method.
Additionally, different than what had been researched, our work re-designed and investigated the best four approaches of VOLUME 11, 2023 the DBC design reported in [10]. These four approaches were intuitively re-designed with time-delay consideration, and an investigation of the number of sampling that can give optimal time-delay compensation was also intuitively conducted in this study, as recommended in [9]. In the end, our proposed combined design can successfully be implemented on microcontrollers, with a relatively similar performance as that of the design implemented on the FPGA in [17]. The remaining parts of this article are structured as described below: timedelay compensation techniques are discussed in Section II, DBC design approaches with time delay are explained in Section III, and the stability analysis of the current controllers is offered in Section IV of this paper. Simulation results can be found in Section V, and in the last part of this report, which is Section VI, the conclusion and some suggestions are offered. Acknowledgment is documented in Section VII.

II. TIME-DELAY COMPENSATION TECHNIQUES
Physical systems with the time delay characteristic are those whose responses to external stimuli are delayed regarding the impact on the systems' output. [18]. Several time-delay compensation strategies have been presented in the literature, categorized as model-based (MB) or model-free (MF) [6]. MB techniques are more precise but reliant on the correctness of the system model, while MF techniques are less precise but independent of the model's accuracy. Examples of MB time-delay compensation methods are the Smith predictor (SP), the modified Smith predictor (MSP), the deadbeat controller (DBC), and the model predictive controller (MPC), among others. Examples of MF methods, on the other hand, included the damping technique (DT), the filter-based technique (FBT), and the technique of shifting the sampling instants (SSI) of the control variable [6]. Short delays may be compensated for using a range of techniques, as detailed in [9]. In the present research work, basically we combined both the MB and MF compensation methods, which were the DBC technique and the technique of shifting the sampling and updating instants of the control variable. In the next subsection, the approach of shifting the sampling and updating instants (SSI) of the control variable is discussed.

A. SHIFTING SAMPLING INSTANTS OF CONTROL VARIABLE OR PWM UPDATING INSTANTS
It is common to sample state variables during PWM on/off times. Inductor, capacitor, and grid currents are measured in this manner, as shown in Fig. 1(a), where m s is the single-updated pulse-width modulation (PWM) wave. The single-updated PWM wave m s (k − 1) of the (k − 1) th carrier cycle is usually loaded at the peak of the (k − 1) th triangular carrier and the duty cycle is expressed as M (K) = m s (k − 1), where m s (k − 1) is the duty cycle, which is calculated by sampling the values at the peak of the (k − 1) th triangular carrier [16]. Fig. 1(a) shows single sampling and updating, with one sampling point and one updating point in the pulse period; Fig. 1(b) shows doubling sampling and updating, where there are two sampling and updating points in one pulse period. Similarly, more than five sampling and updating points are seen in multi-sampling and multiupdating, as shown in Fig. 1(c). Single sampling and updating will often result in a delay of one switching period, which will place a restriction on the bandwidth that is accessible to the current controller. By using the double-updating mode, as seen in Fig. 1(b), the one-switching-period delay may be further decreased until it is equivalent to only half of the switching period. In this mode, the parameters are sampled twice, and the update is performed at the peak and valley of the triangular carrier twice: in the middle of the turn-on time and in the middle of the turn-off time of the pulse width. Additionally, updates are carried out at the peak and valley of the triangular carrier. However, a number of scholars have proposed that, to further reduce time delay, the instant at which a control variable is sampled needs to be relocated closer to the instant at which the duty cycle changes. This method was used in [19], [20], and [21]. However, because of the asynchronous sampling process, utilizing this method may result in harmonic content that is not acceptable [22]. The authors in [9] used the method of sampling control variables around the duty cycle's updating instants, despite the fact that conventional sampling in the middle of the turnon and turn-off phases of the PWM would have minimized harmonic disturbances more effectively. Another method for reducing time delay is to sample the state control variables and perform several updates to the duty cycle within a single switching period, as shown in Fig. 1(c). This method is called the multi-sampling multi-updating approach [17]. This technique may be readily implemented on field-programmable gate arrays (FPGAs) [23].

1) DIGITAL AND PWM DELAYS
For a voltage-source converter (VSC) that is digitally controlled, there will be a computing delay in addition to the PWM delay. The delay in computing is caused by the passage of time between the moment the current is sampled and instant k + 1, when the digital controller's output voltage reference signal is actually adjusted. This passage of time is denoted by the symbol k in Fig. 2, and it is shown as a time difference from k to k+1. The digital sample's instants shown in Fig. 2 are updated at the moment the PWM triangular carrier signal is in the midst of its cycle. This method is known as synchronous pulse-width modulation sampling, and the digital computing delay, in this case, is equivalent to one sample period, shown as the gray band in Fig. 2. The zero-order hold (ZOH) effect is the primary factor that contributes to PWM delay. This effect ensures that the PWM reference value remains unchanged (solid-blue curve in Subplot (b) of Fig. 2) after it has been modified, and the expression can be described as follows [15], [24], [25]: The dashed-blue curve in Subplot (b) of Fig. 2 illustrates visually the averaged value of the PWM reference constant that is kept on after each update. By considering the ZOH impact of PWM, the gold accent band displays the approximated half-sample cycle delay. The following is a mathematical derivation of this approximation [19]: The total digital delay, Gd(s), after taking into account sampling, calculating, updating, and the ZOH impact of PWM, may be determined as: where T s represents the digital sampling time, while T sw represents the PWM sampling time. The condition of T sw = 0.5T s exists when synchronous PWM sampling is taken into account. PWM digital sampling is represented by 1 T s .

III. DBC DESIGN APPROACHES WITH TIME DELAY
For the purpose of comparison, this study used a gridconnected inverter equipped with an LCL filter and active damping, as presented in [26]. Fig. 3 depicts the control loop of the inverter using grid-side current control with feedback of capacitor current for the active-damping LCL filter, where P L represents the third-order filter and K pwm represents the gain of the full-bridge three-phase inverter [27], which can be approximated by Equation 4: Equation 5 may be used to express the control system's loop gain, which can be found in Fig. 4.
where, L ′ g = L g + L gs and T s is the sampling time. To evaluate the combined time-delay compensation techniques, we used the plant transfer function modelled with time delay, as prescribed in Equation 5. The assumption that the grid voltage is an ideal voltage source may be made for frequencies other than the fundamental, and the grid side can be considered as if it were a short circuit [28].  As a result, based on Table 1, the transfer function from Equation 5 can be represented as Equation 6, which becomes the plant to be controlled.
Discretization was carried out utilizing the ZOH approach, and the sampling frequency was set at 10 kHz. The discrete version of the transfer function in Equation 7, as shown at the bottom of the next page.
As can be seen from the zero-pole gain (zpk) in Equation 7, the system had one zero, which was located outside of the unit circle, as well as one pole, which was located on the unit cycle. As a result, a discrete controller must be designed to force the pole to lie within the unit circle. Because the deadbeat controller's design processes were given in d-operator z −1 , Equation 7 can be represented as Equation 8, as shown at the bottom of the page, by simply dividing the zpk by z. Then, using the formulas presented in [7], we developed the controllers.

A. POLE-ZERO-CANCELLATION NON-MINIMUM REALISATION (PZCNR) APPROACH
The tuning polynomial was calculated using the discretized zpk from Equation 8 as follows: As a result, the controller was developed, as shown in Equation 9: The required closed-loop pulse transfer function is provided by: and presented as in Equation 10: Subplots (a) and (b) in Fig. 4 show the step and Nyquist plots, respectively. The closed-loop system settled at two sample periods with no overshoot, and on the Nyquist plot, the critical point was not encircled, demonstrating that the closed-loop system was stable.

B. POLE-ZERO-CANCELLATION MINIMUM REALISATION (PZCMR) APPROACH
Using the discretized zpk from Equation 8, we were able to design the tuning polynomial, as shown in the equation below, by making use of the formula in [10]: As a result, the controller was successfully obtained, as shown by Equation 11: The desired closed-loop pulse transfer function may be represented by the following equations: and presented as in Equation 12: The step plot and Nyquist plot are shown, respectively, in Fig. 4's Subplots (c) and (d). The system stabilized at four sample periods with no overshoot, and the critical point on the Nyquist plot was not encircled, which evidenced that the closed-loop system was stable.

C. POLYNOMIAL (FACTORIZATION/RIPPLE-FREE) DEADBEAT CONTROL APPROACH
The tuning polynomial was calculated using the discretized value of zpk in Equation 8 as M (z) = 0.04955z −1 , C 1(z) = 1, and Q (z) = 1 + 0.9505z −1 + 0.3374z −2 + 0.00852z −3 . As a result, the controller was determined using the equations in [7], as shown in Equation 13. The proposed closed-loop pulse transfer function is expressed as in Equation 14: The step and Nyquist plots of this method are shown in Subplots (e) and (f), respectively, in Fig. 4. As can be seen from the plots, the system stabilized at four sample periods with no overshoot, and the Nyquist plot shows that the critical point was not encircled, indicating that the closed-loop system was stable.

D. POLE PLACEMENT TECHNIQUE (STATE-VARIABLE DERIVATION)
The pulse transfer function, which was found in Equation 8, was transformed into the state space in control canonical form as: Let K T denotes the constant required to place the poles at the origin and X C denotes the characteristic polynomial, as in Equation 15: Equation 16 can be used to obtain the overall transfer function by taking into consideration the signal as it travels from the input to the output [7]: Therefore, the closed-loop matrices were developed into their final form as:  Fig. 4's Subplots (g) and (h), respectively. The system settled at three sample periods with no overshoot, and on the Nyquist plot, the critical point did not seem to be encircled, which suggested that the closed-loop system was operating in a stable region.

E. HYBRID DEADBEAT CONTROLLER USING STATE-SPACE DESIGN
In order to create a deadbeat control that also integrated the control error, we built a new extended set of state and output matrices using the state matrices from the method discussed in Subsection D, but this time we included an extra variable referred to as ν. This construction process was explained in [7]. The new substituted matrices were labeled as follows: ; DB s(z) = 2.578z 5 − 2.004z 4 − 0.5606z 3 + 0.09092z 2 − 0.0974z − 0.004857 z 6 + 12.37z 5 + 6.636z 4 + 0.1719z 3 (17) 12450 VOLUME 11, 2023 this is a vector set of n + 1 by 1 where Q c is the controllability matrix. Therefore, Following the steps outlined earlier, we were able to acquire the deadbeat controller, as in Equation 20, are shown at the bottom of the page, and Equation 21 was used to obtain Equation 22, as shown at the bottom of the page, which describes the closed-loop reference transfer function.
The general feedback transfer function, which goes from the input to the output, can be found in Equation 23, and the step plot and the Nyquist plot can be found in DB hb = 2.579z 6 − 2.126z 5 − 0.4614z 4 + 0.113z 3 − 0.1029z 2 z 6 + 13.32z 5 + 19.38z 4 + 18.59z 3 + 9.969z 2 + 2.024z + 0.04817 (20)   Subplots (i) and (j) of Fig. 4, respectively. The system settled at three sample periods without any overshoot and there was no encirclement of the critical point on the Nyquist plot, both of which indicated that the closed-loop system was stable. Table 2 summarizes the control laws as well as the output difference equations for each of the controllers previously addressed. Following that, we discuss which technique is the most stable, especially in terms of grid-impedance variation.

IV. STABILITY ANALYSIS OF CURRENT CONTROLLERS
At this stage, the stability of the designed controllers was tested to help the authors to draw a conclusion on which method was the best. Fig. 5 shows the step and Nyquist plots for each of the five controllers at steady state, as well as at grid impedances of 40% and 80%. The step plots reveal that all of the controllers had either modest or no overshoot, despite the different impedances. In addition, none of the VOLUME 11, 2023  Nyquist plots indicated that the critical point was enclosed, which demonstrated that the closed-loop system continued to be stable. As demonstrated in Subplots (a), (b), and (c) of Fig. 6, all of the controllers' magnitudes were at −20 dB/dec, going through 0 dB at ω = 1, which indicated that the poles of the closed-loop were at the origin.

V. SIMULATION RESULTS
To learn more about these sorts of controllers, simulations were run for the five controllers, based on the schematic diagram as shown in Fig. 7.
In addition, the currents at the point of common coupling (PCC) before and after current injection are depicted in Fig. 8's Subplots (a), (b), and (c), which indicate that there was negligible distortion when the inverter was hooking to and dropping from the grid. Subplot (a) in Fig. 9 depicts the voltage at the PCC in islanded and grid-connected modes, while Subplots (b) and (c) illustrate the distortions that are caused by hooking to and falling from the grid, respectively. Current and voltage deviations were unequivocally well within the parameters of what is considered acceptable. Figs. 10(a) and (b) illustrate, respectively, the directquadrature-zero (dq0) currents of the current controller and  the electricity that was injected into the grid by the inverter. The graph demonstrates that the 80kW inverter contributed around 12 kW of power to the distribution network.  delay was mitigated by adopting double sampling and updating. Fig. 11(b) shows a comparison of the waveforms of single and double sampling and updating, where about 0.9 units of difference can be observed before and after the transition, and about 5.8 units can be observed during the grid-connected mode. From the close-up view, we observed that by using double sampling and updating, a 50µs time delay in switching from the off-grid mode to the grid-connected mode was also mitigated. Fig. 12(a) shows the superimposed current waveforms of single and quadruple sampling and updating, and it can be observed from the close-up view that about 80 µs of time delay was mitigated by quadruple sampling and updating, while Fig. 12(b) shows a comparison of the waveforms of single and quadruple sampling and updating, where about 1.4 units of difference can be observed before and after the transition, while about 6.3 units of difference can be seen during the grid-connected mode. From the closeup view, it can be observed also that about 80 µs of time delay in hooking to the grid was mitigated using the technique of quadruple sampling and updating, while there was no noticeable difference in its waveform when dropping from the grid. Fig. 13(a) shows the superimposed current waveforms of single and decuple sampling and updating, where it can be observed from the close-up view that about 90 µs of time delay was mitigated by decuple sampling and updating, while Fig. 13(b) shows a comparison of the waveforms of single and decuple sampling and updating, where about 1.6 units of difference can be observed before and after the transition, while about 6.5 units of difference can be seen during the grid-connected mode. From the close-up view, it can be observed also that about 90 µs of time delay in hooking to the grid was mitigated using the technique of decuple sampling and updating, while there was no noticeable difference in its waveform when dropping from the grid. Fig. 14(a) shows the superimposed current waveforms of single and twenty-fold sampling and updating, where it can be observed from the close-up view that about 100 µs of time delay was mitigated by twenty-fold sampling and updating,  while Fig. 14(b) shows a comparison of the waveforms of single and twenty-fold sampling and updating, where about 1.75 units of difference can be observed before and after the transition, while about 6.7 units of difference can be seen during the grid-connected mode. From the close-up view, it can be observed also that about 100 µs of time delay in hooking to the grid was mitigated using the technique of twenty-fold sampling and updating, while there was no noticeable difference in its waveform when dropping from the grid. Table 3 displays the THDs as well as the improvement in time delay accomplished by these controllers. It is evident from the table that there was a significant improvement of 50 µs when double sampling and updating was applied to the PZCNRA. This increase was sustained proportionally up to quadruple sampling and updating, and smaller proportional increases were observed with the increase in the number of sampling and updating up to 50-times sampling and updating, referred to as the multi-sampling multiupdating approach in this research work. Table 4 displays the THDs of these controllers at the sampling and switching frequencies specified (10 kHz) without taking into account any time delay that may be present in the system. Based on the observation, we concluded that quadruple sampling and updating is the optimal time-delay compensation technique to be used on micro-controllers, a device that can be easily implemented.

VI. CONCLUSION
The digital control of a deadbeat three-phase grid-connected inverter with time delay for five different controllers was VOLUME 11, 2023 designed and evaluated in this paper. The existence of time delay in a control loop causes a substantial phase shift at one decade below the switching frequency. Because of this effect, a controller is unable to achieve its full potential bandwidth. In order to make this phase shift less noticeable, two time-delay compensation techniques summarized in [9] were put together as one, i.e., the technique of deadbeat control and the technique of shifting the sampling and updating instants. The optimal technique of shifting the sampling and updating instants was evaluated and found to be quadruple sampling and updating. This technique mitigated a time delay of about 80 µs both during off-grid and grid-connected modes. For the deadbeat control technique, time delay was modeled in the plant before the designing of the controllers was carried out, and the designed controllers successfully eliminated the delay that existed in the plant that was controlled. Additionally, a tuning polynomial was used in the controllers' design, which ensured that the controllers were not too aggressive and robust against parameter variation, especially grid-impedance variation. Based on the frequency response plots and the THDs, as tabulated in Table 3, it can be concluded that this proposed combination gave an outstanding output, which showed a considerable improvement from that of double sampling and updating and a closer range of mitigation to that of the multi-sampling multi-updating technique. Moreover, this optimal design can be easily implemented on microcontrollers, which are not only inexpensive but also simple to use.
In summary, the primary contribution of this study is assessing and defining an equilibrium point between the double-sampling technique, which is implemented on micro-controllers, and the multi-sampling multi-updating technique, which is normally implemented on FPGAs.
In conclusion, the deadbeat current control with time delay modeled in the plant coupled with quadruple sampling and updating is a viable time-delay mitigation control approach which does not require anti-aliasing filter in the feedback loop, provided that an appropriate tuning polynomial is applied.
Experiments to verify the detailed simulations employed here might be a fruitful line of inquiry for further studies in the future.