High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications

This paper presents a fast switching and high-powered single-pole double-throw (SPDT) switch for RF switch circuits, such as TRx antenna switches and frequency band (or operation mode) selection switches in mobile handset applications. For fast switching time and performances of the RF switch, we proposed a novel method that can “selectively” control the impedance of a gate biasing circuit (“high” or “low” impedance). The proposed SPDT switch use the low impedance of the gate biasing circuit for fast switching time and use the high impedance of the gate biasing circuit to avoid the degradation of the insertion loss and harmonics. The proposed SPDT switch has no additional bias and no large payment for size consumption. According to measurement results, the turn-on switching time of the proposed SPDT switch was <inline-formula> <tex-math notation="LaTeX">$0.35~\mu \text{s}$ </tex-math></inline-formula> (at 2 GHz). The insertion loss, isolation, and return loss at 2 GHz were 0.16 dB, 47.1 dB, and 24 dB respectively. 2nd and 3rd harmonic levels at 25 dBm input power at 2 GHz were −88.7 dBm and −78.9 dBm, respectively. Power handling capability was 39.5 dBm of input power at 2 GHz. The designed SPDT switch was implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> partially depleted silicon-on-insulator (PD-SOI) process.


I. INTRODUCTION
The time division duplexing (TDD) technique has been used since the introduction of long-term evolution (LTE), including in the 5th-generation (5G) mobile communication. Because TDD uses the spectrum more flexibly than frequency division duplexing (FDD) and is better suited to burst traffic demands, TDD has become a more attractive duplexing method than FDD. But to deliver even one round trip transmission of a control signal or a data signal, several uplink (UL) and downlink (DL) cycles are required in the TDD system. This leads to the requirement of fast and flexible link direction switching [1]. UL and DL switching guard times are limited by the interface latency and Tx/Rx switching time. Thus, the importance of the switching time of the antenna switches is increasing.
The associate editor coordinating the review of this manuscript and approving it for publication was Mauro Fadda .
As the switching time of the antenna switch becomes important, methods for improving the switching time have been proposed. To reduce the switching time, reference [2] and [3] proposed the methods that are optimizing or using complex analog circuits with the reduced gate biasing resistors. Reference [2] optimized the transistor size of the logic driver and reduced the gate biasing resistors. For fast switching time, reference [3] used high operating voltage of ''3 V'' that is higher than the supplied voltage of 1.8 V. But, to make high operating voltage of 3 V, a low dropout (LDO) circuit and a charge pump circuit should be added inevitably. And reference [3] also used the reduced gate biasing resistors for the purpose simultaneously. Since these both methods reduced the gate biasing resistors for fast switching time, however, the insertion loss and 2nd harmonic are unfortunately degraded accordingly.
Therefore, in this work, to avoid the performance degradation of the insertion loss and 2nd harmonic, we proposed VOLUME 11, 2023 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/  The time diagram about the impedances of both conventional method that have been using the reduced gate biasing resistors and proposed method that selectively control the impedance of the gate biasing circuit.
a novel method that can ''selectively'' control the impedance of a gate biasing circuit (''high'' or ''low'' impedance). Fig. 1 shows a conventional structure with fixed gate biasing resistors ( Fig. 1(a)), and the proposed structure with the selective control of gate biasing circuit ( Fig. 1(b)). The time diagram about the impedances of the conventional method which has been using the ''low'' gate biasing resistors and the proposed method which ''selectively'' control the impedance of the gate biasing circuit is described in Fig. 2. For fast switching time, the biasing resistor bypass circuit (BRBC) in the Fig. 1(b) is turned ''ON'' to reduce the impedance of the gate biasing circuit just during the transient time which means the time duration between when the control signal reached 50 % of its final value and when the output signal reached 90 % of its target maximum RF peak value (A-region in Fig. 2). And then, BRBC is turned ''OFF'' to make ''high'' impedance of the gate biasing circuit during normally ON-state of the RF switch (B-region in Fig. 2), so the proposed RF switch can be implemented without any performance degradation of the insertion loss and 2nd harmonic. Thus, the proposed method is suitable for applications such as high-power user equipment (HPUE) and multi-band antenna switches. This paper is organized as follows. In Section II, we introduce the main factors affecting the switching time of typical RF switches and the design concepts of the fast switching and high-power handling method of the proposed SPDT switch. The simulation results, the measurement setup and the implemented measurement results are presented in Section III. And Section IV concludes this paper.

II. DESIGN CONCEPT
A. SWITCHING TIME ANALYSIS OF TYPICAL HIGH-POWER RF SWITCH As shown in Fig. 1(a), the conventional structure has been used a floating gate/body [4], negative biasing [5], and stacked-FET [6], [7], [8]. However, to handle a high-power while using conventional structure, these techniques use large value gate resistors (R G ) and common gate resistor (R GC ). These resistors slow down the voltage charging and discharging time by limiting the transient current (i g_trans ). Also, transistors with wide total gate width used to improve the insertion loss slow down the voltage charging and discharging time by large value parasitic capacitors such as gate-source capacitors (C gs ) and gate-drain capacitors (C gd ) [8]. If transistors are replaced by parasitic capacitors (C gs , C gd ) as shown in Fig. 1(a), this circuit is a kind of the RC charging/discharging circuit.
Thus, there are two methods to control the switching time: one is to control the biasing resistors and the other is to control the size of the transistors. In this paper, R GC which affects all the stacked-FETs, was selectively controlled by the proposed biasing resistor bypass circuit (BRBC) as shown in Fig. 1(b).

B. DESIGN STRUCTURE OF THE BRBC
Typically, to reduce the insertion loss, wide transistors have been used in the series branch. And since wide transistors cause the large parasitic capacitances (C gs , C gd ), the series branch represents the dominant part of the switching time. As shown in Fig. 3, to control the dominant part of switching time, the BRBC is only implemented in the series branch of the SPDT switch. To improve the switching time of the BRBC, the BRBC is designed with narrow total gate width transistors. And since the BRBC has to handle the RF peak voltage that are induced from the RF signal path, BRBC  is designed with 8 stacks transistors. To decrease the RF signal leakage, when the BRBC is OFF-state, 5 k bypass resistors (R BYP ) are used for each of the transistors in the BRBC as shown in Fig. 3. A 1 k series resistor (R SE ) is also used to decrease the harmonic level and increase the power handling capability. To control the ON-state and OFF-state of the BRBC, a switch controller is designed and integrated into the chip.

C. HIGH-POWER HANDLING AND FAST SWITCHING TIME SCHEME OF BRBC
To briefly explain the fast switching operation of the SPDT switch, when the BRBC is turned on, the impedance of BRBC (Z BRBC ) is reduced due to the on-resistances of the transistors in the BRBC. Through this, fast switching time can be achieved. And when the BRBC is turned off, Z BRBC is high impedance due to the R BYP and the off-capacitance of the transistors in the BRBC. This high impedance minimizes the degradation of the insertion loss and 2nd harmonic during the normally ON-state. As shown in Table 1 and Fig. 4, in the A-region, to quickly turn on the RF switch, transistors in the BRBC are turned on with a transistor gate voltage in the BRBC (V G_BRBC ) of 2.5 V during the switching time of the SPDT switch. In the B-region, the series branch of the RF switch is ON-state. Thus, the DC voltage of the drain and source of the BRBC's transistors is 2.5 V. For high-power handling capability of the SPDT switch, BRBC also has to handle high RF peak voltage. Thus, negative biasing and OFF-state are applied to the BRBC by the V G_BRBC of 0 V. In the C-region, to quickly turn off the RF switch, transistors in the BRBC are turned on with the V G_BRBC of 2.5 V. In the D-region, the series branch of the RF switch is OFF-state.
Thus, the DC voltage of the drain and source of the BRBC's transistors are −2.5 V. The V G_BRBC of −2.5 V can't apply the negative biasing technique and OFF-state for the BRBC simultaneously. Thus, this work uses the ON-state of BRBC with the V G_BRBC of 0 V. And R SE which is significantly higher impedance (1 k ) than the on-resistances of the transistors is used in the BRBC as shown in Fig. 3. When the SPDT switch is OFF-state and the BRBC is ON-state, most of the RF peak voltage between the source voltage of the BRBC (v S_BRBC ) and the gate voltage of the series branch (V G_SE ) is applied not to the transistors in the BRBC but to the R SE . The relationship between the R SE , the number of stacks of BRBC, and RF peak voltage that BRBC has to handle is: Here, BV DS represents the unit transistor breakdown voltage between the drain and source, v S_BRBC represents the RF peak voltage with the DC voltage at the source of the BRBC, v sd_brbc (= v S_BRBC − v D_BRBC ) represents the RF peak voltage between source and drain of the BRBC transistors, Z TR_BRBC (= Z BRBC − R SE ) represents the impedance between the drain and source of the total BRBC transistors, m represents the number of transistor stacks in the BRBC, and V G_SE represents the DC gate biasing voltage of the RF switch. These variables are illustrated in Fig. 3. As shown in (1), increasing the number of transistor stacks (m) in the BRBC and increasing the R SE alleviate the RF peak voltage that the unit transistors in the BRBC has to handle. However, the increased R SE slows down the switching time. Through this and the relationship between the R GC and the switching time which is described in Section II-A, the R SE is consequently the trade-off point between the power handling capability and the switching time.

D. CONVENTIONAL STRUCTURE AND PROPOSED STRUCTURE COMPARISON ACCORDING TO GATE BIASING RESISTANCES
As mentioned in Section II-A, the value of the biasing resistors is the dominant factor of the switching time. And they also affect the insertion loss and 2nd harmonic level of the RF switches. Thus, to compare the conventional structure and proposed structure, these cases are simulated and described in Table 2. Case-0 used biasing resistors of commonly used values, such as R GC of 50 k and the R G of 50 k . Because of the high value of biasing resistors, intrinsic insertion loss is 0.144 dB, switching time is 1.36 µs, and 2nd harmonic level at 25 dBm input power is −79.7 dBm. Case-1 has a switching time similar to that of the proposed structure with the R GC  But the insertion loss and 2nd harmonic level at 25 dBm input power are more degraded than Case-1. Through this, biasing resistors are one of the dominant trade-off factors between switching time, the insertion loss and 2nd harmonic level. To improve these performances, BRBC structure is proposed. The proposed structure has a switching time similar to Case-1, but the insertion loss is improved 14.8 % and the 2nd harmonic level is improved 5.7 % compared to the conventional Case-1.

III. MEASUREMENT RESULTS AND COMPARISON
The designed SPDT switch was fabricated using the 0.13-µm PD-SOI CMOS process, as shown in Fig. 5. The size  of the additional circuits including the BRBC was 0.010 mm 2 each series branch. All the circuit components which are the RF switch, ESD protection block, level shifter, and proposed BRBC were integrated into a single chip of 620 µm × 440 µm. All measurements were performed using a probe tip on the multi-layer printed circuit board (PCB).

A. SWITCHING TIME
The switching time was simulated and measured at the RF frequency of 2 GHz. As shown in Fig. 6, to iteratively control the ON-state and OFF-state of the SPDT switch, a function generator (Tektronix AFG1022) was used to generate a 50 kHz square wave that varies between 0 V and 2.5 V. This wave function was applied as the control bit of the SPDT switch and to trigger the spectrum analyzer (Keysight PXA-N9030A). Spectrum analyzer measures the RF power to measure the switching time of the SPDT switch. As shown in Fig. 7, the measured RF power was converted to a percentage of the maximum RF peak voltage in the normally ON-state of the SPDT switch. The switching time was defined as time duration between when the control signal reached 50 % of its final value and when the output signal reached 90 % of its target maximum RF peak value [2], [9], [11], [12], [13]. The measured turn-on switching time of the proposed SPDT switch was 0.35 µs. The measurement results follow the simulation results well.

B. S-PARAMETER
The S-parameter of the SPDT switch was measured by the network analyzer (Rohde-Schwarz ZVA50). All the measured  results were de-embedded by an open-short pattern of the PCB. As shown in Fig. 8, the measurement results of the proposed SPDT switch were 0.16 dB of the insertion loss, 47.1 dB of the isolation. Antenna-port return loss, ON-port return loss and OFF-port return loss were 24.0 dB, 24.2 dB, and 1.4 dB respectively.

C. POWER HANDLING CAPABILITY AND HARMONICS
The harmonic level and power handling capability of the SPDT switch were measured by the spectrum analyzer (Keysight CXA-N9000A). The measurement setup of the harmonic level and power handling capability are shown in Fig. 9. The fundamental signal (2 GHz) was generated by the signal generator (Keysight N5182A). To apply the fundamental large signal to SPDT switch, the fundamental signal was amplified by gain-amplifier (RFHIC RWP15080-10). To decrease the 2nd and 3rd harmonic signals generated by the gain-amplifier, a low pass filter (Microwave Circuits L2G04G81) was added after gain-amplifier. For the monitoring of the input and output fundamental signal power, the coupler (Krytar 158010) and power-meter (Keysight E4417A) are used. A high pass filter (Mini-circuits VHF-2700A+) was used to lower the output signal power to a low level that the spectrum analyzer (Keysight CXA-N9000A) can endure. The input power calibration was performed to measure in real-time the input power. And the output calibration was performed to confirm the switch path ON-state and OFFstate operation. To compensate the harmonic level, the loss of output due to high pass filter was measured and the harmonic results are compensated for that loss. The proposed switch achieved an input power handling capability of 39.5 dBm. The proposed SPDT switches exhibited 2nd harmonic level of −88.7 dBm, and 3rd harmonic level of −78.9 dBm at an input power of 25 dBm at 2 GHz. Table 3, the measurement results of the proposed SPDT switch are summarized and compared to stateof-the-art SPDT switches. References with faster switching VOLUME 11, 2023 times than this work have lower power handling capabilities [2], [3], [10]. If these references increase the number of stacked transistors to improve the power handling capability, not only increase the insertion loss, but also slow down the switching time correspondingly. Other references that have similar high-power handling capability have very slow switching times like 1.7 µs and 4 µs [9], [11]. And if these references lower the value of the biasing resistors to reduce the switching time, the insertion loss increases too. Therefore, we have proposed the SPDT switch with BRBC to achieve high-power handling capability, fast switching time, low insertion loss and low 2nd harmonic level.

IV. CONCLUSION
To verify fast switching time with the BRBC, the proposed SPDT switch was fabricated and measured. The proposed SPDT switch achieved a switching time of 0.35 µs at 2 GHz. The insertion loss, isolation, and return loss at 2 GHz were 0.16 dB, 47.1 dB, and 24 dB respectively. The 2nd and 3rd harmonic levels at 25 dBm input power at 2 GHz were −88.7 dBm and −78.9 dBm, respectively. Power handling capability was 39.5 dBm input power at 2 GHz. In a further work, the BRBC will be applied to high order switches such as SP4T and SP8T in order to generally verify its usefulness. He holds more than 60 U.S. patents on power-amplifier technology and RF integrated circuits. His current research interests include monolithic microwave integrated circuit design for mobile communication and millimeter-wave systems, the thermal packaging analysis of high-power devices, and intermodulation and noise analysis of nonlinear circuits.