IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control

This paper clarifies the effect of gate inductance <inline-formula> <tex-math notation="LaTeX">$L_{g}$ </tex-math></inline-formula> inside IGBT modules on gate voltage spikes when a digital gate driver is employed. Three IGBT modules with different <inline-formula> <tex-math notation="LaTeX">$L_{g}$ </tex-math></inline-formula> were fabricated to implement double pulse tests by conventional gate driving and digital control gate driving with three-step vectors. It was found that the tradeoff between switching loss and voltage/current overshoots can be improved by digital control, but a large gate voltage spike was generated when gate-driving vectors were changed. And the spike voltage <inline-formula> <tex-math notation="LaTeX">$V_{g\_{}spike}$ </tex-math></inline-formula> was positively correlated to the <inline-formula> <tex-math notation="LaTeX">$L_{g}$ </tex-math></inline-formula>. Although the <inline-formula> <tex-math notation="LaTeX">$V_{g\_{}spike}$ </tex-math></inline-formula> can also be suppressed by decreasing the difference of gate driving vectors between the first and the second steps, the improvement of the tradeoff is weakened. Therefore, it is required that the <inline-formula> <tex-math notation="LaTeX">$L_{g}$ </tex-math></inline-formula> inside the IGBT modules should be reduced to suppress the <inline-formula> <tex-math notation="LaTeX">$V_{g\_{}spike}$ </tex-math></inline-formula> while improving the tradeoff by the digital gate driver at the same time. Furthermore, by analyzing the oscillation of the <inline-formula> <tex-math notation="LaTeX">$V_{g\_{}spike}$ </tex-math></inline-formula>, it indicates that there should be some other stray elements, which couple <inline-formula> <tex-math notation="LaTeX">$L_{g}$ </tex-math></inline-formula> and the stray capacitance inside IGBT chips, affecting the <inline-formula> <tex-math notation="LaTeX">$V_{g\_{}spike}$ </tex-math></inline-formula>.


I. INTRODUCTION
Insulated Gate Bipolar Transistor (IGBT) power module is a key component in various power electronics applications today, such as electric vehicles, industrial motor drives, and transportation [1]. The recent development of IGBT modules is focused on increasing power densities and switching frequencies and achieves design optimization and cost reduction for power conversion systems. Power electronics systems require not only low power loss but also low electromagnetic interference (EMI) noise for high-cost performance by system downsizing. Because EMI noise is induced by high dV/dt, large surge voltage, and high dI/dt, large surge current, switching tradeoff characteristics of power semiconductor devices between loss and noise must be considered in the system design.
The associate editor coordinating the review of this manuscript and approving it for publication was Mostafa Rahimi Azghadi .
For conventional gate driving, the switching performance can be adjusted by changing the gate resistance, but the switching tradeoff characteristics cannot be improved. However, thanks to the simple gate driving pulse, there is almost no unexpected gate voltage V g oscillation and gate voltage spike V g_spike in the switching period [2], [3] except the IGBT is under special conditons [4], [5], [6]. Recently, the digital gate driver (DGD) is a promising technology to improve the switching tradeoff characteristics. Several groups have demonstrated the improvement of tradeoff between turn-on loss E on and the current overshoot I overshoot of collector current I c and the tradeoff between turn-off loss E off and voltage overshoot V overshoot of collector-emitter voltage V ce in power transistors (e.g., IGBT, MOSFET) compared with the conventional fixed gate resistance driver [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17]. However, because the operation mechanism of the DGD is dynamically controlling the gate driving current during the switching transients, the transient change of gate current I g will become complicated and aggressive, so V g_spike is generated and have a risk to destroy the DGD [1], [7], [8], [9], [10]. There is no research about how to suppress the V g_spike while improving the tradeoff characteristics when DGD is employed.
Because the timing of gate voltage spike corresponds to the change of digital control vectors, which means I g is pulled up or pulled down [1], [7], [8], [9], [10], it can be expected that V g_spike results from the coupling of dI g /dt and stray gate inductance L g inside IGBT power modules. In previous works, although the relation between current charge and stray inductance of the main circuit loop inside power modules at conventional gate driving for suppressing the collector voltage surge was reported [18], [19], gate inductance design of IGBT module for DGD have not been investigated.
This paper reports an experimental clarification of the effect of L g inside IGBT modules and dI g /dt on V g_spike . Three IGBT modules with different L g were fabricated, and the change of gate driving vectors n, which led to a large change of I g , was also investigated to show the effect on V g_spike . Moreover, the effects of L g and n on the switching tradeoff characteristics were analyzed to show the necessity of reducing L g . Furthermore, the origin of the gate voltage spike is discussed by the oscillation of V g_spike .

II. EXPERIMENT SETUP
Three IGBT modules, whose breakdown voltage was 680V and rated current was 200A, with different L g were fabricated. By applying different radii and lengths of wires connecting IGBT chip and gate terminals, different L g could be realized and the values were estimated by COMSOL. Fig. 1 shows the model of fabricated IGBT modules and Table 1 shows the dimensions of gate wires and calculated L g as shown in Table 1. Fig. 2 shows a photograph of Sample-B. The half-bridge circuit is a basic configuration of the power electronics circuit. In this work, the high-side IGBT was omitted from the half-bridge circuit, because the module was designed specifically for evaluating the switching characteristics of the low-side IGBT. Therefore, the results of this verification can also be applied to power electronics circuit   design. Fig. 3 is the measured capacitance characteristics of the IGBT chip. C ge was 8 nF, and C gc was 0.28 nF at V ce = 20 V. Fig. 4 shows the circuit schematic for the double pulse test to measure the turn-on and turn-off characteristics of the above IGBT modules. Fig. 5 shows the photo of the experiment setup. To minimize the parasitic inductance of connecting wire, the digital gate driver was connected to the IGBT module directly by a terminal rather than wires. The stray inductance of the connection terminal was about only 2 nH, which was estimated by COMSOL. So, the parasitic inductance of the connecting part was negligibly small. The L g in Fig. 4 represents the gate inductance inside IGBT modules. The measurement system included a 6-bit programmable DGD. To realize a programmable 63-level drivability in the programmable digital gate driver, 63 parallel transistors were connected to the gate of IGBT and a 6-bit VOLUME 11, 2023  control signal was plied to specify the number of activated NMOS and PMOS transistors n NMOS and n PMOS [1], [10]. Current source three-step active gate drivers were proposed by previous papers [7], [8], [9]. Based on the same operation  mechanism, the gate driving method was proposed as follows. Fig. 6 presents the turn-off and turn-on waveforms by the conventional gate driving without the digital gate control. The DGD output current I g can be increased with n NMOS and n PMOS and controls turn-off and turn-on switching speeds. A constant of the n NMOS or n PMOS corresponds to the conventional gate driving shown in the figure. In this work, n NMOS and n PMOS were set to an integer from 5 to 63 to implement double pulse tests without digital gate control. Voltage overshoot V overshoot in the turn-off period and current overshoot I overshoot in the turn-on period were defined as shown in Fig. 6a and Fig. 6b.
In the digital gate control, the n NMOS and n PMOS were set to three different values at each period n1, n2, and n3 in the whole turn-off and turn-on stages as shown in Fig. 7. The n1, n2, and n3 were also set to integers from 5 to 63. The V g_spike was the amplitude of V g after the vector was changed from n1 to n2 as shown in Fig. 7a. Tables 2 and 3 show vectors employed in this work for turn-off and turn-on switching with digital gate control. In the turn-off waveform without digital gate control shown in Fig. 6a, the V ce rises gradually when the I c is still the load current, which results in energy loss in this stage. In the digital gate control of Pattern-a, the n1 was set as the maximum of 63 to shorten the stage before I c started to decrease. In the I c decreasing stage, a large V overshoot occurs due to the large dI c /dt, so the n2 should be set as a small value to slow down the dI c /dt. After that, the main stages correlated with V overshoot and E off are almost passed, so the n3 was set as 63 to complete the turn-off as soon as possible. In contrast, digital gate control Pattern-b, where n1 was set as 20, was proposed to compare to Pattern-a to show the effect of n. The setup of vectors shown in Table 3 for turn-on was similar to that for the turn-off. To shorten the delay time during turn-on shown in Fig. 6b. n1 was set as 63. And n2 was set as 5 in Pattern-a to slow down the change of V ce to decrease the I overshoot . As same as Pattern-a, n3 was set as 63 to complete the turn-on switching with a large voltage slew rate.
And the control signals of the DGD were generated by National Instruments LabVIEW and PXIe-5670 module. The range of gate voltage was from 0 V to 15 V. In addition, the experiment system was operated under a supply voltage of 300 V and a load current of 100 A. Fig. 8 shows typical switching waveforms by conventional gate driving of Sample-C, whose L g was 54 nH when n NMOS and n PMOS were set as a constant value of 9 in turn-off and turn-on periods. n NMOS and n PMOS were 0 before switching and then rose to 9 during the switching period. Under this condition, V overshoot was 229.0 V and I overshoot was 68.1 A.

III. RESULTS
The E off and E on were 8.9 mJ and 5.1 mJ, respectively. Fig. 9 shows the waveforms of Sample-C under the digital gate control of Pattern-a. In the turn-off period, the n NMOS was pulled up to n1 of 63 from 0 to start the turn-off, then n NMOS was pulled down to n2 of 5. Finally, the n NMOS was kept as n3 of 63 to complete the turn-off and keep the off-state. In the turn-on period, gate driving vectors were the same as in the turn-off, except for the time duration. Under this digital gate control, V overshoot and I overshoot were 188 V and 53.3 A. E off and E on were 8.4 mJ and 4.6 mJ. Compared to conventional gate driving without digital gate control, the V overshoot and I overshoot were reduced clearly, while the switching loss was almost kept at the same level. In addition, at the time when n1 was pulled down to n2, which led to a large transient gradient of I g , and large V g_spike of 14.5 V was shown in the turn-off. In contrast, The V g_spike in turn-on was small as 4.7 V because the I g was smaller compared to that in the turn-off due to the difference of on-resistance between PMOS and NMOS transistors in DGD. Fig. 10 shows the waveforms of Sample-A, whose L g was 7nH, under the same digital gate control of Pattern-a in Fig. 9.
Comparing to the results of Sample-C in Fig. 9, the V g_spike in turn-off decreased to 10.3 V, and the V g_spike in turn-on decreased to 2.9 V. It is obvious that the V g_spike can be suppressed by reducing the L g . Fig. 11 shows the waveforms of Sample-C under digital control of Pattern-b, in which n1 was set as 20. Because of a smaller n than that in Fig. 8, the dI g /dt became smaller. The V g_spike in turn-off decreased to 4.5 V, and the V g_spike in turn-on decreased to 3.9 V. It indicates that reducing n can also be an alternative to suppress V g_spike .
The tradeoff between E off and V overshoot in the turn-off switching and the tradeoff between E on and I overshoot in the turn-on switching were improved by digital gate control compared to conventional gate driving as shown in Figs. 12 and 13. Because small vectors make the IGBT switching at a slow speed, the dI c /dt and dV ce /dt become smaller resulting in the overshoot being suppressed. However, due to the long switching period, switching loss increases. Therefore, the tradeoff relationship was shown in both turn-off and turn-on switching characteristics. In Fig. 12, both two digital control patterns improved the tradeoff. The loss in digital control Pattern-a obtained lower power loss than that in Pattern-b. It is because the time before V ce began to rise at a large rate in Fig. 9a was about only half of that in Fig. 11a. In Fig. 13, the results also prove that both the two digital control patterns improved the tradeoff, and the improvement was almost the same under the two patterns. It is because E on and I overshoot were determined mainly by n2 in the second period.
The tradeoff characteristics were almost independent of the L g as shown in Fig. 12 and 13. It is verified that the tradeoff characteristics were determined mainly by the stray inductance in the main circuit loop L e and L c , and the gate drive signal was applied to the IGBT chip normally even at large L g conditions. The tradeoff curve of Pattern-b for VOLUME 11, 2023     Sample-C was slightly different from those of Sample-A and Sample-B as shown in Fig. 12. It would be resulted from switching performance variations of IGBT chips.

A. EFFECT OF GATE INDUCTANCE ON GATE VOLTAGE SPIKE
Because the V g_spike in turn-off was much smaller than that in turn-on, the V g_spike in turn-off was focused to investigate. All three types of samples were implemented double pulse tests by digital gate control shown in Table 2. Fig. 14 shows the relation between V g_spike , L g , and n, which was the difference between n1 and n2 as shown in Table 2. It indicates that the V g_spike was positively correlative to n and L g . Furthermore, the relation between V g_spike and L g under the same digital gate control vectors (n1=63, n2=8, n3 =63) is plotted in Fig. 15. Although V g_spike was positively correlative to L g , the relation was not linear. Therefore, it can be speculated there should be other elements, except for the L g , affecting the V g_spike .

B. EFFECT OF GATE INDUCTANCE AND N ON TRADEOFF
It is discussed about the module and digital gate control designs to cope with both the improvement of the tradeoff and suppression of V g_spike as follows. To appraise the improvement of the tradeoff, the objective function (f OBJ ) as given by Eq. (1) [1], [10] is employed. Small f OBJ means good improvement of tradeoff.  The subscript max signifies the maximum of the corresponding quantity from the experiment results. The relation between f OBJ and V g_spike under Pattern-a and Pattern-b conditions is plotted in Fig. 16. The n of Pattern-b was smaller than that of Pattern-a. Although the V g_spike can be suppressed by decreasing n due to small dI g /dt, for the same sample, Pattern-b had a larger f OBJ than Pattern-a. This proves that the improvement of the tradeoff in the turn-off was weakened if n was decreased. Moreover, Sample A, whose L g was the smallest, had the smallest f OBJ and V g_spike . Therefore, it is the better choice to reduce the L g to suppress the V g_spike and ensure good improvement of the tradeoff for designing IGBT modules driven by the DGD.

C. ANALYZATION OF OSCILLATION OF GATE VOLTAGE SPIKE
To discuss the origin of the gate voltage spike, the oscillation cycle of V g_spike after n NMOS changed from n1 to n2 was analyzed. As shown in the schematic circuit in Fig. 4, the oscillation of V g_spike would be introduced by the LC circuit in the gate loop, which includes L g , C ge , and C gc . And the oscillation period T is given by   According to the results of Pattern-a for three samples, the relation of T and L g is plotted in Fig. 17. T was positively correlated with L g , which was corresponding to Eq. (4). When n1 rose to n2, C ge is 8 nF and C gc is 0.28 nF as shown in Fig. 3. By substituting T , C ge , and C gc , into Eq. (4), the total inductances of three samples are shown in Table 4. L ′ was the calculated total inductance when substituting T and C ge , and L ′′ was the calculated total inductance when substituting T and C gc . L ′ is much smaller than L g , so V g_spike does not result from the resonance of L g and C ge . Although L ′′ is about 10-20 nH larger than L g , considering T is positively correlated to L g . Therefore, the V g_spike would depend on the resonance of an LC circuit including L g , C gc , and other stray inductances. In Fig. 9, Fig. 10, and Fig. 11, there is an oscillation, whose oscillation cycle time is longer than V g_spike happening after n1, and the oscillation is linked with changes in V ce and I c , it can be considered that the C gc and L e influence on the gate voltage.

V. CONCLUSION
This paper clarified the effect of gate inductance on gate voltage spikes when the IGBT modules are driven by a DGD. Although the digital gate control improves switching noiseloss tradeoff, a large gate voltage spike occurs in turn-off. The gate voltage spike was positively correlated with gate inductance and difference among gate control vectors. Reducing the gate inductance inside IGBT modules driven by the DGD is necessary to cope with both the improvement of the tradeoff and suppression of gate voltage spikes. Furthermore, V g_spike would be dependent on the resonance of an LC circuit including L g , C gc , and other stray inductances rather than an LC circuit including L g and C ge .