A Dual-Source Self-Balanced Switched-Capacitor Reduced Switch Multilevel Inverter with Extending Ability

Multilevel inverters (MLIs) with switched-capacitor (SC) combinations are widely recognized to improve the power quality and efficiency of the renewable energy and high-frequency power distribution systems. Self-balancing of SCs and voltage boosting ability are the salient features of the recently developed SC MLIs. This work presents a new SC MLI structure using a reduced number of switches and two dc sources. For increasing the voltage levels, the basic units of the proposed MLI can be extended without increasing the number of dc sources. By suitable charging-discharging patterns, the SCs are self-balanced and voltage boosting is achieved. Comparative analysis with prior-art MLIs demonstrates the merit of topological advancement. Further, extensive simulation and experimental results confirm the feasibility of the proposed MLI under different loading and dynamic operating conditions.


I. INTRODUCTION
Multilevel inverters (MLIs) are the suitable choice for renewable power generation, variable speed drives, and high-frequency power distribution [1]- [3] due to the abilities such as enhanced power quality, high modularity, improved efficiency, and low voltage stress. The conventional neutral point clamped MLI (NPC MLI) and flying capacitor MLI (FC MLI) uses a single dc source, whereas the cascaded H-bridge MLI (CHB MLI) consists of several isolated dc sources. The conventional CHB MLI dominates over the other two types due to the features such as high modularity, smooth fault handling capability, and high reliability [2], [4]. However, these conventional structures need a large number of switches, driver circuits, and passive components. Moreover, the additional voltage balancing and inverter module failure issues [5] also exists in the NPC MLI and FC MLI. Therefore, the research interest is growing to redesign the MLI using a lower number of components and to enable inherent voltage boosting.
In view of different applications, many alternative topologies are developed in recent years that take into account reduction in both the number of switches and source count [1], [6]. These MLIs can be broadly categorized into two types, i.e., switched-dc/diode (SD) type and switched-capacitor (SC) type. Further, these MLIs can be single-dc or multi-dc type. The multi-dc MLIs can be symmetric or asymmetric type based on the magnitude of the dc sources. Multi-terminal SD MLI as disclosed in [7] reduces the switch count, but the number of dc sources remains the same as the conventional MLI. The generalized SD MLI in [8] avoids the back-end full-bridge to synthesize negative voltage levels and thus reduces the voltage stress. To achieve higher number of voltage levels at the output, the CHB MLI topology is modified in [4], [9] by connecting level doubling circuit to it. Self-balanced capacitors are used to reduce the utilization of the dc source significantly. SD MLI topology disclosed in [10] for the photovoltaic (PV) application uses the similar concept. The structure presented in [11] can be extended for producing higher voltage steps and it is suitable for the standalone PV systems. These structures reduce the switch/drivers count considerably and possess a simpler control circuit. However, these MLIs lack the ability to boost the voltage.
A novel approach is suggested in [12] to reduce the dc source count utilizing capacitors in the circuit. This topology can operate in symmetrical as well as in asymmetrical mode. Thus, maximum voltage steps can be created at the output by selecting the magnitude of the dc sources asymmetrically. The SC MLIs proposed in [13] requires additional sensors and voltage balancing controller to regulate the capacitor voltage. Unlike these topologies, new reduced switch SC MLIs are proposed to inherently boost the output voltage without using large-sized transformers and inductors. The generalized SC MLI structures introduced in [14]- [16] can inherently charge the capacitors and features high voltage boosting. The capacitors are self-regulated at the desired voltage using the series-parallel charging-discharging technique. The SC MLI structure proposed in [17], [18] also features high voltage gain, but a modified H-bridge is used in the circuit and thus, the voltage stress is very low. Multi-dc SC MLIs are further explored in [19], [20], which avoids the use of conventional H-bridge. The SCs in the MLI proposed in [21], [22] are charged to asymmetrical voltage and thus can generate more levels using less number of switches. The SC MLI structures disclosed in [23], [24] uses only two dc sources. These topologies have the possibility of cascaded extension for enhancing the voltage level, however; the topology in [24] doesn't require the additional dc sources in doing so.
Furthermore, single dc SC MLIs have been proposed in [3], [15], [25], which uses a back-end H-bridge for changing the polarity. High voltage boosting is achieved in [15], [25], but at the cost of a large number of switches. Due to the presence of series-diodes in the conducting path, the topology [25] is inadequate for operating with high inductive loading. The capacitor current spikes are effectively reduced using the SC MLI proposed in [3]. However, this topology is inefficient to boost the voltage magnitude. Also, without using the conventional H-bridge new single dc SC MLIs have been emerged. The disclosed MLI in [26] generates 5-level output with twice voltage boosting. The MLIs in [27] and [28], [29] can generate a 7level output with 3 times and 1.5 times voltage boosting, respectively. The former topology features single-phase extendibility, whereas the latter has the flexibility to extend in three-phase as well. A single-dc extendable MLI proposed in [30] requires a large number of switches. Single dc 9-level SC MLIs proposed in [31] has quadrupled boosting ability whereas [32], can boost the voltage magnitude to two-times. The voltage stress reduction is significantly achieved, scarifying the switch count. The evolution of self-balanced SC modules is depicted in Fig. 1.  [14], [17], [21], (b) [22], (c) [19], (d) [27], (e) [31] Motivated by the recent developments, this work presents a novel MLI topology with following salient features: i. Total number of switches and capacitors per level is significantly reduced. ii. Only two dc sources are employed to produce N l -level output, thus reduces total cost of the MLI. iii. The capacitors used in the proposed topology are charged through a common switch, possess selfbalancing ability and assists voltage boosting. iv. Less than 50 % of the switches are in conduction for any voltage level and more than 50 % of switches operate at a lower frequency. Thus, the total power loss is very less. v. The proposed MLI can satisfactorily operate under high as well as low power factor loads. The next section introduces the proposed topology including the capacitor sizing and self-balancing mechanism. A comparison with the prior-art MLIs in Section III confirms the topological advancement by extensive comparison. Section IV and V discuss extensive simulation and experimental investigation, respectively, for different dynamic conditions to validate the workability of the 25-level SC MLI. Concluding remarks are provided in Section VI.

A. Recently developed 25-level SC MLIs
The circuit schematic of the recently proposed 25-level multi-input SC MLIs for renewable energy applications is shown in Fig. 2. The developed MLI in [19] consists of four sub-modules. Each module can boost the voltage magnitude to three-times. For synthesizing a 25-level output, this topology requires 4 dc sources, 8 capacitors, and 30 switches.
Similar to this MLI, the topology proposed in [20] can operate in both symmetrical and asymmetrical modes. This MLI however, lacks the ability to boost the voltage. The source count is also increased for the 25-level operation considering the symmetrical topology. Topology developed in [16] requires only 2 asymmetrical dc sources in the ratio 1:2 and 2 capacitors for generating a 25-level output. The switch count is almost halved compared to the other two types. On the other hand, the source count increases when the topology is extended for high voltage levels. The 25-level topology presented in [24] requires only two input dc sources and a very large number of switches. However, due to the presence of internal boost converter a high voltage gain can be obtained. Moreover, additional dc sources are not required in order to synthesize higher voltage levels.  [19], (b) [20], (c) [16], (d) [24]

B. Proposed SC MLI topology
The proposed dual-source switched-capacitor (DSC) MLI comprising of two input sources (N dc ) and several repeating units (RU) is shown in Fig. 3(a). The RU consists of two switches, one capacitor, and a diode. Two input sources are chosen with a proportional factor of 'x', which can be any integer, but the optimal value of it to synthesize symmetrical voltage steps can be selected using (1). The required number of switches (N sw ), drivers (N driv ), diodes (N dd ), capacitors (N c ), and the number of voltage levels (N l ) in terms of the n RUs is given in (2)(3)(4)(5). Moreover, total standing voltage (TSV) is computed as per (6) for the proposed MLI by adding the individual voltage stress of the switches. The diodes D 1 -D n and the switch S c is used to provide a path for charging of the capacitors C 1 to C n .

= + 2
(1) In the present work, two RUs (n=2) are considered. Thus, the DSC MLI synthesizes a 25-level staircase output voltage (V o ) for which the circuit operation is shown in Fig. 3(b). The two inputs (V dc & V dc /4) of the MLI appear at the output through the switches S 1a and S 2a . The capacitors C 1 and C 2 are symmetrically charged to the low-input voltage magnitude (V dc /4) through the devices D 1 , D 2 , and S c during the B-to C+ switching states. A key advantage of the proposed MLI is that the capacitors C 1 , C 2 , … C n are selfcharged through a common switch S c . These capacitors can also be charged to the higher input source magnitude. However, this may be avoided as it will block the conduction of the inbuilt diode of switches S 1 and S 3 . Moreover, C 1 and C 2 discharge to the load through S 2 and S 4 , respectively. The capacitor C b is alternatively charged throughout the negativehalf cycle and discharges to the load in a similar pattern in the positive-half cycle. S 5b and S 6b are used to connect C b in series with the load and to bypass it, respectively. The voltage across the capacitor C b is maintained such that it creates the intermediate voltage steps, which double the number of levels. Fig. 3(b) illustrates the circuit operation of the 25-level proposed MLI up to G+ and G-states. Subsequent voltage steps are generated in a similar fashion, but by complementing the states of S 1a and S 2a . The complete switching mechanism of the proposed MLI to synthesize 25level along with capacitor charging (↑) and discharging (↓) modes are illustrated in Table I. Due to operation of four switches at fundamental frequency, the total power loss is very less. Further, the proposed MLI can satisfactorily operate under high and low power factor loads due to the existence of both forward and backflow current path.

Idc1 Idc2
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.

C. Design and self-balancing of the capacitors
Longest discharging period (LDP) of the capacitors over a fundamental period is taken into account to determine the capacitance values [15], [27]. LDP is the time duration during which a capacitor discharges the maximum stored charge, as indicated in Fig. 4(a). The discharging quantity of the capacitor depends on both LDP and type of loading, which is given in (7)(8)(9). Thereby, the optimal value of the capacitance for the DSC MLI is expressed in (10), where γ is the acceptable percentage voltage ripple.
where Ф is the lagging angle between the load current (I o ) and fundamental voltage, I omax is the peak fundamental load current. Considering 240 V (V dc ), 80 Ω-variable inductive loading, and the output frequency of 50 Hz, variation in capacitance with respect to phase angle (Ф) is shown in Fig.  4(b)-(d) for different value of γ (5 %, 7 %, 10 % and 15 %). The figure implies that capacitors can be optimally selected keeping in mind the allowable voltage ripple limit and the loading value.

Value of C b (F)
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Furthermore, all the capacitor voltages in the DSC MLI are inherently balanced at the desired value without the need of any closed-loop control circuit. The voltage across the capacitors C 1 , C 2 of the proposed DSC MLI are selfregulated at the desired level (V dc /4) using series-parallel technique [25] and suitable sizing of capacitors. These capacitors discharge in series with the source according to the conduction states in Table I. The capacitors are brought in parallel with the source to charge in each cycle, thus maintaining the desired voltage across it. Alongside, the voltage across the capacitor C b is selfbalanced using the level doubling principle [10], which is mathematically verified here. Fig. 5 delineates the equivalent circuit and current flow path during chargingdischarging of C b to generate ±7V dc /8 at the output. The average current flowing through the capacitor (I cb ) during these instances with net impendence z is expressed as follows: Therefore, net charge (q) absorbed or delivered by C b over a period of T can be expressed as, Net charge absorbed or delivered by C b in the steady-state is zero. Thus, simplifying (13) gives V Cb = V dc /8. Therefore, the voltage across C b automatically reaches the desired level (V dc /8) and thereby enhances the voltage level.

III. COMPARATIVE ANALYSIS
In order to investigate the merits of the proposed DSC MLI, a comparison with several state-of-art MLIs is carried out. It is evident from Table II that the proposed DSC MLI involves 14 semiconductor switches and 13 drivers, which is lowest among all the recent-art topologies. The single-dc MLI in [31] requires a large number of switches to generate the same output but with minimum stress across the switches. Fig. 6(a) depicts the N l -level DSC MLI also requires least switch count when compared against similar extendable MLIs (T1 [25], T2 [15], T3 [3], T4 [22], T5 [7], T6 [21], T7 [27], T8 [30], T9 [14], T10 [29], T11 [31]). Compared to the proposed MLI, the single-dc MLI in [25] requires a significantly more series diodes in the load current flow path, thus this topology does not have the inductive loading ability (ILA). The proposed MLI ranks the second-lowest in terms of the capacitors requirement. The MLI disclosed in [16] requires a minimum number of capacitors, whereas the stress across all the capacitors is more than or equal to the total input voltage (N cs ), in contrast to the proposed MLI. With reduction in total switch count, the number of maximum devices in conduction (N mc ) also drastically reduced for the proposed circuit. Despite using a large number of capacitors and multiple sources in the 25-level circuit [20], the capacitor voltages cannot be added with the dc sources during maximum voltage level generation. Thus, except the MLIs disclosed in [20], all other compared MLIs, including the proposed MLI have the boosting ability (BA).
Moreover, the cost factor (CF) is evaluated for the MLIs considering the sum of number of components (N sw , N driv , N dd , N c , N dc ) and per unit TSV [8]. The weightage coefficient (w) is considered 1, in case of equal weightage to the switch count and the TSV. For more weightage to the number of switches, w<1 and w>1 when more weightage to the TSV is considered. The proposed MLI stands superior with respect to the overall CF, as can be verified from Table II and Fig. 6(b). The comparison in terms of output frequency demonstrates the SC MLIs are suitable in highfrequency power distribution systems. Various controllers are used to test the feasibility of the MLIs at different power levels, which is also summarized in Table II. The distinctive features of the proposed DSC MLI ascertain the proposed MLI is one of the suitable alternatives to synthesize high-quality output voltage using the least number of components.   T2 T1  T3  T4  T5   T6  T7  T8  T9  T10  T11 This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.

IV. SIMULATION ANALYSIS
The simulation analysis of the proposed MLI with two RUs to generate 25-level output is performed in the MATLAB/SIMULINK environment. The dual dc sources are selected as 60 V (V dc1 ) and 240 V (V dc2 ). The IGBTs with an anti-parallel diode are taken as the switching devices, capacitor C 1 , C 2 is chosen as 4700 μF and C b as 3300 μF. The carrier frequency and output frequencies are chosen as 5 kHz and 50 Hz, respectively. Phase-disposition PWM control scheme based on high switching frequency [26], [29], [31] is adopted to control the proposed MLI.
First, the MLI is tested under varying modulation index (Mi) and fixed loading (80 Ω) condition. It can be observed from Fig. 7(a) that, at 0.6 Mi some voltage steps are elapsed and the MLI operates at reduced voltage levels. At Mi > 1, the voltage level is disturbed that contributes to more harmonics in the output voltage. Therefore, Mi is fixed at 0.95 to validate the effective working in other dynamic test cases. Fig. 7(b) shows the operation of the DSC MLI under dynamic loading condition, where loading is changed from unity power factor (PF) to low PF. Output current (I o ) is a 25-level stepped waveform similar to output voltage (V o ) during pure resistive loading, however, attains a sinusoidallike waveform for the inductive type loading. The capacitor voltages (V Cb , V C1 , & V C2 ) are also presented, which implies the decrease in capacitor voltage ripple as the load is switched to highly inductive. The working of the proposed MLI is also verified under non-linear loading condition. A diode bridge rectifier is used as a non-linear load with 50 Ω-50 mH loading and the output waveform is illustrated in Fig. 7(c). All the voltage levels in V o are retained, although the ripples in the capacitor voltages are comparatively more. The average value of the capacitor voltages is maintained at the desired magnitude under all the above operating conditions. Results acquired in Fig. 7(d) with a different initial voltage across the capacitor C b implies the inherent-balancing ability of the capacitors.
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2022 To verify the blocking voltage of the switches, voltage stress across the switches is presented in Fig. 7(e). For the 25-level operation, the switches S 1a , S 2a blocks the voltage 3V dc /4, switches S 1 , …, S 4 blocks the voltage V dc /4, switch S c blocks the voltage 5V dc /4, switches S 1b , …, S 4b blocks the voltage 3V dc /2, and switches S 5b , S 6b blocks the voltage V dc /8. Therefore, the TSV of the 25-level DSC MLI is 10V dc , which is in accordance with the expression (6).

V. EXPERIMENTAL VERIFICATION
In order to verify the feasibility of the proposed 25-level DSC MLI, an experimental test circuit comprising IGBT switches (12N60A4D:600 V) and discrete diodes (MUR860:600 V) is devised in the laboratory. The value of the three capacitors C 1 , C 2 and C b are chosen as C 1 , C 2 = 4700 μF (R int = 31 mΩ), C b = 3300 μF (R int = 56 mΩ), considering the voltage ripple of 5-7 %. The input supply voltages are set to 60 V (V dc1 ) and 240 V (V dc2 ) using programmable dc supplies. A DSP controller is utilized for the real-time pulse generation. Pulses are generated using MATLAB/Simulink-DSP interfacing. The Simulink model of the 25-level MLI is created in CC studio and downloaded to the DSP. The pulses from the controller are amplified using the TLP250 driver circuit, which also provides the required isolation between the control and power circuit. All the output waveforms are acquired with the help of a ScopeCoder (DL850E) and the power quality analysis is carried out using the analyzer (WT1800). The experimental tests are conducted using both a fundamental frequency switching scheme [10], [11] and high-frequency modulation scheme [26], [29], [31]. Fig. 8(a)-(c) depicts the results under the fundamental frequency switching scheme. The results are shown in Fig.  8(a) and (b) with R-load and sudden change in load from R to RL, respectively for a 50 Hz output frequency. The desired 25-level output, self-balancing of capacitors, change in ripple and change in load current pattern due to sudden variation in loading can be inferred from the results. As highlighted earlier, SC MLIs are widely used in highfrequency power distribution systems due to its advantages such as reduction in capacitor voltage ripple, low inrush current and high-quality output voltage. To verify the feasibility of the proposed MLI in high-frequency systems, waveforms are acquired in Fig. 8(c) with 500 Hz output frequency.
The test results are acquired under the high-frequency (switching frequency of 5 kHz) modulation scheme in  Furthermore, power losses are evaluated under 60 Ω-50 mH loading and fundamental switching scheme. Fig. 9(a) depicts the ohmic loss and switching loss on the switches (P oh-sw , P s-sw ) and anti-parallel diodes (P oh-dd , P s-dd ). The total power loss excluding the ripple power loss is about 18.03 W for ≈1 kW output power. The power quality analyzer results under 60 Ω-50 mH loading and 60 Ω-250 mH loading are shown in Fig. 9(b). The active power (P) CH1:200 V/div CH2: 5 A/div CH3: 100 V/di v CH4:100 V/div CH5:50 V/div CH1:200 V/di v CH2: 5 A/div CH3: 100 V/div CH4:100 V/div CH5:50 V/div CH1:200 V/div CH2: 5 A/div CH3: 100 V/div CH4:100 V/div CH5:50 V/di v decreases from ≈1 kW to 400 W and the reactive power (Q) increases with the change in PF (λ). The frequency of the output voltage is maintained at 50 Hz. The measured efficiency (η) of the proposed MLI, voltage THD and current THD are also depicted in the result. However, it is noteworthy that the efficiency may vary with the loading and device/power rating of the MLI.
(a) (b) Fig. 9. (a) Losses on the switches, (b) Performance parameters obtained using the WT1800 analyzer under different loading (high PF and low PF)

VI. CONCLUSION
A novel DSC MLI with extending ability using a reduced number of switches and two dc sources has been introduced in this work. For the 25-level operation, minimum number of switches with two diodes, and three capacitors are employed. Capacitors are arranged in such a way that, the source count is reduced as well as the use of external balancing control is avoided. The design and voltage balancing ability of the capacitors has been established. The capacitors C 1 and C 2 are self-charged using series-parallel charge balancing principle and assist the voltage magnitude boosting. On the other hand, the capacitor C b is self-balanced using the level doubling principle that assists voltage level enhancement.