Virtual Subspace-based DTC Strategy For Torque Ripple Minimization in Six-phase Induction Motors

Classical switching-table-based direct torque control (ST-DTC) of six-phase induction machine (6PIM) drives is seriously penalized by current harmonics as well as torque ripples because of uncontrolled voltage vectors in the low-impedance non-energy subspace and hysteresis torque regulator, respectively. Hence, a virtual subspace-based DTC strategy is proposed to alleviate the impact of low-order current harmonics and torque ripples. The proposed virtual subspace includes 48 virtual voltage vectors (VVs) in the α - β subspace with average volt-seconds of zero in the z1 - z2 subspace, which offers full extent of freedom degrees for 6PIM fed by a two-level voltage source inverter (VSI). The increased number of VVs allows the possibility to design up to nine-level hysteresis torque regulator to minimize the torque ripples. Nevertheless, in this paper, it is found that torque ripple, current harmonics, average switching frequency, and computational burden come to a compromise with a seven-level hysteresis torque regulator. The impact of these VVs on the performance of ST-DTC is experimentally studied and some details of hardware implementation are presented. The performance of the proposed scheme is verified by simulations as well as laboratory experiments, where a complete comparison with recent schemes is made to reveal the superiority of the proposed scheme.


A. MOTIVATION
S WITCHING-table-based direct torque control (ST-DTC) strategy has much to offer in terms of fast dynamic, simplicity, and low parameter dependency [1], [2]. As frequently mentioned in the literature, the classical ST-DTC suffers from high torque ripple and variable switching frequency due to hysteresis regulators [3]. Modulation-based DTC has been proposed to tackle these problems [4], [5], however, it may overshadow fast dynamic, simplicity, and robustness of ST-DTC [6].
Safety-critical applications, such as fuel pumps, electric vehicle and ship propulsion systems, are the main beneficiary of the multi-phase drives (with more than three phases) due to their inherent fault-tolerant capability without any extra equipment [7]- [9]. Beside aforementioned problems in relation to ST-DTC, simple extension of the classical ST-DTC to multi-phase drives causes an additional problem in term of current harmonics, when only large voltage vectors are selected during the whole sampling period [10]. The reason lies in the fact that the secondary components, i.e., z 1 − z 2 components, remain uncontrolled when only large voltage vectors are applied. These cases highlight the need for an efficient ST-DTC for multi-phase drives. Among possible choices of multi-phase drives, an asymmetrical six-phase induction machine (6PIM) with two three-phase winding sets, which are spatially shifted by π/6, is a promising structure because the three-phase technologies can be conveniently generalized to six-phase ones [11]. Such a structure is depicted in Fig. 1.

B. LITERATURE REVIEW
There is a fruitful research activity to overcome the problems of classical ST-DTC for multi-phase drives [12]- [17]. Appli-  [12] and [13], respectively. However, it should be acknowledged that the study of DTC strategy during fault occurrence has remained poor, mainly due to the lack of internal current control loops. The concept of duty ratio control to reduce unwanted current harmonics has been frequently addressed [14]- [18], where the large voltage vectors in classical DTC are replaced by the virtual voltage vectors (VVs), which are defined as a combination of large, medium, and small voltage vectors. The duty ratio is calculated to remove the average volt-sec in the z 1 − z 2 subspace. The duty ratio control-based ST-DTC has been established in response to current harmonics due to nonzero voltage vectors in the secondary subspace, but not the current harmonics due to dead time, winding asymmetry, and back electromotive force distortion. To overcome later cases, a DTC strategy using proportional-integral-resonant (PIR) current controller has been proposed in [17]. Nevertheless, such a DTC schemes cannot reduce the torque ripple significantly.
Increasing the action points in the hysteresis torque regulator has been found suitable for torque ripple reduction in the multi-phase drives [19]- [22]. Fortunately, further voltage vectors in the multi-phase drives in comparison with threephase ones offer the possibility to adopt five-phase hysteresis torque regulator, where the outer band is responsible for the good dynamic performance while the inner band is responsible for the torque ripple reduction [20]. Such a scheme with symmetrical and asymmetrical pulse patterns has been proposed in [20] and [21], respectively. Switching frequency and complexity are the main differences between symmetrical and asymmetrical pulse patterns. Furthermore, a sevenlevel hysteresis torque regulator has been proposed in [22] for 5PIM fed by the three-level voltage source inverter (VSI), where some improved results can be found against fivelevel hysteresis regulator. Modifying the switching table [23], [24], improving the three-level hysteresis torque regulator [15], controlling the duty ratio of the active voltage vectors by inserting zero voltage vectors [25], and combining the ST-DTC and space vector modulation (SVM)-based DTC  55  34  62  20  23  2  58  16  10  31  59  17  8  29 1 43 40  61   5   47   32   53   56   48   49   51   35  3   7   15   14   12   28  60   57   18   41   54   25  36  26  45   9  38 27 37   22   16   52   24  44   30   13   6   11  39  19   33   50   58   61  40  62  20  29  8  46  4   10  31  47  5  2  23 1  schemes [26] are some other attempts to tackle the problem of high torque ripple in the classical ST-DTC.

C. PAPER CONTRIBUTION
In order to improve the performance of the classical ST-DTC in terms of torque ripples and low-order current harmonics, and at the same time, to retain the fast dynamic and simplicity of ST-DTC, this paper proposes a virtual subspace-based ST-DTC using a seven-level hysteresis torque regulator for a two-level dual three-phase VSI-fed 6PIM. The proposed virtual subspace contains 48 VVs with partially reduced voltage levels in the α − β subspace as compared to actual ones and zero averages in the z 1 − z 2 subspace, hence, they can effectively reduce the harmonics mapped into th z 1 − z 2 subspace. Since that a two-level dual three-phase VSI has totally 48 unique active voltage vectors, it can be said that the ST-DTC can fully access the additional freedom degrees, i.e., different voltage levels, through defining this virtual subspace. Therefore, torque ripples can be significantly reduced by a multilevel hysteresis torque regulator. To highlight the contribution of the paper, the proposed scheme is experimentally compared with the conventional ST-DTC as well as the prior arts presented in [15], [20], [21] from different viewpoints.

D. PAPER STRUCTURE
The rest of the paper is organized as follows. Section II discusses the feasible VVs in a two-level dual three-phase VSI with their properties. The proposed ST-DTC is presented in section III, where the virtual subspace is firstly defined. Then, the impact of VVs on the dynamic and steady-state (SS) performances of ST-DTC is studied experimentally. Accordingly, a seven-level hysteresis torque regulator-based ST-DTC is investigated. Experimental results and quantitative comparisons are given in section IV. Finally, section V summarizes the findings and concludes the paper.

II. VIRTUAL VOLTAGE VECTORS
There are totally 2 6 = 64 switching states in two-level dual three-phase VSIs. The switching states constitute 64 nonunique voltage vectors in the α − β, z 1 − z 2 , and o 1 − o 2 sub- In the case of 6PIM with two isolated stator sets, the voltage vectors are mapped into the origin of o 1 − o 2 subspace. For this case, the voltage vectors in the α − β and z 1 − z 2 subspaces are shown in Fig. 2. The α − β components contribute towards electromechanical energy conversion, while the z 1 − z 2 components only cause losses. Among these vectors, there are four zero voltage vectors and 48 unique active voltage vectors, which are spatially distributed in the α − β or z 1 − z 2 subspaces. Four voltage levels are formed by these active voltage vectors, which are shown as four nonzero dodecagons in Fig. 2. Each decimal number represents a switching state using a binary sequence as where S is the state of upper switches. The voltage vectors in the α − β subspace are categorized according to Table  1. The amplitude of the large and small voltage vectors in the α − β subspace is reversed in the z 1 − z 2 subspace, while the amplitude of the medium large and the medium small vectors remains constant in both subspaces. Defining the voltage vectors as V hk , where h ∈ {L, M L, M S, S} and k is the voltage number corresponding to the α − β subspace, if k increases by +1 in the α − β subspace, it will increase by +5 or −7 in the z 1 − z 2 subspace, because the z 1 − z 2 subspace contains fifth and seventh harmonics rotating with +5ω s and −7ω s frequencies [27], where ω s is the fundamental frequency. For control techniques without modulation strategy such as ST-DTC and predictive torque control (PTC), where the voltage vectors are selected according to the switching table and cost function minimization, respectively, applying the actual voltage vectors during whole sampling period leads to the large current harmonics due to the non-zero voltage vectors in the z 1 − z 2 subspace. Replacing the actual voltage vectors by VVs is a promising solution to manage this problem,  Fig. 3 where VVs are constructed using actual voltage vectors with appropriate action times to make an average volt-seconds of zero in the z 1 − z 2 subspace. The classification of VVs for dual three-phase VSI in the α − β subspace is tabulated in Table 2. Furthermore, the normalized VVs in the α−β and z 1 −z 2 subspaces are shown in Fig. 3. The voltage space vectors are given by and a = e jπ/6 . The normalized amplitude of the voltage vectors is calculated as and the DC-link utilization rate (η) is defined as The simplest VVs are synthesized using two voltage vectors (2D VVs), where the constructed VVs must include medium large voltage level, due to its opposite direction in z 1 − z 2 subspace against large and small voltage vectors. There are two possible groups of 2D VVs, i.e., G 1 and G 2 , which offer two voltage levels in the α−β subspace as shown in Fig.3 (b) and (c). The action times of the actual voltage vectors, used in VVs, are calculated according to a simple vector sum in the z 1 − z 2 subspace to provide a zero resultant vector during each sampling period T s . For instance, the VOLUME 4, 2016 action times of T 48 and T 57 (from G 1 group) are calculated as where superscript z denotes that the amplitude of voltage vector is in the z 1 − z 2 subspace. Similarly, the action times of T 57 and T 54 (from G 2 group) are T 57 = cos(π/12) cos(π/4)+cos(π/12) T s T 54 = cos(π/4) cos(π/4)+cos(π/12) T s As shown in Figs. 3 (b) and (c), the constructed VVs of G 4 group, made by three consecutive large voltage vectors, are the same as G 1 group. Moreover, VVs of G 3 group, made by two consecutive medium small voltage vectors and one medium large voltage vector between them, are the same as G 2 group. The differences appear in the hardware implementation, where the switching sequences are different. In order to facilitate the hardware implementation through middle-high switching sequences for upper switches of VSI, a combination of G 1 -G 4 and G 2 -G 3 switching sequences has been proposed [15], [20].

III. PROPOSED ST-DTC SCHEME A. DEFINITION OF VIRTUAL SUBSPACE
As shown in Fig. 3, three voltage vectors-based VVs (3D VVs) permit utilization of the additional freedom degrees in the dual three-phase VSI through defining more voltage levels in the α − β subspace. This offers some merits such as further reduction of torque ripple in comparison with classical ST-DTC as well as the proposed ST-DTC in [20]  and [21]. Applying three consecutive actual voltage vectors, with the same voltage levels to constitute 3D VVs as G 4 −G 7 groups, can also provide a generalized ST-DTC scheme, because the action times of the constructed 3D VVs are uniform regardless of the voltage level, thus it is straightforward in the hardware implementation. Fig. 4 shows an example of VVs construction for G 5 group, which can be extended to G 4 , G 6 , and G 7 , as well. According to this figure, the action times of G 4 − G 7 groups-based VVs can be calculated as solving (8) yields where h ∈ {L, M L, M S, S}, and k is the sector (voltage) number.
Examining the 3D VVs made by three consecutive voltage vectors in each sector, as depicted in Figs. 3 (b), (d), (e) and (f), which are related to G 4 , G 5 , G 6 , and G 7 groups, respectively, it can be seen that the voltage levels of these groups are slightly lower than their corresponding actual voltage vectors in the α − β subspace. In this regard, according to Tables 1 and 2, the amplitude of the mentioned 3D VVs are 0.60V dc , 0.44V dc , 0.31V dc , and 0.16V dc for large, medium large, medium small, and small voltage vectors, respectively, while these numbers are 0.64V dc , 0.47V dc , 0.33V dc , and 0.17V dc for the actual ones. Therefore, it is possible to replace 48 actual voltage vectors with these 48 3D-VVs to constitute a virtual subspace, where the amplitude of the 3D VVs is slightly lower than the actual ones, while the resultant voltage vectors are zero in the secondary subspace. However, there are still some considerations in the formation of this virtual subspace from hardware implementation, switching frequency, and ST-DTC performance viewpoints. According to Figs. 3 (c) and (e), the VVs of G 6 group are shifted by π/12 compared to G 2 group, while their voltage level difference is about 0.04 P.U. The shifted VVs of G 6 group, which are exactly aligned with the actual medium small voltage vectors with slightly lower voltage level, may differently change the torque and flux in ST-DTC in comparison with remaining groups as well as they increase the average switching frequency. Hence, G 6 group is replaced with G 2 group. On the other hand, the G 1 and G 4 groups are theoretically the same in terms of torque and flux regulations as well as average switching frequency. However, separate implementation of G 4 group requires more computational burdens. Hence, the G 4 group is replaced by G 1 group in the proposed virtual subspace.  The proposed virtual subspace can be realized in the hardware implementation using totally 10 switching sequences, which are shown in Fig. 6. For the medium large and small levels-based VVs, since that VVs are made by three voltage vectors, there are totally 2 3 = 8 possible switching sequences (i.e., Case#0-Case#6, and Case#9). Theoretically, these three voltage vectors can be arranged in 3! = 6 sequences. However, four sequences overlap with the remaining ones, hence, there are two different unique sequences. In this paper, the sequence of V h(k−1) , V hk , and V h(k+1) is adopted for 3D VVs because of its symmetrical pattern. In Fig. 6, Case#7 and Case#8 are specific for medium small virtual voltage level, while the other cases are used for large, medium large, and small voltage levels, irrespective of Case#0 and Case#9. Accordingly, examples of switching sequences for the constructed VVs in the proposed virtual subspace as well as the switching states of the actual voltage vectors are presented in Table 3. There are totally 48 VVs, but only 12 of which are shown in Table 3. Each VVs is described by a decimal sequence as C = [C u1 C u2 C w1 C w2 C v1 C v2 ], where C ∈ {0, ..., 9} is the switching sequence of upper VSI's switches, which was already drawn in Fig. 6. These switching sequences can be implemented using pulse-width modulation (PWM) module in the most micro-controller platforms. The PWM settings for their implementation on TMS320F28335 digital signal controller are tabulated in the Appendix A.  Volt.

B. EXPERIMENTAL ASSESSMENT OF THE PROPOSED VIRTUAL SUBSPACE
This section experimentally assesses the impact of VVs in the proposed virtual subspace on the SS and dynamic performances of ST-DTC for 6PIM. In this regard, different ST-DTC schemes are separately implemented using actual large voltage vectors as well as VVs belonging to the same voltage level in the virtual subspace (see Fig. 5 and Table 3 .., 12} is selected according to the outputs of three-level hysteresis torque regulator and twolevel hysteresis flux regulator using a switching table, which is drawn in Table 4. The experimental study for SS and dynamic performances of ST-DTC of 6PIM for different VVs as well as actual voltage vectors is summarized in Table 5. The adopted hysteresis torque regulators, using appropriate torque indices according to the Table 4, are depicted in the third column of Table 5, while the average switching frequency f sw and voltage levels can be found in the second column of this table. The SS and dynamic results are shown in fourth and fifth columns, respectively. For the SS experiments, speed and flux commands are 100 rpm (in the reverse rotation) and 0.6 Wb, respectively, under about 2 Nm load torque. For the dynamic experiments, a speed step increase from 10 rpm to 400 rpm is imposed under same loading level. All experiments are carried out under same DC link voltage, torque, and flux hysteresis bands, which are set to 3% and 1% of their rated values, respectively.
The SS results clearly shows that the torque ripple is continuously decreased, when the voltage level is decreased. In this regard, small VVs offer the lowest torque ripple, while large VVs impose the highest torque ripple on the drive system. The torque ripple of other VVs is placed in between V V L and V V S . On the other hand, as expected, the large VVs guarantee stability and fast dynamic performance during sudden changes of speed as well as load torque, while the small VVs poorly behave under dynamic experiments. Similarly, the fast dynamic property of other groups takes place in between V V L and V V S . The average f sw is obtained by counting total number of jumps of switches and calculating every 0.1 s. Obviously, the average f sw is increased, when the number of applied voltage vectors during each sampling period are increased, hence, V V S and V V M L impose higher average f sw . As shown in Table 5, despite the lowest torque ripple, small VVs have the highest average f sw . The reason can be extracted from Table 3 and Fig. 6, where the total number of switching cases 2 or 5 is four for each small VVs. Cases #2 and #5 increase the average f sw more in comparison to other cases. For the same reason, the average f sw of ST-DTC scheme using V V M L is higher than V V L and V V M S . Not surprisingly, the conventional ST-DTC with V L offers the lowest average f sw . As discussed, lower voltage level results in lower torque ripples with poor dynamic response, even instability and SS errors. Therefore, a combination of different VVs through a multilevel hysteresis torque regulator is introduced as a promising solution, where the inner bands are responsible for torque ripple reduction and outer bands are responsible for fast and stable dynamic performance. The proposed virtual subspace offers the possibility to design up to nine-level hysteresis torque regulator, due to four levels of VVs arranged in Table 5 and zero voltage vectors, to utilize full extent of freedom degrees of dual three-phase VSI-fed 6PIM and to minimize the torque ripples. However, as it will be discussed in the next section, a seven-level hysteresis torque regulatorbased ST-DTC technique is prepared to compromise on the benefits of freedom degrees.

C. ST-DTC BASED ON VIRTUAL SUBSPACE
The schematic diagram of the proposed ST-DTC, ST-DTC of [20] and [21], and conventional ST-DTC is shown in Fig.  7. A two-level hysteresis flux regulator is employed in all schemes. The classical estimation of flux is provided by where ψ s , v s , i s , and R s are the stator flux, voltage, current, and resistance, respectively. The electromagnetic torque is expressed by where P is the number of pole pairs and ⊗ represents cross product. Due to problems of pure integration in the classical voltage model (10), a modified voltage model is used as [28] where ζ is a constant gain. The stator voltages in the stationary reference frame can be constructed using the switching states and measured DC-link voltage with a nonlinear inverter model as [29] where T d is dead time and m ∈ {u 1 , u 2 , w 1 , w 2 , v 1 , v 2 }. The experimental assessment presented in III-B, regarding the impact of different VVs on the performance of ST-DTC technique, has been mathematically investigated in [20], [21]. Briefly, the time derivative of electromagnetic torque can be VOLUME 4, 2016  HTe = {-4,-2, 0, 2, 4} HTe = {-4, -3,-2, 0, 2, 3

S = {0,1}
Switching Table  D = {0, 0.27, 0.42,  0.58, 0.73, 1} Switching Table   C  written as [30] dT where ψ r , L s , and ω r are the rotor flux, the stator inductance, and the rotor speed, respectively, and represents dot product. It can be seen that the zero voltage vectors only decrease the torque because the third term in (14) becomes zero, while the active voltage vectors may increase or decrease the torque according to the selected voltage vectors. The effect of voltage level on the torque variation can be surveyed by the third term of (14), where larger amplitude of voltage vectors leads to a larger variation of torque because of steeper slopes of torque characteristic. It should be noted that the torque behavior is also speed-dependent due to second term in (14), whereby the absolute torque variation during increasing and decreasing is different, especially at high speeds [20]. Although the small VVs offer the lowest torque ripple, however, there are some problems associated with them. Firstly, the average switching frequency of small VVs is higher than the other VVs, which the reason was described previously. Secondly, consider the 6PIM model in the where L ls is the stator leakage inductance. Since that the small voltage vectors appear as large voltage vectors in the z 1 − z 2 subspace, any asymmetries may exacerbate i z1z2 currents, especially when the L ls is too small. Hence, in this paper, a seven-level hysteresis torque regulator-based ST-DTC is introduced using V V L , V V M L , and V V M S . The adopted switching table was shown in Table 4, where ♦ symbol indicates the VVs used in the proposed ST-DTC scheme.
Using the proposed ST-DTC scheme, torque ripple, current harmonics, average switching frequency, and computational burdens reach an agreement.

A. PRELIMINARIES
Besides some simulation results which will be presented in the next section, the performance of the proposed ST-DTC based on virtual subspace is experimentally investigated, and a comparison study is carried out using the following schemes: • Conventional ST-DTC using actual large voltage vectors with a three-level hysteresis torque regulator (hereinafter labeled C3LDTC). • A modified ST-DTC using large VVs with a three-level hysteresis torque regulator, which has been proposed in [15] (hereinafter labeled 3LDTC). • A modified ST-DTC using large and medium small VVs with a five-level hysteresis torque regulator, which has been proposed in [20], [21] (hereinafter labeled 5LDTC). • Proposed ST-DTC using large, medium large, and medium small VVs with a seven-level hysteresis torque regulator (hereinafter labeled P7LDTC). Hysteresis torque regulators for the mentioned schemes are shown in Fig. 8. Although there are some asymmetric hysteresis torque regulators [31] to remove SS torque error, such a comparison is fair because asymmetric changing the hysteresis outputs can be applied for all hysteresis regulators shown in Fig. 8.

B. SIMULATION RESULTS
An extensive simulation study was carried out to investigate the performance of the proposed scheme. The simulations are run using Matlab/Simulink software with 10kHz sampling frequency, where some selected results are shown in Figs. 9 (a) and (b) for 5LDTC and P7LDTC, respectively. In these tests, the speed command is set to 70 % rated speed under rated load torque. From top to bottom, the electromagnetic torque, the stator flux, and the stator phase current traces are shown in each row. The results of other schemes, i.e., C3LDTC and 3LDTC, are omitted in this figure, while they will be also included for experimental tests. It is obvious that P7LDTC effectively reduces the average SS torque ripples in comparison with 5LDTC. For a much clearer comparison, the average torque ripple index (index1) is defined as follows:  where T ei and T avg are the instantaneous and the average torque values. Moreover, index2 is defined as a product of index1 and average switching frequency It is worth mentioning here that index1 evaluates the average torque ripple value, while index2 considers this value, together with the average switching frequency. Obviously, lower values of both indices show better performance of the drive system. The values of index1 and index2 in different speeds and load torques for the P7LDTC and 5LDTC are shown in Fig. 10. As can be seen from this figure, the proposed scheme offers lower values of average torque ripples for different drive operating points. On the other hand, although P7LDTC inevitably increases the average switching frequency, index2 can justify the merits of P7LDTC over 5LDTC as a unified index.

C. EXPERIMENTAL TEST BENCH
A photograph of the experimental test bench is shown in Fig. 11. An eZdsp F28335 board based on TMS320F28335 digital signal controller has been used for implementing the control algorithms and generating the PWM signals, which has been programmed through code composer studio (CCS) development environment. The main control algorithm has been executed through a PWM interrupt service routine (ISR) with 10 kHz frequency, and the speed controller and calculation have been executed using a timer interrupt with 100 Hz frequency. The 6PIM is fed from dual three-phase Semikron SKiiP VSI connected to a 250-V dc power supply. An incremental shaft encoder with 2048 pulses/revolution has been used to measure the rotor pulse train. A 4-hp and 8-pole three-phase wounded rotor induction motor with 48slot stator has been rewound to provide a 4-pole asymmetrical 6PIM.

D. STEADY-STATE PERFORMANCE
Figs. 12 (a) and (b) present the SS performance results of C3LDTC, 3LDTC, 5LDTC, and P7LDTC, under no load and 50% rated load torque, respectively. The speed and stator flux commands for both cases are 100 rpm (in reverse rotation) and 0.6 Wb, respectively. From top to bottom, the electromagnetic torque, z 1 -current, and phase currents are shown in each oscillogram. High harmonic content of the stator currents due to uncontrolled z 1 − z 2 subspace is obvious for C3LDTC. 3LDTC improves the performance of C3LDTC from current harmonic viewpoints, but not torque ripples, becasue there is no remarkable difference in voltage levels of V L and V V L used in C3LDTC and 3LDTC, respectively. As can be seen in Fig. 12, 5LDTC reduces the torque ripples in comparison to C3LDTC and 3LDTC, and P7LDTC minimizes the torque ripples to the 6PIM drive system. According to the SS test results, the proposed ST-DTC technique offers 5-10 % (of rated torque) decrease in torque ripple in comparison with 5LDTC. Amplitude difference of phase currents, which is more visible under no load condition, is due to inherent asymmetry in the 6PIM windings and/or converters, which causes current flow in z 1 − z 2 subspace with fundamental frequency.

E. DYNAMIC PERFORMANCE
The oscillograms of Figs. 13 (a), (b), and (c) illustrate the dynamic performance of 3LDTC, 5LDTC, and P7LDTC for loading/unloading, speed reversal at no load, speed reversal under loading experiments, respectively. The electromagnetic torque, phase current, rotor speed, and stator flux modulus are shown in each oscillogram. The stator flux command is 0.6 Wb for all tests. In Fig. 13 (a), the speed command is 200 rpm (in direct rotation), and load torque suddenly increases to the rated value and deceases to zero after a short time passed. In Fig. 13 (b), the speed command is reversed from +200 rpm to -200 as a step function under no load condition. The same experiment is repeated but for 50% rated load torque, which the results are shown in Fig. 13 (c). It can be seen from the results that the P7LDTC has the minimum torque ripple in comparison with 3LDTC and 5LDTC, which was already found from SS tests. Moreover, fast dynamic property of 3LDTC is preserved in the proposed ST-DTC technique for different dynamic test scenarios.

F. SWITCHING FREQUENCY
The average f sw of C3LDTC, 3LDTC, 5LDTC in [20], 5LDTC in [21], and P7LDTC for SS experiments, which their results were shown in Fig. 12, is reported in Table  6. C3LDTC possesses the minimum average f sw because Avg. fsw (kHz) Avg. fsw (kHz) in Fig. 12 (a) in Fig. 12 [20] has the maximum average f sw , because in that work, switching sequences have been rearranged to obtain standard middle-high pulse patterns to make it easy for implementation, but with increased average f sw . The average f sw of 3LDTC and 5LDTC presented in [21] takes place within the medium range, i.e., lower than [20] and higher than C3LDTC. The average f sw of P7LDTC is higher than 3LDTC and 5LDTC of [21], because of applying medium large VVs based on three voltage vectors in each sampling period, but it is lower than 5LDTC of [20].

G. EXECUTION TIME
In order to investigate the software complexity of the proposed ST-DTC, its average computation burden, for the main control loop, is monitored and compared with the C3LDTC (or 3LDTC), 5LDTC in [20], and 5LDTC in [21]. It should be noted that, since the execution time is hardware dependent and programming dependent, same programming style makes such a comparison fair. The execution time, number of CPU cycles, and the percentage of CPU utilization are tabulated in Table 7. The total number of cycles in every ISR call, considering 10 kHz frequency @150 MHz CPU operating speed is 15000 cycles. As expected, the execution time of P7LDTC is the highest due to enlarged switching table as well as PWM settings, shown in Appendix A. However, the scale of differences between CPU cycles for the compared techniques may marginally overshadow modern and highspeed micro controllers.

V. CONCLUSION
This paper is simultaneously aimed at minimizing torque ripple and reducing the harmonic content of stator currents in classical ST-DTC of 6PIM. For this, a virtual subspace with 48 virtual voltage vectors was introduced, which provides full extent of non-zero VVs in a two-level dual three-phase VSI. Some details of hardware implementation of these VVs were presented. The effect of different VVs on the SS and dynamic performances of ST-DTC technique for 6PIM was studied. A seven-level hysteresis torque regulator-based ST-DTC based on virtual subspace was proposed. The proposed ST-DTC has the the merits of minimized torque ripples, reduced current harmonics, and fast dynamic property. The performance of the proposed scheme was experimentally compared with prior arts from different viewpoints. The results confirmed that the torque ripple was effectively reduced in comparison with three-level and five-level hysteresis torque regulators, while fast dynamic property of conventional ST-DTC was preserved. .