Voltage Balancing Strategy for V-Clamp Multilevel Converter Under High Modulation Index and High Power Factor Condition

Featured with the simple structure, V-clamp multilevel converter (VMC) shows good prospect in the high-voltage and high-power applications. But VMC is endangered by the deviation of dc-link capacitors voltage, especially under the high modulation index (MI) and high power factor (PF) condition. Thus, a voltage balancing strategy for three-phase seven-level VMC is proposed in this paper. This strategy re-designs the carriers and reference to achieve capacitors voltage balancing with reduced switching actions. Besides, an active compensation control for capacitors voltage is presented to improve the dynamic performance. Compared with the conventional virtual space vector modulation, the proposed strategy significantly reduces the switching loss while provides a better output voltage under the high MI and high PF condition. The simulation model and experimental prototype of VMC with 7.2kW/220V are constructed to verify the validity of the proposed strategy.


I. INTRODUCTION
Due to the small electromagnetic interference and lower switching stress, multilevel converters have been widely used in high-power applications [1], [2]. Conventional topologies for multilevel converters include neutral point clamped (NPC), flying capacitor (FC) and cascaded H-bridge (CHB). Among them, NPC and FC higher than three levels suffer from the mass clamping devices, hence they are hard to be applied to higher voltage (over 6kV) applications. Although the CHB offers a solution in this case, it is limited by the requirement of multiple isolated dc sources [3]- [5].
The V-clamp Multilevel Converter (VMC) is a suitable topology for the high-voltage applications [6]. Compared with the conventional topologies, VMC shows advantages as follows: 1) The clamping devices in VMC is reduced than that in NPC and FC counterparts.
The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao .
2) VMC needs single dc source and contains no flying capacitors, which leads to simple structure and small volume.
3) The series-connected switches in VMC only sustain one level voltage during commutation process. Hence, the seriesconnected switches can be controlled as simple as one switch and the dynamic voltage unbalancing issue is avoided.
VMC attracts much attention in recent years [7]- [9]. The topology extension form of VMC is deduced in [7]. And a direct torque control for VMC is studied in [8]. In [9], a back-to-back VMC system is applied in 6.6kV motor drive application, which achieves transformer-less operation and good harmonic characteristics.
In spite of its merits, VMC with passive front-end has the same issue of dc-link capacitors voltage unbalancing as NPC. Since VMC higher than three levels contains multi intermediate nodes, the dc-link capacitors voltage are prone to deviate from the rated valve. Which results in the deterioration of the output performance and failure of system [10]. It has been revealed that the traditional algorithms based on nearest-three space vector modulation (SVM) failed to maintain capacitors voltage balancing under the high modulation index (MI) and high power factor (PF) condition [11], [12]. However, converters are generally operated at high MI to improve the utilization of dc-link voltage. Moreover, the high PF operating capability is required in many applications, such as mining, traction and power transmission [13]. Therefore, the study on voltage balancing strategy for VMC under high MI and high PF condition is necessary.
Various investigations have been done to solve the abovementioned issue [14]- [20]. Additional circuit is applied to keep capacitors voltage equal in [14], [15]. But this method results in extra investment and complex structure. In [16], a voltage balancing control based on divided SVM is proposed for five-level converter. The five-level vector space is divided into six two-level vector spaces, and redundant vectors are selected based on the capacitors voltage. However, transition levels are generally injected to avoid multilevel voltage jumping in each switching cycle, which results in extra switching actions [17]. The virtual SVM (VSVM) only uses the self-balancing virtual vectors, thus the natural capacitors voltage balancing within one switching cycle is achieved under ideal and steady states [18]. In the practical system, however, VSVM still need a closed-loop control to eliminate the effects of non-ideal factors (parameter differences, deadzone effects, etc.) [19]. Besides, VSVM requires complex computation and unneglectable increase of switching loss in the converters with higher levels. In [20], the algorithm of VSVM is simplified, but the drawback of high switching loss still remains. This paper proposed a voltage balancing strategy for the VMC under high MI and high FP condition. In the proposed strategy, carrier waves are re-designed firstly, in this way the dc-link capacitors voltage balancing for full operating range is achieved naturally. Furthermore, by injecting a proper zero-sequence component to reference waves, one phase is clamped to the highest or lowest level in certain sectors, then the switching loss is significantly reduced. Besides, considering the error caused by non-ideal factors, this paper also provides an active compensation control to improve the dynamic performance of the proposed strategy. Finally, the simulation and experimental results verify the validity of the proposed strategy.

II. CAPACITORS VOLTAGE BALANCING CRITERION OF VMC
A. CONFIGURATION OF 3P7L-VMC As illustrated in Fig. 1, three-phase seven-level (3P7L) VMC shares six common dc-link capacitors. The negative dc bus is taken as the reference zero level, and the rated voltage of each capacitor E is taken as the one level voltage. Each phase leg consists of six clamping branches and one power arm, then the output terminal can be clamped to the seven levels (0, E, 2E, 3E, 4E, 5E and 6E) of dc-link. The dc bus current I dc = [i dcP , i dcN ] T , capacitors current   The switching states of 3P7L-VMC is shown in Table 1, where ''0'' and ''1'' represent the off-state and on-state respectively. Since the series-connected switches in VMC are controlled simultaneously, the switching states of S 4a , S 4b and S 4c are represented by S 4 here. So does the S 5 , S 10 and S 11 . It can be seen that, there is no redundant current path contained capacitors in VMC, which means the current flows through the certain dc-link node when the output level is determined. This feature also exists in NPC. It indicates that the capacitors voltage unbalancing mechanism of VMC and NPC are the same.

B. CPACITORS VOLTAGE BALANCING CERTERION
The criterion for the capacitors voltage balancing in VMC is discussed in this section. For simplified analysis, the following assumptions are set: 1) the capacitance of each capacitor is C. 2) the initial voltage of each capacitor is E.
Generally, the voltage variation of capacitor v C is affected by its current i C . In order to ensure the voltage balancing, the integration value of i C should be zero: where θ is the phase angle. VOLUME 9, 2021 Consequently, the integration values of all capacitors currents I C in the 3P7L-VMC need to be zero: According to kirchhoff's current law, i dcP , i dcN , i 0 and i 6 will not cause the unbalancing of capacitors voltage. Therefore, regardless of these current components, the relationship of I C and I I can be obtained as (3).
Further deduction shows that the rank of matrix A equals to the unknown number, which is 5. Therefore, (3) has the unique solution. By substituting (2) to (3): It can be seen that, the capacitors voltage balancing is guaranteed when (4) is satisfied. Since the average value of I I in each switching cycle can be calculated directly by the duty ratio and output currents, equation (4) is taken as the criterion for capacitors voltage balancing in this paper. As shown in Fig. 2, the output level is decided by the comparison results between the carriers and reference voltage v ref .

III. PROPOSED VOLTAGE BALANCING STRAGEGY
In the digital control, the generation of v t1 and v t6 is the same as the conventional three-level PD-PWM. Besides, the general generation flow chart of v t2 to v t5 is illustrated in Fig. 3, where N clk is the basic clock counter. N clk increases 1 in each clock cycle (T clk ). N PRD is the count value of half T c , and N PRD = T c /2T clk . N tn is the count value of v tn , and N tn = N PRD (v tn + 1). According to the judgement result of carrier location, the step value of N tn per T clk is selected and the value of v tn can be obtained.
Based on the MCBM, the duty ratios of all intermediate levels in each carrier cycle are the same, which benefits the equal energy distribution among the dc-link capacitors. Another advantage of MCBM is the simplicity for digital implementation as (5).
where, d j represents the duty ratio of jE level, j = 0, 1, 2, 3, 4, 5, 6. Since the value of d 1 , d 2 , d 3 , d 4 and d 5 are equal, they are represented as d I here.

B. DISCONTINUOUS REFERENCE WAVES
As seen in Fig. 2, when the conventional sine references are applied, the MCBM needs 10 switching actions per phase in one T c . In this case, MCBM only reduces 2 switching actions than VSVM in 3P7L-VMC. The number of switching actions is still high, which leads to the high system switching loss and limitation for practical applications.  The MCBM releases the control freedom of zero-sequence voltage, which is different from VSVM. Therefore, this paper adopts the discontinuous references to reduce the switching loss.
As shown in Fig. 4. The final three-phase references v ref_a , v ref_b and v ref_c are obtained by injecting the zero-sequence component v Z to the original sine references v ref_a0 , v ref_b0 and v ref_c0 . In this way, one reference is clamped to −1 or 1 during each π/3, and the number of switching actions in clamped phase keeps 0.
Equations (6) where M is the modulation index.
v Z is calculated as

C. VOLTAGE BALANCING MECHANISM
With the above-mentioned MCBM and discontinuous reference waves, the capacitors voltage balancing can be achieved naturally in the ideal and steady system. The balancing mechanism is analyzed in the following text.
Firstly, set the three-phase output current as where I m is the amplitude of output currents, ϕ is the power factor angle.
Assuming the output current is unchanged during one T c . According to the area equivalence principle and (5), the equivalent value of each intermediate current i I is the same, which can be expressed as: where d I_x represents the duty ratio of intermediate level of In combination with (5)-(10), the integration value of i I in each phase within one fundamental period T f can be obtained. Taking phase a as example: Hence, the solution of (11) is obtained as Similarly, the same solutions can be obtained in other phases. The total average i I is zero within one fundamental period. From (4), it can be known that the criterion of capacitors voltage balancing is satisfied with the proposed strategy, and it is irrelevant to the MI and PF. When the balanced load are connected, based on the symmetry, the 3P7L-VMC system can achieve capacitors voltage balancing within one-third fundamental period for full operation range.
It is noteworthy that, as long as v Z meets the limitation of (12), the result of (13) can be obtained and the natural capacitors voltage balancing of system is achieved. VOLUME 9, 2021 Hence the applied reference waves are not directly associated with the MCBM. Other reference waves that meet the limitation of (12) are also available for system to achieve different control objections. In this paper, the v Z shown in (8) is selected to reduce the switching loss under the high PF condition.

IV. ACTIVE COMPENSATION CONTROL
In the practical system, the natural voltage balancing may be deteriorated by the non-ideal factors, such as the capacitance differences between dc-link capacitors, insertion of deadzone, and the switching delay and voltage drop [21]. Therefore, an active compensation control (ACC) for capacitors voltage balancing is provided here to improve the system dynamic characteristics.
Noted that, since the zero-sequence voltage has been determined in (8), the ACC needs to regular capacitors voltage without changing the phase output voltage. Fig. 5 shows an example of the ACC. When v C4 < v C5 , i C4 should be increased and i C5 should be decreased to eliminate the voltage difference. If the output current i o is positive, the duty ratio adjustment of each output level is shown in (14), Consequently, the adjustment of each capacitors current can be obtained from (3) and (14).
It can be seen that, the voltage difference between C 4 and C 5 is reduced with the ACC, while other capacitors voltage are not affected. Moreover, the removed area is equal to the added area in Fig. 5. Hence, the equivalent output voltage keeps unchanged with ACC.
Considering the voltage deviations of all capacitors, the general duty ratio adjustments can be obtained directly by (16). Meanwhile, the reference variation v ref keeps zero, as shown in (17).
Noted that, the ACC ignores the voltage difference between C 1 and C 2 when v ref > 0. In this way, the 0 level is excluded in this stage, which avoids the extra switching action. Similarly, the voltage difference between C 5 and C 6 is also ignored when v ref ≤ 0, and the 6E level is excluded. Besides, the duty ratio adjustment of each output level must be less than its original value. For the three-phase VMC system, the duty ratio adjustments of each phase can be calculated respectively.
Finally, the control diagram of the proposed strategy is illustrated in Fig. 6. The switching pulses can be easily obtained by three equations and switching states table.

V. CHARACTERISTICS ANALYSIS
This section analyses the characteristics of the proposed strategy, including the capacitors voltage ripple, switching loss and total harmonic distortion (THD) of line-to-line voltage. The analysis results are compared with VSVM [18].

A. CAPACITORS VOLTAGE RIPPLE
VSVM realizes the capacitors voltage balancing within one T c , which means its average value of voltage ripple in T c is zero. Generally, the capacitors voltage ripple in VSVM is  smaller. For the proposed strategy, the voltage balancing is achieved within one-third T f . The voltage ripple is effected by the C, I m , MI and PF. Its amplitude of voltage ripple is calculated here.
It can be seen that in Fig. 7, the capacitors voltage ripple increases along with the PF when MI is low; however, the trend is opposite when MI is high. With the MI increasing from 0 to 1, the voltage ripple firstly increases and then decreases. Overall, the proposed strategy has a good performance of voltage ripple under the high MI and high PF condition.

B. SWITCHING LOSS
The switching loss of single switch P L in one T f is expressed as (19) [22].  where, t on and t off are the switching turn-on time and turn-off time respectively. And i s represents the switching current. i s = |i o | when the switch acts. Otherwise, i s = 0. It should be noted that, in the different intervals of one T f , the phase switching actions n s per carrier cycle are different. Take phase a as example. For the VSVM, n s = 12 in the intervals [0, π/6), [5π/6, 7π/6) and [11π/6, 2π]; n s = 10 in the intervals [π/6, 5π/6) and [7π/6, 11π/6). For the proposed strategy, n s = 10 in the intervals [0, π/3), [2π/3, 4π/3) and [5π/3, 2π ]; n s = 0 in the intervals [π/3, 2π /3) and [4π/3, 5π/6). Taking account of the difference of n s , the average switching loss of VSVM and the proposed strategy can be obtained as Fig. 8.
In Fig. 8, the proposed strategy has less switching loss compared with the VSVM with full range. The reduction is obvious especially under the high PF condition. When the PF is 1, a 51.2% reduction of switching loss is achieved.

C. THD OF LINE-TO-LINE VOLTAGE
The THD of line-to-line voltage v ab in VSVM and the proposed strategy under different MI is illustrated in Fig. 9. The comparison is based on the ideal simulation environment. Fig. 9 shows that the proposed strategy has higher THD of v ab at low MI. However, when MI is higher than 0.65, the output voltage THD in the proposed strategy is smaller than the VSVM.
It can be concluded from the above-mentioned analysis, with a certain increase of capacitors voltage ripple, the pro- posed strategy achieves significantly reduction of switching loss and lower THD of line-to-line voltage than VSVM under the high MI and high PF condition.

VI. SIMULATION AND EXPERIMENT
In order to verify the feasibility of the proposed voltage balancing strategy, the simulation model and experimental platforms of 3P7L-VMC are constructed in this paper. Fig. 10 shows the experimental platform. The main parameters are listed in the Table 2. Fig. 11 shows the simulation results of VSVM and the proposed strategy under the high MI and high PF condition (MI = 0.87 and PF = 1). It is known from Fig. 11(a) that, the phase a voltage v a of VSVM contains six levels (for two-third of T f ) or seven levels (for one-third of T f ) per switching cycle. However, v a of the proposed strategy contains six levels (for two-third of T f ) or be clamped without switching actions (for one-third of T f ). In this way, the switching loss are significantly reduced in the proposed strategy. The line-to-line voltage v ab is shown in Fig. 11(b). Noted that, the THD of v ab in the proposed strategy (46.4%) is less than that in the VSVM (58.5%). Consequently, a good performance of load a current i load_a is achieved in the proposed strategy, as shown in Fig. 11(c). From Fig. 11(d), the VSVM achieves voltage balancing within one carrier cycle, its capacitors voltage ripple are negative related to the carrier frequency. In this simulation case, its capacitors voltage ripple is about 0.12V. It also can be seen in Fig. 11(d), capacitors voltage balancing of the proposed strategy is attained within  one-third T f . The ripple of v C1 and v C6 , v C2 and v C5 , v C3 and v C4 are opposite. Their amplitudes are 1.5V, 0.9V and 0.3V, respectively.

A. SIMULATION RESULTS
Except the simulation results of high MI and high PF (MI = 0.87 and PF = 1) condition shown in Fig. 11, other three operation conditions are also discussed, including the high MI and low PF (MI = 0.87 and PF = 0.1), low MI and high PF (MI = 0.5 and PF = 1), and low MI and low PF (MI = 0.5 and PF = 0.1) conditions. The performance comparison for VSVM and the proposed strategy is summarized in Table 3 and Table 4. From these results, some observations can be obtained as following.  1) Both VSVM and the proposed strategy can achieve the dc-link capacitors voltage balancing under full operation conditions. 2) Lower voltage ripple is the main advantage of VSVM.
Its amplitude of voltage ripple have little difference under different operation conditions. 3) For the proposed strategy, its output voltage THD decreases when MI increases. Under the high MI region, the output voltage THD of proposed strategy is lower than VSVM. 4) The proposed strategy has less switching loss than VSVM under full operation conditions. This loss reduction ratio reaches about 50% under the unity PF condition. Consequently, for the proposed strategy, the benefits of reduction of switching loss and lower output THD are obvious under the high MI and high PF condition.

B. EXPERIMENTAL RESULTS
The steady experimental results of the proposed strategy under high MI and high PF condition are shown in Figs. 12-15. Fig. 12 shows the overall output waveforms of 3P7L-VMC, it verifies the validity of proposed strategy. In Fig. 12(a), v a is VOLUME 9, 2021 clamped to 360V or −360V for one-third T f , other two phases voltage are the same but phase-shifted ±120 • . As shown in Fig. 12(b), v ab is synthesized by thirteen levels, each level voltage is 120V. The line-to-line voltage is sine wave with high frequency harmonics. The load current and dc current are illustrated in Fig. 12(c). As seen, good performance of load current is achieved in this system. The average value of i dcP is about 10A. And carrier frequency fluctuation can be observed in the i dcP . Fig. 13 shows the harmonic spectrums of line-to-line voltage and load current. The THD of v ab is 49.91%. As seen, its most harmonics are around the carrier frequency f c and twice f c . Hence the resonant frequency of LC filter is set as f c /5 to achieve a good attenuation effect. The three-phase load current are shown in Fig. 13(b), and its THD is about 2.81%. Fig. 14 shows the details of v a . When 0 < v ref_a < 1, v a contains E-6E levels; and when When −1 < v ref_a < 0, v a contains 0-5E levels. Noted that, before v a is clamped to 6E (v ref_a = 1) in the next T c , the transition levels of 2E-5E are injected to avoid multilevel jumping. Each transition level remains 2µs for the complete action of switches. Similarly, the transition levels are also required before v a is out of clamping states of 6E. Since the transition levels are only injected twice in one fundamental cycle, the switching loss and THD will not be affected obviously. Fig. 15 shows the capacitors voltage. The waveforms of condition without initial voltage offset is illustrated in Fig. 15(a). The balancing of all dc-link capacitors voltage is achieved within one-third T f . Where C 1 and C 6 have the larger voltage ripples than other capacitors, their amplitude is about 1.7V (1.46% of rated voltage). The system can operate well at steady condition. In Fig. 15(b), set the initial value of v C1 -v C6 as 0.9E, 0.85E, 1.3E, 1.2E, 0.85E and 0.9E, respectively. After the ACC is trigged, the voltage balancing  is achieved again in 250ms. This verifies the effectiveness of the ACC.
To verify the analysis of switching loss for the VSVM and the proposed strategy, the experimental results of power loss and efficiency are obtained by the power analyser (HIOKI 3390), as summarized in Table. 5. It can be seen that, the system efficiencies of VSVM and the presented strategy are 96.39% and 96.58% respectively. The power loss of VSVM is 261W, which is 13W higher than the presented strategy. This power loss difference is basically coincided with the aforementioned analysis.
The dynamic experimental results, including the start-up and the input voltage variation experiments, are shown in Fig. 16 and Fig. 17 respectively. As seen in Fig. 16(a), during the start-up phase, the modulation index increases from 0 to 0.87 in 200ms. The waveforms of v a and v ab change according to M . Correspondingly, the amplitude of i load_a increases to its rated value gradually. The waveforms of capacitors voltage are shown in Fig. 16(b), before the system starts up, the parameter differences lead to certain offset of capacitors voltage. This voltage offset is eliminated quickly when the system starts up and the ACC is trigged.  In Fig. 17, the modulation index keeps 0.87, while the input voltage V dc drops from 720V to 600V firstly and then recovers after 0.5s. It can be seen that, the system output voltage and current change smoothly during the V dc variation process. And the dc-link capacitors voltage keeps balanced under both the steady and dynamic conditions.

VII. CONCLUSION
A voltage balancing strategy for V-clamped multilevel converter is proposed in this paper. The carrier waveforms are modified firstly to achieve the natural voltage balancing. The discontinuous reference waves are also adopted to clamp one phase in each carrier cycle, which reduces the switching loss. Furthermore, an active compensation control for voltage balancing is presented. By adjusting the duty ratio of output levels, the capacitors voltage is compensated without changing the output voltage.
Simulation and experimental results show following features of the proposed strategy: 1) carrier-based modulation leads to the simple calculation. 2) Capacitors voltage balancing with full operation range is obtained. 3) Compared with the virtual space vector modulation, the proposed strategy achieves reduction of switching loss and lower THD of output voltage under the high modulation ratio and high power factor condition. Its disadvantage is the larger capacitors voltage ripple. 4) The active compensation control enhances the system dynamic performance.
Consequently, the proposed strategy provides an effective solution for V-clamp multilevel converter under the high modulation ratio and high power factor condition.