A Non-Pulsating Input Current Step-Up DC/DC Converter With Common Ground Structure for Photovoltaic Applications

Many of the High Gain Step-Up DC/DC converters proposed in the literature do not share common ground and have a pulsating or discontinuous input current, making the converter unsuitable for solar photovoltaic applications. In this article, a non-pulsating input current (NPIC) with a high-gain DC/DC step-up converter is proposed and analyzed in detail. The converter shares a common ground structure and a voltage conversion ratio more than twice that of the Traditional quadratic boost converter (TQBC). The converter has two switches that operate in phase, which makes it easy to control. Also, the voltage stress across all semiconductor devices is lower than the output voltage, which enhances the efficiency of the converter. The loss analysis is carried out with the PLECS software, integrating the real models of switches and diodes from the technical datasheet. To confirm and validate the functionality of the proposed converter, a 200 W hardware prototype is being developed in the laboratory. It was observed that the maximum efficiency was 94.5% with an input voltage of 16V. The converter achieves high gain at low duty cycles and has been shown to perform well in open loop conditions.


I. INTRODUCTION
The voltage produced at the output of many distributed generation (DG) sources such as solar photovoltaic (PV) systems, batteries, and fuel cells is low and needs to be increased to higher levels for practical applications. The high-gain DC/DC converter plays an important role in DC Microgrid and EV. These converters can generate controllable high DC voltage at the output. There are numerous applications for these converters. These converters are used in EV, solar PV, robotics, and aerospace applications [1]. High-gain converters are advantageous over traditional boost converters (TBC) and their variants [1] because they are operated at much lower duty ratios to achieve the same voltage gain. This leads to better efficiency. These converters are broadly classified into isolated and non-isolated structures [2]- [8]. The requirement of electrical isolation between input and load to prevent flow of direct flow of current is fulfilled by isolated converters. The high frequency transformer is used to achieve isolation, but increases The associate editor coordinating the review of this manuscript and approving it for publication was Jiann-Jong Chen .
cost [3]- [7] and size. High step-up converters [8]- [13] with switched capacitor (SC) voltage multiplier perform better than in semiconductors voltage stress and power density. The capacitor in the SC circuit is charged by the input source when the switch is ON, and the stored energy is discharged when the switch is OFF, so the voltage conversion ratio is significantly improved. The converter proposed in the literature [14]- [15] do not operate in wide range of duty cycles. Such converters fall in the category of quazi-z-source or z-source converters where the inductor is replaced by an impedance network. In [16], a transformerless active switched inductance (ASL) with a simple structure with a low voltage load on the active switch is presented. To further increase the voltage gain and reduce the voltage load of hybrid switching reactors, converters are presented in [17]. An active LC network is used to overcome the disadvantage of the ASL network, as shown in [18]. These converters use two switches similar to the converter proposed in this article, but the converter in [18] lacks a common ground structure.
The common ground between input and output can be used to increase system performance, eg, photovoltaic systems connected to the grid without a transformer [2]. The general diagram of the photovoltaic system connected to the grid showing the application of the proposed converter is shown in Figure 1. The proposed converter has a common connection between the input source and the output loads. A voltage doubler is a very common method of multiplying the voltage conversion ratio [19]. In [19] a new impedance network is presented and the converter has the function of expanding the impedance network in n stages, but this deteriorates the efficiency of the converter.
A continuous input current of the step-up converter makes it suitable for renewable energy applications. This non-pulsating input current (NPIC) and the continuous current are included in the proposed converter. In the publication [20] a modified SEPIC converter with high gain with continuous input current is described. In [21] a buck-boost converter with a continuous input and output port with a higher conversion rate is proposed. In [22] another buckboost topology, but it has a discontinuous input current that limits some applications. A switched inductor voltage multiplier with a capacitor is used in a traditional quadratic boost converter (TQBC) (Figure 2) in [23] to achieve twice of quadratic gain but the converter utilizes three inductors, unlike the proposed converter. The voltage stress of the converter reported in [23] is the same as the output voltage which is a major demerit of the converter.
Interleaving of the boost converter reduces the input ripple, but the switches operate with a phase shift of 180 degrees if a two-phase interleaved boost converter is proposed. A clamped structure is proposed in [24] which is used with an interleaved converter to enhance the voltage conversion ratio but the common connection between output and input is lost. In [25] a quadratic gain converter is proposed that has a conversion ratio of exactly half that of the proposed converter. However, the above converters only take into account the voltage stress on the switch in the off state. No voltage stress on semiconductor components should be neglected. The output diodes in the converters discussed above have a voltage stress equal to the output voltage, so a high-rated power diode should be used at the output. The proposed converter is advantageous over these converters with low voltage stress on the output power diode.
The above discussion considers the voltage conversion ratio and voltage stress of semiconductor devices without considering the nonpulsating nature of the input current. A pulsating input current can shorten the life of the electrodes in energy storage applications [26]. An LC filter can be used to reduce the ripple in the input current, but the circuit becomes bulky and degrades the efficiency of the converter and the dynamic response of the converter [26]. Interleaving seems promising to reduce the input ripples, but the control of the switches is very complex, and extra circuitry will be required which makes the circuit bulky, unlike the proposed converter.
Knowledge of the need for a higher voltage gain, a low voltage stress on semiconductor components, a non-pulsating nature of the input current, and a common ground structure. This article proposes a high-gain DC / DC converter with the attractive properties mentioned above. The proposed topology has a simple structure and is easy to implement and can also be used for industrial use.
The remainder of the literature is as follows. Section II presents the operating principle of the proposed NPIC converter. Steady-state analysis of the NPIC converter in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) in detail. Section III presents the parameter guidelines of the NPIC converter and section IV covers the non-ideal analysis of the NPIC converter. Comparative analysis among the recent similar converters is done in Section V. To determine the efficacy of the converter hardware, results are presented in Section VI. Finally, the literature is concluded in Section VII.

II. OPERATING PRINCIPLE OF THE PROPOSED CONVERTER (NPIC) A. CIRCUIT DESCRIPTION
The proposed topology (NPIC) consists of two power switches (S 1 and S 2 ), five diodes (D 1 , D 2 , D 3 , D 4 , and D 5 ), two inductors (L 1 and L 2 ), five capacitors (C 0 , C 1 , C 2 , C 3 , and C 4 ) as shown in Figure 3. The load R is taken as purely resistive. The inductor L 1 is always attached to the input source V in , which contributes to the NPIC nature of the proposed converter. This is useful in reducing the current stress on the input dc source. The operation of the NPIC converter is explained in Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM).
In the following analysis, some logical assumptions are considered: a) All the semiconductor power devices and passive elements are Ideal and non-dissipative. b) Capacitance of all the capacitors is high enough to hold the voltage constant. c) All the inductors, capacitors and resistors are linear, timeinvariant, and independent of frequency.

B. CIRCUIT ANALYSIS IN CCM MODE
The converter operation in CCM mode can be divided into two modes: a) Mode 1 and b) Mode 2. Some characteristic waveform in this mode of operation is depicted in Figure 4. MODE 1 (t 0 to t 1 ): Both the switches are turned ON. In this mode, the equivalent circuit is depicted in Figure 5(a). Diodes D 2 and D 4 are forward biased. Diodes D 1 , D 2 , and D 5 are reverse biased. Inductor L 1 is charged through input dc source and L 2 is charged through capacitor voltage C 3 . The voltage and current relations can be obtained as where i L1 and i L2 are ripple-free inductor currents, i in is input current, i S1 and i S2 is on state current through the switches S 1 and S 2 .  MODE 2 (t 1 to t 2 ): Both switches are turned OFF at the beginning of this Mode 2. Diodes D 1 , D 2 , and D 5 are forward biased. Diodes D 2 and D 4 are reverse biased. Inductor L 1 is discharged and L 2 is discharged to supply energy load R. In this mode, the equivalent circuit diagram is depicted in Figure 5(b). The voltage and current relations can be obtained as

C. VOLTAGE GAIN CALCULATION
Applying voltage second balance on inductor L 2 during one switching period T.
The following relation between capacitor voltages can be obtained by equations (1), (3) and (5) Applying voltage second balance on inductor L 1 during one switching period T.
The voltage conversion ratio of the NPIC converter can be expressed using equation (7) where d is the duty cycle.

D. VOLTAGE STRESS CALCULATION
According to the above analysis, the voltages stress of capacitors can be expressed using equation (6).
The voltage stress on the power switches S 1 and S 2 in the proposed converter is V S1 , and V S2 can be calculated as The voltage stress on the power diodes D 1 to D 5 in the proposed converter is V D1 , and V D5 can be calculated as

E. CALCULATION OF CURRENT STRESS
Since the circuit is loss free. On applying energy conservation i.e.
The average input current I in or average inductor current L 1 is given by the below equation The ampere second balance on capacitor C 0 gives the following relation The average current through switch S 1 (I S1 ) is given using the result obtained in equation (13) Ampere second balance on capacitor C 4 gives the following relation The average current through the inductor L 2 is obtained by equation (15) Ampere second balance on capacitor C 3 gives the following relation The average current through switch S 2 (I S2 ) is given using the result obtained in Equation (17) In Mode 1, In Mode 2, The average values of currents (I Dx ) through all the diodes D 1 to D 5 can be expressed as

F. VOLTAGE GAIN ANALYSIS IN DCM MODE
The characteristic waveform is shown in Figure 6. The analysis is done in three modes. MODE 1 (t 0 to t 1 ): The switch is turned ON at t=0. This mode is the same as Mode 1 in CCM. Both the inductor current start increasing from zero and reaches to peak value at instant t=dT. The peak value of currents through inductors L 1 and L 2 expressed as MODE 2 (t 1 to t 2 ): The switch is turned OFF at the end of the dT interval similar to Mode 2 of CCM. Currents start to decrease with a constant slope, and the current of L 2 reaches zero at the end of the d 2x T interval. The current of the L 1 inductor continues to fall further as depicted in the figure. The inductor L 2 peak current in terms of d 2x T can be expressed as MODE 3 (t 2 to t 3 ): Both the switches are still OFF. The current in the inductor L 2 is zero. Therefore, the voltage across the inductor L 2 is zero. By using equations (22) and (23) the parameter d 2x can be expressed as During the OFF state of both switches. The average current through the capacitor C 3 , I C3 can be expressed as When substituting (22) into (25), I C3 can be derived as Since the average capacitor current is zero, therefore using (26) Voltage gain of the NPIC converter versus duty cycle.  When substituting the value of d 2x from (27) On solving the quadratic equation (28) the voltage gain in DCM mode can be expressed as The curve of voltage gain in this mode is presented in Figure 7.

G. BOUNDARY CONTINUOUS MODE OPERATION
In this mode of operation, the voltage gain of CCM is equal to the voltage gain in DCM mode.

G CCM = G DCM
The boundary normalized inductor time constant can be derived using (8) and (29) Figure 7 shows the boundary normalized inductor time constant versus duty ratio (d). The boundary between the CCM and DCM is depicted in Figure 8.

H. EXTERNAL CHARACTERISTIC OF NPIC CONVERTER
On combining the equation (29) with (30) the external characteristic of the NPIC converter can be depicted in Figure 8. It is to be noted from Figure 8 and Figure 9 the maximum value of β LB is 0.02113 at d=0.5428.

I. INPUT CURRENT RIPPLE
The difference between the maximum (i L1,max ) and minimum (i L1,min ) of the inductor, current L 1 is the input current ripple VOLUME 9, 2021 of the NPIC converter. i in is the input current ripple. The following equations can be obtained.
The input current ripple can be expressed as The relationship between the duty cycle of the NPIC converter and traditional boost converter (TBC) can be expressed as (33) under the same conditions of inductor current, output, and input voltage.
The reduction in the input current ripple of the proposed NPIC converter in comparison to TBC can be expressed as (34) where i T is the input ripple of the TBC and d T is the duty of the TBC.

III. PARAMTER DESIGN GUIDELINES A. INDUCTOR SELECTION
The ON state of the current ripple in an inductor can be expressed as Hence the inductance value of L 1 and L 2 is calculated using equations (37) and (38) where r L1 % and r L2 % is percentage ripple allowed in the inductor currents L 1 and L 2 .
To operate the inductors in CCM mode, the following equation in (40) and (41) must be valid.

B. CAPACITOR SELECTION
The capacitor selection can be made by equation (41) where r C1 %, r C2 %, r C3 %, r C4 % and r C0 % is percentage ripple allowed in capacitor voltages.

C. SEMICONDUCTOR SELECTION
The parameter selection of power switch and diodes are based on their current and voltage stresses respectively, as tabulated in Table 1 as calculated in section II.

IV. NON IDEAL ANALYSIS OF NPIC CONVERTER
The actual real-world model of the NPIC will have some non-idealities. The non-ideal model of the NPIC converter is presented in Figure 10. The inductors (L 1 and L 2 ) equivalent series resistance (ESR) r L1 and r L2 is considered. MOSFETS S 1 and S 2 have on resistance equal to r S1 and r S2 . The diodes D 1 to D 5 forward voltage drop is V F and on-resistance equal to r D . The ESR of capacitors C 0 to C 4 is r C .

A. POWER LOSS IN INDUCTORS
The ohmic losses in the inductor depend on the current through the inductors L 1 and L 2 . P L1 and P L2 are the ohmic losses in the inductor L 1 and L 2 and I L1 rms and I L2 rms are root mean square value of inductor currents.

B. POWER LOSS IN SWITCHES
The two types of losses that occur in the MOSFET are ohmic loss and switching loss. Ohmic loss occurs due to the ON resistance of the MOSFET. I S1 rms , I S2 rms is the root mean square value of current passing through switch S 1 and S 2 . The total ohmic losses, P ohmic S,total occurring in both the switches is the summation of individual ohmic losses that occur in both switches.

P ohmic
S,total = k=2 k=1 I Sk rms 2 r Sk = I 2 S1 rms r S1 +I 2 S2 rms r S2 (45) Total switching loss in the MOSFET is denoted by where,t r and t S are rise and fall time of switches respectively and f S is switching frequency. Total loss in the switches is the summation of ohmic loss and switching loss.

C. POWER LOSS IN DIODES
Switching loss is neglected in power diodes. Losses occurring due to the on-resistance of the diode and the forward voltage drop are only considered in the calculation. On the basis of the calculation in Section II, the average and RMS values of current through diodes can be calculated as The power loss associated with the forward voltage drop V F in power diodes can be calculated as The ohmic loss occurring in power diodes due to internal resistance r D can be calculated as The total power loss in the diodes is the sum of the loss due to forward voltage drop and ohmic loss.

D. POWER LOSS IN CAPACITORS
The RMS value of the current through the capacitors can be expressed as The total losses in the capacitors due to ESR of the capacitor r C can be expressed as Thus, the efficiency (η) of the proposed NPIC converter can be calculated as η = P O P O + P L,total + P S,total + P D,total + P C,total where, Therefore non-ideal gain in CCM mode can be expressed as The curve of ideal voltage gain and non-ideal voltage gain with r S1 = r S2 = 0.07 , r L1 = r L2 = 0.2 , r C = 0.1 , r D = 0.04 , V F = 0.4V with duty ratio is shown in

V. COMPARISION AMONG SIMILAR DC/DC NON ISOLATED CONVERTER
In this section the comparative analysis of the NPIC converter with other previous topologies is carried out. The comparison is made based on the number of active and passive elements, the voltage gain and the voltage across the switch when the switch is off, the type of input current, and the availability of a common ground between the source and the load., as shown in Table 2. The comparison of the boosting capability of the proposed converter is shown in Figure 12 (a). It should be noted that the NPIC converter has the highest voltage in all duty cycles. According to Table 2, the converter indicated in [C] has the maximum number of components equal to 16, while the NPIC converter has a total of 14 components, which is the same as the converter indicated in [A]. The NPIC converter utilizes two switches equal to converters reported in [F] and [H] while all the converters reported in Table 2 [3] has the maximum number of diodes, while the NPIC converter uses five diodes which is less than the converter in [A]. The NPIC converter has the maximum number of capacitors. Since voltage gain is not a sufficient metric to evaluate the performance of the converter, several devices have been involved in the comparison of the converter. The voltage gains per inductor, voltage gain per switch, voltage gain per diode and voltage gain per capacitor count is presented in Figure 12(b) to Figure 12(e) respectively.
It can be observed that the proposed converter has the highest voltage gain per inductor as depicted in Figure 12(b). The voltage gain per switch count is depicted in Figure 12(c) since the converter reported in [G] consists of a single switch, so it has the highest voltage gain per switch. The voltage gain per switch of the NPIC converter is highest except converter   advantageous of all converters in this term due to the low count of diodes, but the NPIC converter the has also highest share of the diode in achieving gain except [B]. The voltage gain per capacitor count is depicted in Figure 12 The voltage stress of the switch is an important criterion for evaluating DC / DC topologies. A diagram of the normalized voltage stress of the switch is shown in Figure 12  has a discontinuous input current which restricts its operation.
Application for MPPT applications. A common ground connection between the load and the source makes the converter suitable for various applications. There is more safety, fewer protection problems and reduced electromagnetic interference (EMI). Moreover, there is no extra dv/dt between the input and output grounds. NPIC converter, TQBC and  Table 2. Therefore, it can be concluded that the NPIC converter has many advantages over the other listed converters.

VI. HARDWARE RESULTS OF THE NPIC CONVERTER
To validate the performance of the NPIC converter, a 200W hardware model is built with the specifications defined in Table 3. The input voltage waveforms and output voltage are shown in Figure 13(a). In the same figure, the input voltage VOLUME 9, 2021 is observed to be 12V and 102V at a duty ratio of 40%. The blocking voltage waveforms of both MOSFETS S 1 and S 2 are shown in Figure 13(b). The blocking voltages V S1 and V S2 of the switch S 1 are 20V and the switch S 2 is 46 V, which is 19.6% and 45% of the output voltage (V O ). The open-loop operation of the NPIC Converter is done in CCM mode. The inductor currents (I L1 and I L2 ) waveform associated with CCM Mode is shown in Figure 13(c, d) at a duty percentage of 40% and 30% at a constant resistive load of 450 ohms. As the duty ratio is decreased from 40% to 30%, the mean value of the currents of inductors L 1 and L 2 will decrease. From the same Figure 13(c) it can be seen that the mean value of the inductor currents L 1 and L 2 is 1.56A and 0.375A at a duty cycle of 40%. The ripple values of the inductor current are nearly equal to 25% in L 1 and L 2 . When the duty cycle is reduced to 30% the mean values of the inductor currents L 1 and L 2 are 1.5A and 0.362A, respectively.
The input current of the converter is equal to i L1 , hence the converter naturally has a continuous input current. In most of the switched capacitor topologies, a high ripple in input current is observed due to the large current drawn by the capacitors for charging. The voltages of the capacitors are depicted in Figure 13(e). The capacitor voltages C 1 and C 3 are found to be 17V and 34V, respectively. When both the switches are ON, the output diode D 5 is OFF and diode D 4 is ON. The standing voltages of diodes D 5 and D 4 are equal to 48V at a duty of 30% which is almost 57% of V o as depicted in Figure 13(f). When the diode D 1 is ON, diode D 2 is OFF as shown in Figure 13(g) the blocking voltages of both the diodes are equal to 17 V which is equal to 20% of the V o . Low voltage stress across the semiconductors (switches and diodes) allows the use of low voltage rating devices with low on-resistance, to improve the efficiency. The converter performance in dynamic conditions from Figure 13(h-i). In Figure 13(h) as the input voltage increases from 12V to 16V, the output voltage increases from 90V to 120V at a fixed duty of 0.34. In the next Figure 13(i) as the duty cycle is decreased from 0.34 to 0.3 with a fixed   input voltage of 12V, the output voltage is decreased from 90V to 82V.
The efficiency versus output power of the converter is presented in Figure 14, as the output power is increased the efficiency decreases as the current in the converter increases which results in more power loss in the converter. As the input voltage has increased the efficiency of the converter increases as seen from Figure 14. The loss bifurcation among the components is presented in Figure 15. The losses in the system are determined using PLECS software. The maximum power loss occurs in the diodes (47%) as concluded from the same figure. The losses in the switches (S 1 and S 2 ) is close to 19%. The total losses in inductors and capacitors are 20% and 14% respectively.

VII. CONCLUSION
In this study, a non-pulsating continuous input current step-up DC/DC converter is NPIC. The operating principle and theoretical analysis in both CCM and DCM are discussed in detail. A shared connection between the input source and the load, non-pulsating nature of the input current of the NPIC converter makes it suitable for PV applications and energy storage systems. The converter can achieve a boosting factor of 8.88 at a gate pulse of 40%. From experimental results, it is verified that the voltage stress on the semiconductor devices is less than V o . The efficiency of the converter is high but decreases at high power output. This converter can be easily employed for applications up to 500 W. Based upon the comparative analysis of the voltage gain per devices count, the converter has a significant voltage gain(G) per device (N L , N S , N D and N C ) count over similar structures. The proposed converter is suitable for low and medium power applications. In the absence of galvanic isolation, the efficiency reduces at high power levels. The targeted power level is up to 500 W without cascading the converter or using the multilevel structure. The hardware prototype of a maximum power rating of 200W was tested for power ratings for efficiency analysis and the maximum efficiency was observed to be 94.5%. It was also observed as the input voltage is decreased the efficiency gets lower at the same power rating due to more conduction losses. The converter performance under dynamic conditions was found to be good and the experimental results fit well with the theoretical results. According to the performance of the converter, the converter can be a suitable candidature for high voltage renewable energy applications and grid-tied PV systems.