Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability

The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to reduce gate charge for high performance and to enhance avalanche ruggedness for reliability in switching applications. Reduced-surface-field (RESURF) techniques, including surface implant (P-Top), split-gate (SG), and shallow trench isolation (STI), with an optimum doping implant of the drift region, are presented to improve the on-state safe operating area (SOA) and hot carrier stress (HCS) reliability of DeNMOS after the gate charge reduction. It is shown that under unclamped inductive switching (UIS) conditions, the avalanche ruggedness of optimized devices is improved, whereas DeNMOS_C shows high susceptibility towards thermal runaway and device failure due to electrothermal effects. Switching performance shows a reduction of up to 46% in total gate charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {g}}$ </tex-math></inline-formula>) and more than 65% in gate-to-drain coupling charge (<inline-formula> <tex-math notation="LaTeX">$Q_{\mathrm {gd}}$ </tex-math></inline-formula>). Moreover, the highest improvement achieved in switching delay is 34%. The high-frequency figure of merits such as FoM1 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {gd}}$ </tex-math></inline-formula>) and FoM2 (<inline-formula> <tex-math notation="LaTeX">$R_{\mathrm {ON}}\times Q_{\mathrm {g}}$ </tex-math></inline-formula>) show significant improvement of up to 65% and 35%, respectively. The tradeoff in the DC figure of merits FoM3 (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}/R_{\mathrm {ON}})$ </tex-math></inline-formula> and Baliga-FoM (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {BD}}^{2}/R_{\mathrm {ON}})$ </tex-math></inline-formula> are also analyzed. Comparative analysis of optimized DeNMOS structures indicates that split gate DeNMOS without STI shows a minimum degradation of DC performance and the most significant improvement in high-frequency performance and switching reliability.


I. INTRODUCTION
Drain Extended MOSFET (DeMOS) is extensively used as a high voltage device in SoC and integrated circuit designs. It finds application in interface and I/O circuit design due to its high voltage blocking capability and integration with advanced CMOS processes [1]- [4]. The analytical study of CMOS compatible reduced-surface-field (RESURF) based STI DeNMOS and configurations of high-voltage devices using standard 5V CMOS technology are presented in [1] and [2], respectively. Applications of DeNMOS in CMOS level shifter [3] and RFIC [4] require high voltage capability and high-speed transient switching characteristics. For switching performance analysis, a power device gate charge (Q g ) is an industry-standard metric. A low gate charge value The associate editor coordinating the review of this manuscript and approving it for publication was Jiajie Fan .
gives high switching performance by reducing switching loss and delay. Multiple gate charge optimization techniques for lateral power MOSFETs are discussed earlier [5]- [10]. Polysilicon gate layout and doping optimization to reduce total gate charge (Q g ) and gate-to-drain coupling charge (Q gd ) are discussed in [5]- [7]. In recent works, superjunction and split gate topology achieved a superior tradeoff in on-resistance and Q g [8]. Schottky contact [9] and low-k dielectric in trench gate MOSFET [10] significantly improved the switching figure of merit and dynamic performance by reducing the gate charge.
This work shows that the presence of a long gate-todrain overlap length in conventional drain extended NMOS (DeNMOS_C) results in a significant rise of Q g and Q gd . However, in the absence of gate-to-drain overlap, a suitable RESURF technique should be applied to improve the on-state safe operating area (SOA). Earlier work on lateral power devices used RESURF based drift region engineering for an improved tradeoff between on-resistance (R ON ) and off-state breakdown voltage (V BD ) [11]- [13]. For example, a superjunction with a trench oxide layer achieved high V BD by modulating the bulk electric field and low R ON by creating a path for the electron current in a forward conduction state [14]. Similarly, field-shaping methods and the role of drift parameters to improve R ON and V BD are discussed in [15]- [17].
This work investigates multiple RESURF techniques such as the surface implant, split-gate, and shallow trench isolation (STI) in the drift region to ensure on-state SOA remains the same after the gate charge reduction. DeNMOS with the RESURF implant can significantly improve the breakdown voltage by reducing the surface field and is reported widely [18]- [20]. Application of the grounded field plate is another widely used RESURF technique. Source connected split-gate over the drift region act as a field plate to modulate the surface field [21], [22]. STI placed below the gate edge acts as RESURF to modulate the surface field and improve the gate oxide reliability [23]. STI enhances the gate edge reliability by shifting the peak electric field into the trench [24], [25].
Transient switching reliability becomes critical when these devices turn off from on-state under unclamped inductive switching (UIS) conditions. Electrothermal analysis for the unified study of SOA and UIS behavior of LDMOS was reported earlier [26]. We present a detailed investigation of the switching avalanche reliability of optimized DeNMOS structures using electrothermal simulations to explain the time evolution of bipolar triggering, space charge modulation, and lattice heating. Simulation results show that DeNMOS with lower avalanche ruggedness experience self-heating induced bipolar triggering and space charge modulation, resulting in current crowding and device failure due to increased lattice temperature. It is also shown that optimized devices achieved higher avalanche ruggedness than DeNMOS_C, thereby improving the device reliability in switching applications.
In this paper, section II presents different DeNMOS structures using various RESURF techniques and their simulation setup. Then, section III discusses the gate charge optimized DeNMOS design steps using drift region layout and doping optimization. Finally, we present an analysis of avalanche behavior and switching performance for all the optimized DeNMOS in section IV, followed by a conclusion in section V.

II. DeNMOS STRUCTURE AND SIMULATION SETUP
This work uses a well-calibrated process file to simulate the conventional DeNMOS (DeNMOS_C) using triple well CMOS process technology, shown in Fig. 1(a). The structure comprises an extended lightly doped drain known as the N-drift region with a gate-to-drain overlap length (L OV ) of 200 nm to modulate the surface field. It has a gate oxide of ∼2 nm and uses n-well and p-well in the standard CMOS process as N-drift and P-body regions. The junction of P-body   [11]. and N-drift is the edge of intrinsic MOS with a channel length (L CH ) of 200 nm. Fig. 2 shows the calibration of DeNMOS_C [11]. The DeNMOS_C structure is further modified using different RESURF techniques in the drift region, and its L OV is scaled to 50 nm to reduce its gate length. The DeNMOS designs shown in Figs. 1(a)-1(d) have the same source to drain pitch, L CH , and other layout parameters except for drift regions. Modified DeNMOS with different drift region designs has been investigated and compared with the DeNMOS_C. Table 1 lists various DeNMOS drift region layout designs for different RESURF techniques used in this work. In extended-gate DeNMOS_C, a strong gate-to-drain coupling results in the degradation of switching performance. Hence, L OV is reduced to 50 nm to enhance switching performance. P-Top DeNMOS shown in Fig. 1(b) uses a P-type pocket with optimum doping and dimension near the gate edge. Surface implant using a P-type pocket near the gate edge is an effective RESURF technique. However, the presence of P-Top can significantly degrade R ON . Source connected split-gate (SG) DeNMOS labeled as SG_NonSTI is shown in Fig. 1(c), ensures RESURF at high drain voltage, while R ON degradation is minimal at low drain voltage.  SG_NonSTI has a source connected SG of 100 nm length considering high field effects near the SG edge. The distance between the active gate edge and SG is critical, and hence an optimum value is chosen without influencing the static characteristics [27]. Fig. 1(d) shows SG_STI DeNMOS with STI to suppress high field-effect near the SG edge. SG length was extended from 100 nm to 250 nm to sufficiently overlap over the STI region. Furthermore, we also varied the STI depth as 150 nm, 250 nm, and 350 nm to study its impact on device performance. All 2-D device simulations in this work are performed using the Sentaurus Device TCAD simulator [28].
The hydrodynamic carrier transport model is used to perform electrical simulations. Shockley-Read-Hall and Auger recombination models are included considering carrier generation-recombination. In addition, doping-dependent mobility models, high-field mobility saturation, and interface field-induced mobility degradation models are used for the simulation. Finally, the dynamic avalanche ruggedness of all the DeNMOS structures is compared using electrothermal simulations under unclamped inductive switching.

A. IMPACT OF GATE CHARGE OPTIMIZATION
Reduction of gate length and gate to drain coupling can minimize DeNMOS gate charges Q g and Q gd . The gate charge waveforms shown in Fig. 3 show that scaling the L OV for conventional DeNMOS from 200 nm to 50 nm can reduce Q g and Q gd by more than 40% and 60%, respectively. This significant reduction of Q g and Q gd can enhance device switching speed and reduce switching losses [6]. However, scaling the L OV degrades device R ON , output resistance (R OUT ), on-state SOA, and hot carrier stress (HCS) reliability due to high avalanche generation at P-body/N-drift junction near gate edge. The absence of the extended gate field plate effect, which can disperse the surface potential lines, gives such design challenges. After L OV scaling, L OV _50 DeNMOS in Fig. 4(a) shows a step increase in drain current at high drain voltage, which degrades on-state SOA. Furthermore, a high substrate current peak in L OV _50 DeNMOS [ Fig. 4(b)] results in substrate current induced body effect (SCBE) [29], which is responsible for the rise of drain current in the saturation region. From Figs. 4(c) and 4(d), it is observed that increased potential line crowding results in a high field-effect near the gate edge in the absence of an extended gate. A high electric field near the gate edge increases the impact ionization rate (IIR) near the Si/SiO 2 interface in L OV _50, reducing gate oxide reliability. Hence, there is a need to re-engineer the drift region of L OV _50 DeNMOS to enhance device SOA and reliability without compromising device transient switching performance.

B. DRIFT REGION LAYOUT OPTIMIZATION
As discussed in the previous section, the drift region surface experiences potential line crowding when the extended gate length (L OV ) is scaled from 200 nm to 50 nm [see L OV _50 in Fig. 4(d)]. L OV scaling thus degrades on-state SOA because of high IIR near the gate edge. The presence of an extended gate in DeNMOS_C can effectively modulate the surface potential lines and suppress peak IIR by shifting its location away from the surface into the bulk. The extended gate generates a uniformly distributed vertical field that overlaps with the lateral field at high drain voltage and helps in modulating the surface field [18]. As shown in Figs. 5(a)-5(b), an increase in gate overlap reduces the surface electric field near the P-body/N-drift junction. Moreover, depletion of the extended gate edge shifts the current path from the surface into the bulk, as shown in Fig. 5(d), while L OV _50 [ Fig. 5(c)] shows high surface current density. In conjunction with reduced surface current density, the modulated electric field lowers the IIR near the gate edge and shifts peak IIR into the bulk [ Fig. 4(c)], thereby improving on-state SOA [ Fig. 4(a)].
Implementation of RESURF techniques like P-Top, split gate, and STI can modulate the surface field to reduce IIR and improve on-state SOA after L OV scaling. Figs. 6(a)-6(f) shows the IIR contour plots for DeNMOS_C and layout-optimized devices. Like DeNMOS_C, layoutoptimized devices after L OV scaling can effectively suppress IIR and shift its peak away from the surface. Fig. 6(b) shows P-Top DeNMOS with a surface implant near the gate edge. Inserting a P-type region near the gate edge over the silicon surface can cut the lateral electric field and spread the surface potential lines near the gate edge, which helps in mitigating surface IIR. Dimension, doping, and location of P-Top are instrumental in defining the electric field profile within the drift region [20]. SG_NonSTI in Fig. 6(c) uses a source-connected split-gate (SG) to exert the field plate effect over the drift region and can effectively modulate the surface field. However, the edge of both the active gate and SG is prone to high field-effect due to potential line crowding, resulting in high IIR near the active gate edge. Therefore, the length of the split gate and its distance from the active gate should be minimum according to device technology specifications. Figs. 6(d)-6(f) shows the IIR plot for all the DeNMOS structures with the split gate and STI of different depths. STI with a low dielectric constant material like SiO 2 increases the potential drop in the drift region, which thus improves the P-body/N-drift junction breakdown voltage and gate oxide reliability near the gate edge. In SG_STI_150 [ Fig. 6(d)], smaller STI depth raises the electric field near the STI edge towards the source, leading to IIR near the STI edge. An increase in STI depth relaxes the electric field at the STI/N-drift interface, reducing the IIR near the STI sidewall, as indicated in Figs. 6(e)-6(f). Drift region engineering using various RESURF techniques thus enhances SOA for all layout optimized devices as shown in output characteristics in Fig. 6(g), while charge accumulation is also greatly reduced after gate-to-drain overlap length scaling, which thus improves the switching performance.

C. DRIFT REGION DOPING OPTIMIZATION
RESURF techniques to engineer drift regions can effectively enhance on-state SOA after L OV scaling, as discussed in the previous section. However, the high field at the active gate edge increases IIR near the P-body/N-drift junction after RESURF optimization. The rise of IIR near the P-body/N-drift junction results in the generation of the hot carriers near the intrinsic MOS channel edge, which degrades long-term reliability due to HCS [21], [24]. Therefore, drift region doping is optimized for each structure to reduce the  IIR at Si/SiO 2 interface near the P-body/N-drift junction and STI sidewall. Dose (D) and energy (E) of doping implants are analyzed to optimize the net charge within the drift region. Figs. 7(a)-7(h) shows the IIR plot near Si/SiO 2 interface across cutline C, E1, E2, and E3 depicted in Fig. 6. E1, E2, and E3 cutline correspond to the Si/SiO2 interface at the   Fig. 8(a), all the modified DeNMOS structures have higher R ON than DeNMOS_C as surface charge accumulation is reduced due to L OV scaling. In Fig. 8(b), off-state breakdown voltage characteristics show that drift region layout and doping optimization have little impact on device V BD , which varies within the acceptable range of 8V to 10V. Output resistance (R OUT ) is defined as the reciprocal of the slope of drain current at a given bias condition in output characteristics. A high value of R OUT indicates that the saturation current is less dependent on the drain voltage. All the optimized structures show a reduction in R OUT except for SG_NonSTI, as shown in Fig. 8(c). Optimum doping corresponding to each structure is selected such that the IIR remains smaller  than that of DeNMOS_C at Si/SiO 2 interface near P-body/Ndrift junction, and the tradeoff in DC parameters is minimum. Table 2 shows the selected doping dose and energy corresponding to each DeNMOS structure and its DC parameters.

IV. SIMULATION RESULTS AND COMPARISON A. AVALANCHE BEHAVIOUR ANALYSIS
DC characteristics of all the optimized DeNMOS structures are compared and shown in Figs. 9(a)-9(c). Doping optimized devices show similar on-state SOA as layout optimized devices with a slight variation in R ON , as shown in output characteristics in Fig. 9(a). Substrate current responsible for the substrate current induced bias effect (SCBE) at high drain voltage is suppressed for all the optimized devices, as shown in Fig. 9(b). IIR for all the devices is plotted across cutline C (Fig. 6), near the Si/SiO 2 interface, as shown in Fig. 9(c). IIR at the active gate edge (C1) is reduced for all the selected optimized structures compared to DeNMOS_C. Lower IIR near P-body/N-drift junction improves HCS reliability near the intrinsic MOS channel edge. After L OV scaling, implementation of drift region optimization techniques resulted in the desired on-state SOA and increased HCS reliability.
The dynamic avalanche reliability of all the DeNMOS structures under unclamped inductive switching (UIS) conditions is analyzed using electrothermal 2-D TCAD simulations [30]. Figs. 10(a)-10(d) shows the UIS test circuit and its corresponding waveforms. The gate electrode receives a 1.2V pulse of finite duration, and V D is provided with a voltage close to the breakdown voltage of DUT. During the on-state of DUT, the drain current is ramped up as a function of supply voltage V D and load inductor L. Drain current reaches its peak when the DUT is turned off, as shown in Fig. 10(c). In the absence of a freewheeling diode across inductor L, the inductor current starts discharging through the internal body diode of DUT as there is no inversion channel in the absence of gate supply. Fig. 10(d) shows an abrupt rise of drain voltage for devices with higher avalanche ruggedness.   DeNMOS_C shows the highest susceptibility towards thermal runaway [ Fig. 10(b)] and eventually device failure at a given UIS condition. The thermal runaway at longer times corresponds to an exponential rise of temperature and results in device failure due to excessive heating. P-Top, SG_NonSTI, and SG_STI_350 show avalanche reliability with reduced lattice heating, whereas junction temperature rises for SG_STI_150 and SG_STI_250. The exponential rise in temperature is due to current crowding and filamentation near the drain after space charge modulation [31]. To demonstrate how different physical behavior like parasitic NPN BJT triggering and lattice heating of DUT evolve with time under UIS conditions, we investigate contour plots of DeNMOS_C, P-Top, SG_NonSTI, and SG_STI_350 to explain the dynamics of parasitic NPN BJT triggering and thermal runaway.

1) DYNAMICS OF BIPOLAR TRIGGERING
After the DUT is turned off, its drain voltage rises to support the large drain current, as shown in Fig. 10(d). High drain voltage results in avalanche-generated holes within the DUT, which lowers the barrier across the source substrate junction and triggers parasitic NPN BJT. From Figs. 11(a)-11(d), it is observed that strong bipolar is present in all the devices at time T=3 µs [ Fig. 10(c)]. However, at time T=5 µs [ Fig. 10(c)] parasitic bipolar of SG_NonSTI and P-Top is entirely switched off, while SG_STI_350 shows a weaker parasitic bipolar effect than DeNMOS_C [ Figs. 12(a)-12(d)]. The delay in avalanche degradation is responsible for a large parasitic bipolar current at longer times. An increase of avalanche degradation time raises the lattice temperature, and hence we observe the highest junction temperature in the case of DeNMOS_C [ Fig. 10(b)].

2) DYNAMICS OF THERMAL RUNAWAY
Devices DeNMOS_C, SG_STI_150, and SG_STI_250 show a thermal runaway, whereas the maximum junction temperature of P-Top, SG_NonSTI, and SG_STI_350 starts decreasing at longer times, as shown in Fig. 10(b). The exponential rise of lattice temperature with time due to space charge modulation and subsequent current filamentation is explained using DeNMOS_C, as shown in Figs. 13(a)-13(d). The NPN BJT of DeNMOS_C is weaker at T=7 µs [ Fig. 13(b)] compared to time T=5 µs [ Fig. 12(a)]. However, the drain current of DeNMOS_C is increasing at T=7 µs [ Fig. 10(c)] instead of decreasing with a reduced current density of NPN BJT [ Fig. 13(b)]. The rise of the DeNMOS_C drain current after T=5 µs results from lattice heating-induced threshold voltage degradation, which turns on the MOS channel. High drain current eventually results in space charge modulation [ Fig. 13(a)], which starts shifting peak electric field and lattice temperature hotspots towards the drain [ Fig. 13(c)]. The electric field near drain diffusion (location A at N + /N-well interface shown in Fig. 14(b)) is plotted for all the devices in Fig. 14(a). The rise of the electric field at point A results in avalanche generation of holes which triggers parasitic NPN BJT again, hence for DeNMOS_C, SG_STI_150, and SG_STI_250, NPN regenerative feedback mechanism is observed. Eventually, the rise of lattice temperature and an electric field near drain diffusion results in an exponential rise of drain current, and at T=10µs non-uniform current distribution results in current filamentation near both source and drain [ Fig. 13(d)] [31].
It should be noted that drift region layout optimization can improve the switching performance by reducing the gate charge. However, doping optimization plays a significant role in improving avalanche reliability in DC and transient conditions. From Fig. 15, we observe that P-Top and SG_NonSTI avalanche ruggedness is low, and their drain current increases exponentially without doping optimization. Whereas the presence of STI has improved turn-off avalanche reliability when compared to DeNMOS_C. The presence of STI suppresses the IIR, which reduces the avalanche degradation time and improves the avalanche ruggedness.   After doping optimization, reduction in doping dose and increased doping energy enhanced the avalanche reliability of P-Top and SG_NonSTI, whereas the reduction of doping energy lowered the same for SG_STI_250 and SG_STI_350.

B. SWITCHING PERFORMANCE ANALYSIS
Gate charge is a critical parameter that evaluates the switching speed and losses of the transistor. The gate charge characteristics [6] are simulated using the test circuit depicted in Fig. 16(a). The simulation uses 10 4 cells connected in VOLUME 9, 2021 parallel and a 10 µA current source connected to the gate. In Fig. 16(b), the gate charge waveform shows a significant reduction of Q g and Q gd for all optimized devices compared to DeNMOS_C. Q g is the total gate current multiplied by charging time at V GS = 1.2V, while Q gd corresponds to the product of total gate current and period for which gate voltage remains constant in Fig. 16(b) [32]. The SG_NonSTI has the lowest Q gd (7.14 pC), which is a reduction of more than 70% compared to DeNMOS_C (23.88 pC), while other devices show a reduction in the range of 66.5% to 68% [ Fig. 17(a)]. SG_NonSTI also shows the lowest Q g (41.13 pC), which is 46.9% [ Fig. 17(b)] reduction compared to DeNMOS_C (77 pC). Transient switching delay waveform is plotted for all the devices using the inverter circuit shown in the inset of Fig. 18 (a). The gate is subjected to a 1.2 V voltage pulse with a rise and fall time of 100 ps. Fig. 18(a) depicts the output voltage waveform across load C L . The switching delay has improved for all the optimized devices in the range of 10% to 34% [ Fig. 18(b)], with the P-Top device showing the lowest propagation delay. The improvement in switching delay is a result of the reduced Q g and Q gd of optimized devices. P-Top gives the lowest switching delay as it has lower drain-tosource coupling than devices using a source-connected split gate.
The figure of merit (FoM) of a power device is dependent on R ON , V BD , Q g , and Q gd . We have calculated the highfrequency figure of merit FoM1 (R ON × Q gd ) and FoM2 (R ON × Q g ) for transient performance [33]. The smaller the value of FoM1 and FoM2 better will be the switching performance. FoM3 (V BD /R ON ) and Baliga-FoM (V 2 BD /R ON ) are DC figures of merit, where the higher the value better will be device conduction efficiency [34]. With the least R ON degradation and a significant reduction in both Q g and Q gd , SG_NonSTI shows the greatest improvement in FoM1 and FoM2 [Figs. 19(a) and 19(b)]. Large R ON in P-Top and STI-based DeNMOS has reduced the percentage improvement in their FoM1 and FoM2 compared to SG_NonSTI. Although an increase in R ON has resulted in the degradation of FoM3 and BFoM of optimized devices [Figs. 19(c) and 19(d)], in the case of high-speed switching applications, switching losses are much higher than conduction losses. Hence, significant improvement in FoM1 and FoM2 will outperform reduction in DC figure of merits as switching performance at high-speed switching applications is greatly improved.

V. CONCLUSION
This work presents a comprehensive comparative investigation of various RESURF techniques to optimize DeNMOS_C for high performance and avalanche reliability in switching applications. The on-state SOA of the gate charge optimized DeNMOS is enhanced using RESURF, whereas doping optimization of the drift region improved onstate HCS and switching reliability of optimized structures compared to DeNMOS_C. We investigated three structures of DeNMOS: P-Top, SG_NonSTI, and SG_STI (with STI depth of 150 nm, 250 nm, and 350 nm). Electrothermal simulations under the UIS test condition show improved dynamic avalanche ruggedness and switching reliability of optimized structures compared to DeNMOS_C. Moreover, all the optimized structures showed a reduction of Q g (46% to 46.8%), Q gd (66.5% to 70%), and switching speed (10% to 34%) compared to DeNMOS_C. In addition, the highfrequency figure of merit FoM1(R ON × Q gd ) shows 40% to 65% improvement, and FoM2 (R ON × Q g ) shows 5% to 35% improvement for optimized devices. The presence of STI has shown improvement in on-state and switching avalanche reliability, while optimized P-Top shows the lowest switching delay. Furthermore, compared to other optimized structures, SG_NonSTI shows the best FoM1, FoM2, and the lowest degradation of FoM3 (V BD /R ON ) and Baliga-FoM (V 2 BD /R ON ) with the highest switching reliability. Thus, it can be concluded that the use of RESURF techniques and drift region doping optimization can significantly enhance the switching performance and reliability of DeNMOS while also avoiding the severe concerns of on-state SOA and HCS reliability.
SHRADDHA PALI is currently pursuing the Ph.D. degree with the Centre for Applied Research in Electronics, Indian Institute of Technology Delhi (IIT Delhi), India. Her Ph.D. topic is co-design of drain extended MOS devices for high performance and reliability in switching applications. Her current research interests include device simulation and optimization.
ANKUR GUPTA received the Ph.D. degree from IIT Bombay, in 2015. He was an I/O Circuit Designer with Texas Instruments Inc., where he was responsible for architecture definition of the I/O, implementation by circuit design at schematic level and characterization. He was a Visiting Research Scholar with Intel Inc., Germany, where he worked on RF power amplifier design. He also worked at Global Foundries Singapore, where he was responsible for RF-CMOS fabrication process integration. He is currently an Assistant Professor with the Indian Institute of Technology Delhi, New Delhi, India. VOLUME 9, 2021