Quantitative feedback theory control to improve stability in dc catenary feeding traction and auxiliary drives

The progressive electrification of railways involves an increasing number of power electronic converters connected to the railway catenary, which may compromise its stability. Both the converter for traction and the converter for auxiliary power systems (APS) behave as constant power loads (CPL) and interact negatively with the catenary impedance producing voltage instability. This article applies quantitative feedback theory (QFT) to design an ac voltage controller for the APS converter that shapes the dc input admittance of the converter by performing only ac side-control without a dc-side feedback loop. The QFT enables to design a low order controller that satisfies multiple performance specifications in systems with high uncertainty as is the case of the train system. The proposed control guarantees catenary stability while ensuring ac output voltage reference tracking and providing robustness to unmodeled uncertainties. As an additional contribution, the article presents an algorithm for including input admittance specifications in the QFT design process. The proposed control has been evaluated on an experimental platform that recreates the train system. Experimental results show that the controlled system meets railway standards and correctly shapes the specified dc input impedance.


C
Capacitor of the output filter in the APS. Maximum overshoot for T Ru (s). ω g Angular frequency of v C . ω nu , ω n l Natural frequency for T Ru (s) and T R l (s), respectively. P CP L Power consumed by the traction converter.

R CAT
Resistive term of the catenary impedance. R L Parasitic winding resistance of L. R LF Parasitic winding resistance of L F . S d Sensitivity function. σ u , σ l Damping ratio for T Ru (s) and T R l (s), respectively. T d (s) Tracking transfer function. T Ru (s), T Rl (s) Upper and lower limit of T d (s). t su , t s l Minimum and maximum settling time. V CAT DC catenary voltage. v c APS ac output voltagê v Cdq APS dq-axis small-signal ac output voltage.

V Cdq
Operating point ofv Cdq . v P CC Small-signal PCC or APS input voltage. V P CC Operating point ofv P CC .
Open-loop APS input admittance. Y LO Auxiliary load admittance. Y C AP S−C Curve between the permitted and not permitted admittance regions. Z AP S−C Closed-loop input impedance of the APS. Z CP L CPL impedance modeling the traction converter. Z F CAT Output impedance of the LC filter and the catenary. Z LO Auxiliary load impedance. Z S Output impedance seen from the APS.

I. INTRODUCTION
R AIL is one of the most sustainable modes of transport thanks to its growing electrification and the increasingly use of renewable energy sources [1]. For that reason, it is set to become a key player in reducing transport emissions. In Europe, for example, railway is mostly electrified and represents only 0.5 % of the greenhouse gas emissions of all modes of transport, while it transports 11.2 % of freight and 6.6 % of passengers [2]. Electrification leads to an increase in the presence of power electronics converters that are connected to the catenary. Typically, the train is equipped with converters for traction and converters to supply auxiliary systems. These converters are connected to an ac or dc catenary at a point of common connection (PCC). Although the presence of ac catenaries is predominant in modern highspeed corridors and common in long distance railways with heavy traffic [3], dc catenaries are still prevailing in short and medium distance railway systems and urban rail transport (light rails, tramways or metros) [4], [5] and constitute 47.3 % of railway lines around the World [6].
The interaction between the catenary and the controlled power electronics converters can cause oscillations in the catenary voltage [7]. This problem is inherent to the appli-cation and is caused by the fact that a voltage-controlled converter behaves as a constant power load (CPL) in some frequency ranges [8]. A CPL is equivalent to a small-signal negative resistance, since an increase in the voltage implies a decrease in the current and vice versa in order to keep constant power [9]. In this case, the auxiliary voltage-controlled converter or auxiliary power system (APS) behaves as a CPL because its main objective is to keep a regulated ac voltage [10]. Given the static nature of its load, keeping a stationary ac voltage (50 Hz and 400 V) implies consuming a constant power. A torque control is applied to the traction converters, but as the speed varies slowly, it can be considered also as a CPL [11]. These catenary voltage fluctuations compromise stability and can lead to a voltage drop on the railway line, which has a negative economic impact. Not considering the problem during the design stage may result in additional costs due to on-site adjustment of the APS by a team of engineers, the possibility of rejection of the equipment by the customer or having to oversize the LC filter capacitor [12]. This stability problem has been studied extensively in trains with ac catenary [13]- [17] and less widely in railway systems with dc catenary [18]- [20] on which this work focuses. Figure. 1 presents the block diagram of the dc railway system under study. The dc catenary or dc overhead line is generated by the substation, which has traditionally used a 12-pulse rectifier to perform the ac-dc conversion [6], [21]. The catenary feeds a power-controlled traction converter and a voltage-controlled auxiliary power system (APS) converter through an LC filter. The functions of the filter include filtering ac components in the PCC and preventing the transmission of voltage peaks in the catenary to the converters. As mentioned above, the CPL behavior of both converters have a negative impact on the PCC stability. The LC-filter capacitance can be designed to ensure system stability, but usually the design only takes into account the connection of the traction converter. For this reason, the connection of the auxiliary systems can still cause undesirable oscillations in the PCC.
The frequency of the PCC oscillation is variable, because it depends on resonance frequency of the LC filter. The resonance frequency is also a function of the catenary impedance which varies with the position of the train along the catenary. The rail catenary is divided into sections of several kilometers, with each substation, feeding two adjacent sections. The greater the distance of the train from the substation feeding the catenary section, Le CAT , the greater the inductive-resistive impedance of the catenary, L CAT and R CAT . The LC-filter resonance frequency decreases as catenary inductance increases, so it may conflict with the low-frequency CPL behavior [12] [8] of the converters and destabilize the system. Different approaches have been proposed to improve catenary stability, being possible to classify them in two main categories. The first group consists of adding passive components to the system and includes both passive damping [22]- [24] and adding more capacitance to the LC filter [12]. The DC railway system. The dc catenary is generated by the substation through an LC filter. Two power electronics converters (PECs) are connected to the PCC: the power-controlled traction converter and the voltage-controlled auxiliary converter which is a three-phase inverter with LC output filter.
second approach is based on modifying the control of the converters. It includes two main methods: active damping [19], [20], [22], [25], [26] and input-admittance shaping [13], [18], [27], [28] of the auxiliary converter to meet an impedance-based stability criteria (such as Middlebrook [29], Opposing Argument [30], Gain Margin Phase Margin (GMPM) [31] or Energy Source Analysis Consortium (ESAC) [32] criteria). In general, the control-based approach is preferred because adding passive components increases the cost and weight of the train. This article proposes a voltage control for the auxiliary converter based on the use of the Quantitative Feedback Theory (QFT) [33] to shape the dc input admittance/impedance of the converter. The main objective of the proposed design is to shape the input admittance of the converter to meet an impedance-based stability criterion to ensure stability in the catenary. In addition, the converter must regulate its ac output voltage and be robust to non-modeled uncertainties. QFT control makes it possible to synthesize a simple, loworder, minimum-bandwidth controller that satisfies multiple specifications in uncertain systems [34].
In this paper, the QFT controller is designed to meet three performance specifications (input admittance, reference tracking and relative robustness [35]) ensuring stable and correct system operation over the full range of variation of catenary inductance, catenary voltage and auxiliary load.
The main contribution of the proposed control is to shape the dc input admittance of the auxiliary converter to guarantee catenary stability, while ensuring perfect reference tracking of the ac output voltage and offering robustness to non-modeled uncertainties. A thorough search of the relevant literature yielded no related literature on shaping the dc input impedance by performing only ac-side control with no dcside feedback loop. Another contribution of the article is to propose an algorithm to include input admittance specifications in the QFT design process. The proposed algorithm uses the opposing argument criteria, but it can be modified to use any other impedance-based stability criterion.
The rest of this article is organized as follows. Section II briefly describes the methodology of the QFT-based design process. Section III presents the modeling of the system and its uncertainties. Section IV defines the performance specifications and determines the bounds in which the QFT design is based. Section V describes the steps of the QFT design considering the modeled dc rail system and the proposed specifications. Section VI deals with the verification of the design QFT controller. In Section VII, the performance of the proposed controller is evaluated in a experimental setup. Finally, Section VIII concludes the article.

II. QFT DESIGN PROCESS IN A NUTSHELL
Quantitative-feedback theory (QFT) control belongs to the so-called robust control techniques and was first formally formulated by Horowitz and Sidi in 1972 [36]. Since then, it has been used in diverse fields such as aerospace applications [37], [38] or mechatronics [39], [40]. A few examples are found in the fields of power electronics [41]- [43] and power systems [44], [45].
QFT technique simultaneously reduces the effects of plant uncertainty and satisfy performance specifications through feedback [46]. The uncertainty model of the plant G(jω) (see Section III) and its frequency and time specifications VOLUME 4, 2016 (see Sections IV-A,IV-B,IV-C) define a set of curves in the Nichols charts, known as bounds (see Section IV-D), which are used as a guide to obtain the open-loop transfer function, L(jω) = K(jω) · G(jω). The bounds delimit the permitted and not permitted values that L(jω) can take.
After defining the bounds, the synthesis or loop shaping of the controller K(jω) is essentially visual and performed on the Nichols chart (see Section V). The designer introduces gain, zeros and poles into K(jω) to make the open-loop function L(jω) lie near its bounds at each frequency to obtain an optimal controller [34]. After designing a controller, it must be validated by analyzing the frequency-and timedomain performance (see Section VI). Fig. 2 shows the main steps of the QFT design that will be described in detail applied to the converter control design in the following sections.

III. SYSTEM MODELING A. DYNAMIC MODELING
A critical factor for system stability is the interaction between the closed-loop input impedance of the APS Z AP S−C and the output impedance that it sees toward the catenary Z S . Both impedances can be obtained analyzing the small-signal model of the system presented in Fig. 3.
The small-signal model in synchnonous-reference frame (dq-axes) presented in Fig. 3.(a) is derived from modeling the components of the system represented in Fig. 1. The diagram of the dc railway system shows that the ac transmission line feeds the dc catenary voltage V CAT through the substation, which consists of a three-phase transformer and a 12-pulse rectifier. From the point of view of the train, the catenary can be modeled as a ideal voltage source with and equivalent series RL impedance, L CAT and R CAT . The LC filter between the catenary and the PCC is modeled considering the parasitic winding resistance R LF in the filter inductance L F and an ideal shunt capacitor C F . The traction converter connected to the PCC is modeled as a CPL [12] in which an impedance Z CP L consumes a constant power P CP L . Modeling the traction converter as a CPL with finite bandwidth assumes the worst case in terms of stability and challenges the proposed control for the auxiliary converter.
The APS is depicted in detail in Fig. 1. It consists of a voltage-controlled three-phase inverter with an LC output filter, C and L, in which the inductance winding resistances R L are considered as parasitic elements. In this paper, only a resistive load Z LO is going to be considered as auxiliary load. The dq-axes small-signal model of the APS comprises a dc small-signal circuit and two coupled ac small-signal circuits [47] as shown in Fig. 3.
The output impedance Z S seen by the APS consists of the parallel of the CPL with the impedance network formed by the catenary and the LC filter.
In this type of systems, the design of C F is made in order to ensure stability under the assumption that only the traction converter is connected to the PCC. Therefore, the connection of the APS to the PCC can be a potential source of instabilities.
The small-signal model of the APS is a multiple-inputmultiple-output (MIMO) system with 2 inputs (the duty cyclesd d andd q ), 3 outputs (the input currentî I and the output voltagesv Cd andv Cq ) and 3 input disturbances (the output currentsî Od andî Oq and the input voltagev P CC ). show the block diagrams of the input-output dynamical models for input currentî I and output voltageŝ v Cdq , respectively. The diagrams include the voltage controller K dq (s). These models help to determine the closedloop input admittance that will be one of the specifications in the control design.
The relationship between the dq-axes output voltagev Cdq with the dq components of the duty cycled dq is modeled in small signal as the matrix of open-loop transfer functions where A and B are transfer functions given by in which ω g is the angular frequency of the APS output voltage v C and Y LO = Z −1 LO is the load admittance. The relationship between the PCC voltagev P CC and the input currentî with The operating point of the duty cycle is given by where V Cd and V Cq are the operating points of the output voltagev Cdq and The transfer matrix that relates the input currentî I with the duty cycled dq is defining The relationship between the PCC voltagev P CC and the dq-axes output voltagev Cdq is given by the transfer matrix: where A and B are given by (2) and (3).
The APS closed-loop admittance can be obtained from The output impedance Z S (s) is defined as the parallel of the CPL impedance Z CP L and the output impedance seen toward the catenary Z F CAT (s): being

B. UNCERTAINTY MODELING
The plant model of the railway system under study is affected by a variety of uncertainties. First, the European standard for railway applications allows that the PCC voltage can vary from v P CC = 650 V to v P CC = 1000 V [48]. Second, the APS load condition can change from no load to Z LO = 3.2 Ω. Finally, the position of the train along the catenary can vary from Le CAT = 0 km to Le CAT = 4 km, which implies a variability R CAT and L CAT . The parameters listed in Table 1 has been used to analyze the system uncertainty. Both PCC voltage uncertainty and load uncertainty result in uncertainty in G VDdq . Uncertainty in V P CC also results, together with uncertainty in Le CAT , in variability in the output impedance Z S as it can be observed in Fig. 4. The QFT technique works with a set of frequencies of interest that are determined by inspecting the frequency response of the plants resulting from considering the range of uncertainty.
• Low frequencies for tracking and robustness specifications. The fundamental frequency of the abc-axes output voltage is f g = 50 Hz, but when applying the Park transformation, the fundamental dq-axes components are dc (that is 0 Hz). A frequency very close to 0 is selected: F 1 = 10 −5 Hz. • Medium frequencies for admittance and robustness specifications. Fig. 4 shows that resonance of Z S is between 12.     Figure 6 shows the Nyquist diagram of Z F CAT /Z CP L when only the CPL is connected to the catenary and for the worst conditions (maximum Le CAT and minimum V P CC ). It can be observed that the system is at the limit of stability under these conditions. If the APS control is designed to guarantee stability when the APS plugs in while the train is operating in this worst-case scenario, the rail system will be stable for any other situation.

IV. SPECIFICATIONS AND BOUNDS
Unlike other robust control techniques, the QFT technique only needs to deal with the nominal plant to synthesize the control, since all model uncertainties are included in the QFT bounds [34]. The QFT bounds are curves on the Nichols chart resulting from the combination of the model uncertainties in the form of the QFT templates (Fig. 5) and the type of specification. There exists a QFT bound at each frequency of interest and for each type of specification. The intersection of all the bounds at a frequency ω a determines the permitted values that the open-loop function L(jω a ) can take at that frequency. Fig. 7 shows the four possible types of bounds (n, u, o and i). Three types of specifications are considered for designing the controller: • Reference tracking, in which the objective is to track the voltage reference with zero steady-state error. As it was mentioned in subsection III-B, the fundamental components are dc signals in dq-axes. • Input admittance, which is the main objective in order to solve the problem under study. The aim is to obtain a closed-loop input admittance of the inverter that meets the opposing argument criterion. • Relative robustness, which aims to ensure that the designed control is robust to non-modeled uncertainties.
The three specifications are described in the following subsections.
The QFT bounds considering tracking and robustness specifications are obtained by using the QFT toolbox for Matlab [49]. The algorithm to obtain the QFT bounds from the input admittance specification is presented in this article.

A. TRACKING SPECIFICATION
For tracking performance considering low frequencies F 1 , it is desired that the settling time of the response of the controlled APS be between a minimum t su and a maximum t s l . The tracking specification is defined by constraining the tracking transfer function T d (s) between an upper limit T Ru (s) and a lower limit T Rl (s) : where The upper restriction T Ru (s) is chosen to meet a minimum settling time t su and a maximum overshoot M pu . From these two specifications, the dynamic behavior of a second-order system can be described in terms of its natural frequency ω nu and damping ratio ζ u [50]. It is advisable to relax the tracking condition at high frequencies, since the plant variability is higher than at low frequencies [34], so a zero is added a decade in frequency above σ u = ζ u ω nu , that is a = 10σ u . T Ru (s) is modeled as The lower restriction T Rl (s) is defined as a critically damped system (ζ l = 1) with a settling time t s l = 4/σ l where σ l = ω n l . It is also desirable to relax the tracking condition at high frequencies, but in this case a pole is added a decade above σ l . T Rl (s) is then given by: VOLUME 4, 2016

B. INPUT ADMITTANCE SPECIFICATION
The proposed solution is based on shaping the input admittance of the APS to meet the opposing-argument criterion [30] and ensure stability at the PCC. For that reason, an input admittance specification must be introduced in the QFT design. The algorithm that obtains the bounds for the input admittance specification is one of the main contributions of this article. The specification is set in closed-loop, Y AP Sdq−C (s), so the algorithm must transfer it to open-loop to generate the corresponding admittance bounds, LC d (s).
The variability in V P CC (650 V, 750 V and 1000 V), Z LO (3.2 Ω, 6.4 Ω and ∞ Ω) and Le CAT (0 km and 4 km) supposes 18 different combinations of parameters, while the number of frequencies of interest (F 1 , F 2 and F 3 ) is 11. Therefore, there are 18 · 11 bounds. The process is illustrated in Fig. 8 at a frequency of 12 Hz (ω a = 75.4 rad/s)and with v P CC = 650 V, Z LO = 3.2 Ω and Le CAT = 4 km. The process must be repeated for each combination of parameters and frequency. It consists of the following steps: • Step 1: Since the opposing-argument criterion is used, the desired gain margin for Z S (s)Y AP S−C (s) must be defined. In this case, GM op = 6 dB. The following restriction must be complied at ω a : Step 2: The curve between the permitted and not permitted admittance regions, Y C AP S−C (jω a ) is given by for ω a is calculated as LC d (jω a ) = f (Y AP S−C (jω a )).

C. RELATIVE ROBUSTNESS SPECIFICATION
The sensitivity function S d = (1 + K dq,(1,1) G V Ddq,(1,1) ) −1 is a good indicator of robustness, being its maximum peak an inverse indicator of the system stability [35]. A typical maximum value of |S d | max = 6 dB is chosen for all the frequencies of interest (F 1 , F 2 , F 3 ). It provides to the controlled system with at least a phase margin P M = 30 • and a gain margin GM = 6 dB, which are acceptable figures of robustness.

D. RESULTING BOUNDS IN NICHOLS CHART
The Matlab toolbox [49] and the proposed algorithm are used to obtain the bounds for each frequency of interest according to the QFT templates and the chosen specifications. The intersection of all the bounds results in the limiting curve for each frequency in (F 1 , F 2 , F 3 ). The Nichols chart that includes the bounds at each frequency (marked by a circle) and the nominal plant (black solid line) of the uncontrolled system is presented in Fig. 9.(a), in which the most restrictive bounds are of type n and u, corresponding respectively to the tracking and admittance specification. The design process of the voltage controller starts from this Nichols diagram.

V. QFT CONTROLLER DESIGN PROCEDURE
The QFT design procedure of the voltage controller is essentially a visual process, in which the designer introduces gain, poles and zeros into the controller transfer function to make the open-loop gain meet the bounds obtained in the previous step and shown in Fig. 9.(a). As mentioned above, there is an additional specification that limits the bandwidth to BW = f s /6 = 1.6 kHz. Fig. 9 illustrates the steps of the design procedure that consist of: • Step 1: An integrator is added to the controller for tracking the dc voltage reference, K 1 (s) = 1 s . It increases the gain and decreases 90 • the phase at frequency F 1 . • Step 2: A notch filter is added at 12 Hz, K 2 (s) = s 2 +30.84s+5944 s 2 +254.3s+5944 . It reduces the gain and increase the phase at medium frequencies F 2 . • Step 3: Three poles at 100 rad/s and three zeros at 70 rad/s are included into the controller, K 3 (s) = (s+70) 3 (s+100) 3 . They increase the phase at frequencies F 2 but with almost no reduction in gain, thus the bandwidth keeps constant. • Step 4: Three zeros are added to increase the gain at frequency 1600 Hz. In addition, two poles are included to make the controller strictly causal.
Step 5: Finally, the gain is adjusted to achieve the desired bandwith of 1600 Hz, G = 4078. The resulting dq-axes voltage controller is where

VI. THEORETICAL AND SIMULATION VERIFICATION
The QFT design process ends by verifying that the controller meets the different specifications through theoretical analyses and simulation. In case of the controller does not meet the requirement, the design process would be repeated after modifying the QFT design specifications.

A. THEORETICAL VERIFICATION
The tracking specification described in subsection IV-A is verified by analyzing the d-axis complementary sensitivity function T d (s). Considering all the rank of variability of the PCC voltage V P CC and of the load Z LO , Fig. 10 shows that T d (s) meets the specifications and is between the limits T Ru (s) and T R l at low frequencies where the tracking specification is defined. The input admittance specification described in IV-B is the most important objective to be met by the voltage Step 1 Step 2 Step 3 S c S d control proposed in this article. Fig. 11 presents a comparison between the frequency response when the APS is not connected (Z F CAT /Z CP L ) and when the APS is operating (Z S (s)/Z AP S (s)) with the maximum auxiliary load (Z LO = 3.2 Ω). The worst case has been considered (maximum distance, Le CAT = 4 km, and minimum PCC voltage, V P CC = 650 V). Fig. 11 shows that the designed controller meets the opposing-argument criterion for the input admittance/impedance, Re(Z S (s)Y AP S−C (s)) > −1/GM op . Finally, Fig. 12 verifies that the maximum value of the sensitivity function is lower than the maximum specified in subsection IV-C, |S d | max ≤ 6 dB . The maximum value of S d is given for no load (Z LO = ∞ Ω) and maximum voltage (V P CC = 1000 V). Fig. 13 shows the system response to steps in the catenary voltage V CAT . The negative impedance of the CPL is higher as the PCC voltage is lower. Therefore, the test is performed by setting the catenary voltage steps within a minimum range (650 V -750 V) to assume the worst case. In addition, an auxiliary power load connected to the APS close to zero (Z LO = ∞ Ω) is equivalent to assuming that the APS is disconnected from the system for the V P CC stability. Hence, the system has been evaluated assuming maximum auxiliary power load (Z LO = 3.2 Ω). Fig. 13.(a) shows the PCC voltage response to catenary voltage steps with and without the APS operating. Two catenary voltage steps has been tested: from V CAT = 750 V to V CAT = 650 V at t = 0.1 s and from V CAT = 750 V to V CAT = 650 V at t = 2 s. It can be observed that in both cases the PCC voltage oscillates in a underdamped way but stable, being the response with the APS opearting with full load slightly better than with only the CPL connected to the PCC. Fig. 13.(b) shows how the controlled output voltage V C d tracks the output voltage reference V * C d with an underdamped transitory after the V CAT steps. Fig. 13.(c) shows how the a-phase output voltage is still correctly regulated after the voltage steps.

VII. EXPERIMENTAL RESULTS
The proposed approach is experimentally evaluated with two different objectives. First, it is evaluated that the system complies with the european railway standards EN 50533 [51] and EN 61287 [10] under load changes and input voltage variations. Second, it is verified that the controlled inverter presents the modeled input impedance.
The experimental tests are carried out in the experimental setup shown in Fig. 14 whose main parameters are listed in Table 2. It consists of the following components: • A dc voltage source based on 2 parallel-connected programmable dc power supplies. • A boost dc/dc converter to emulate the dc catenary. The converter allows adding sinusoidal disturbance in the PCC for identifying the input impedance of the inverter and emulating the voltage jumps that usually occur in the catenary. • A three-phase inverter acting as the railway auxiliary converter. It consists of a three-phase two-level voltagesource converter with an LC output filter. • A programmable resistive load that emulates the auxiliary loads. Step 1: K 1 (s) Step 2: K 2 (s) Step 3: K 3 (s) Step 4: K 4 (s) Step 5: G   and EN 61287. The standards specify that the converter output must be regulated at a line rms voltage of 400 V and frequency 50 Hz under load and input voltage variations within the power and input voltage ranges of the converter. Fig. 15 shows the results when the inverter is operating in steady state with an input voltage V P CC = 750 V and feeds an 8 kW load. The total harmonic distortion in the voltage is T HD v = 2.5 %, lower than 8 % established in section 4.4 of the standard EN 50533 for linear loads. Fig. 16 and Fig. 17 show how the controller regulates undisturbed the output voltage in case of load jumps, in compliance with section 4.8 of the standard EN 50533 for power steps. In Fig. 16, the controlled inverter perfectly responds in case of a load step from 4 kW to 9 kW without appreciating any variation in the output voltage. A similar response is obtained with a load step from 9 kW to 4 kW as presented in Fig. 17. In both cases it can be observed that the variation in the output voltage is practically negligible, clearly complying with the standard, which establishes up to 40 % of permissible variation with respect to the rated value in the event of power steps from 0 % to 100 %.
Finally, Fig. 18 and Fig. 19 show as the output voltage reaches the nominal value after an input voltage step from 650 V to 750 V and from 750 V to 650 V, respectively. In both cases, the output voltage returns to nominal ratings in less of VOLUME   100 ms that is maximum time specified in section 4.5.3.20 of the standard EN 61287 after an input voltage step. Similar results in terms of time domain specifications could be obtained with a traditional controller such as a PI structure. However, due to its low order, it would not be able of shaping the dc input admittance to comply with impedance-stability criteria. More complex traditional control structures could shape this admittance but dealing with a high complex design process that could result in a highorder controller considering the multiple specifications and the uncertain model.

B. INPUT IMPEDANCE VERIFICATION
The input impedance of the inverter Z AP S must meet both the opposing argument criterion defined in Section IV with respect to the catenary output impedance Z S and a gain margin GM op lower than 6 dB. That implies a high value of the input impedance at 12 Hz, where the resonance of the input LC filter is maximum. The experimental identification of the input impedance is made considering a frequency sweep f d = [5 − 50] Hz and a power load of 8 kW. The boost dc/dc converter that emulates the catenary adds a constant-amplitude sinusoidal disturbance with frequency f d to the dc voltage. The PCC voltage V P CC and the inverter input current i I are acquired using an oscilloscope and then analyzed by applying an FFT algorithm to obtain their harmonic spectrum. The impedance at frequency f d is given by dividing the magnitude of the PCC voltage by the magnitude of the input current at frequency f d , Z AP S (f d ) = |v P CC (f d )| / |i I (f d )|. Fig. 20 shows a comparison among the theoretical frequency-shaped impedance (solid blue line) and the obtained in simulation (purple circles) and experimentally (brown crosses). Results successfully comply with impedance restrictions inherited from impedance criteria. A small deviation in module can be observed in certain frequencies due to model mismatching and measurement noise.

VIII. CONCLUSION
This article has addressed the stability problem in railway catenary with CPL behaving converters connected to their PCC. The approach consists in the QFT-based design of a voltage controller for the APS converter that ensures stability at the PCC of the catenary by meeting an impedance-based stability criterion. The proposed QFT voltage controller shapes the dc input admittance of the APS converter without a feedback loop on the dc side while tracking the ac output voltage reference and provides robustness to unmodeled uncertainties. To meet these three specifications at the same time will be not possible applying a classical PI controller due to its lack of controller order that reduces the design degrees-of-freedom below the needed to meet impedance-criteria or forcing to severely reduce tracking performance. More complex classical control approaches could deal with the design but at the cost of a cumbersome design process and resulting in high-order controllers. QFT proves to be a powerful tool in the design of controllers with multiple specifications and high variability in plant parameters. Additionally, this paper has provided an algorithm to include in the QFT the input admittance specification to meet impedancebased stability criteria. Experimental results have verified that the proposed QFT voltage controller complies with the European railway standards and that correctly shapes the specified dc input impedance.