Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis

In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneling FET (TFET) can be improved by using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. Our results indicate that TFETs in which DIBW dominates exhibit a steep subthreshold swing (≈35 mV/dec) and a low OFF-state current (<inline-formula> <tex-math notation="LaTeX">$\approx 10^{-16}\text{A}/\mu \text{m}$ </tex-math></inline-formula>) without affecting the ON-state current. We also show that TFETs exhibit a reverse short channel effect due to an increase in the tunneling width at the source-channel junction.


I. INTRODUCTION
With advantages such as a sub-60 mV/dec subthreshold swing (SS) at room temperature and a lower OFF-state leakage current, the tunnel field effect transistor (TFET) presents itself as a promising low power alternative to the conventional MOSFETs [1]- [6].
To enhance the performance of TFETs, different techniques have been attempted in the past such as bandgap engineering using a graded Si/Ge heterojunction TFET [7] and using dual spacer dielectrics [8]. Similarly, using a very lightly doped drain material (N D ≈ 1 × 10 17 cm −3 ) with low density of states (e.g. InGaAs), it has been shown that a reduction in OFF-state current and subthreshold swing can be obtained [9]. In such a structure, to reduce the drain series resistance, the length of the lightly doped drain should be limited to approximately 10 nm by backing it up with an n + -contact [9]. It has been shown recently that by using a non-uniform body thickness in a TFET, the ON/OFF current ratio of TFETs can be improved. Realizing such a structure requires precise control of device dimensions, particularly the channel thickness [10]. TFETs are the potential candidates to The associate editor coordinating the review of this manuscript and approving it for publication was Jesus Felez . surmount the performance challenges in transistors. Therefore, there is a great need to study the performance of TFETs using viable approaches required for future low power circuit applications.
In this paper, using calibrated two-dimensional simulations, we demonstrate that TFETs with low OFF-state leakage current and sub-60 mV/dec subthreshold swing can be realized without affecting the ON-state current using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. We show that the presence of DIBW leads to reverse short channel effects in TFETs as the channel length is reduced. Our results may pave the way, for realizing steep subthreshold TFETs with low OFF-state leakage current required in future low power integrated circuits. We discuss the device structure and the simulation parameter details in Section II and then present the simulation results in Section III. Finally, the conclusions are summarized in Section IV. Fig. 1 shows the cross-sectional schematic views for (a) the TFET with no gate-on-drain overlap (conventional TFET), (b) the single material gate (SMG) TFET using gate-on-drain overlap with uniform thickness for the gate oxide and the oxide under the gate-on-drain overlap (UOX-SMG), (c) the dual material gate (DMG) TFET using gate-on-drain overlap with uniform thickness for the gate oxide and the oxide under the gate-on-drain overlap (UOX-DMG), and (d) the dual material gate TFET using gate-on-drain overlap with differential thickness for the gate oxide and the oxide under the gate-on-drain overlap (DOX-DMG).

II. DEVICE STRUCTURE AND SIMULATION PARAMETERS
The device parameters used in our simulations are shown in Table 1. We have used three different drain doping concentrations (N D = 1 × 10 18 cm −3 , 5 × 10 18 cm −3 and 1 × 10 19 cm −3 ). For each of these drain doping concentrations, the gate work function ( G ) and the gate-on-drain overlap work function ( OL ) and the equivalent oxide thickness (EOT) under the gate-on-drain overlap (t OX,OL ), given in Table 1, are optimised for steeper subthreshold swing (SS) and low OFF-state current in DOX-DMG and UOX-DMG TFETs for L = 10 nm. The same gate work functions ( G and OL ) are then used in the other three structures. The length of the gate-on-drain overlap (L OL ) is chosen to be 30 nm in our study for the structures shown in Fig. 1 as this length has been shown to be the optimum gate-on-drain overlap length for reducing the ambipolar current in TFETs [11]. It has also been shown in [11], [12] that the AC performance of the device will not be impacted adversely by the gate-drain capacitance (C gd ) due to the gate-on-drain overlap. The gate-on-drain overlap and the step gate oxide required in this study can be realized using the fabrication techniques reported in [13]- [21].

III. SIMULATION APPROACH
All the simulations were done in Silvaco Atlas [22]. As described in [23], [24] our simulation set up was calibrated to the results in [4]. To take into account the lateral tunneling that takes place at the source-channel junction, we used a nonlocal band to band tunneling (BTBT) model. Due to the high doping concentration in the source and drain regions, the bandgap narrowing model is enabled. We used a concentration dependent model to include the mobility effects in our simulations. The Shockley-Read-Hall (SRH) recombination model and the Fermi Dirac statistics were also used. All the  doping profiles are assumed to be abrupt in these simulations as previously done in [23], [24]. Quantum mechanical effects are not considered for t si ≥ 7 nm [5], [25]. Therefore, we have not included quantum mechanical effects in these simulations as we have limited t si to 10 nm as previously done in [23], [24].

IV. RESULTS AND DISCUSSION
The transfer characteristics of a conventional TFET for different channel lengths and drain doping concentrations can be seen in Fig. 2. From Fig. 2 (a), we observe that even at the conventional drain doping concentration N D = 1 × 10 18 cm −3 , the transfer characteristics become non-ideal at a channel length of 10 nm and the TFET becomes unusable due to its poor subthrehsold swing and increased OFF-state current at V GS = 0.0 V. This is in agreement with the previously reported results [7], [9], and makes the device unsuitable To obviate the problem of poor subthreshold swing and large OFF-state current associated with short channel TFETs, we have studied three different TFET structures with gateon-drain overlap as shown in Fig. 1. For UOX-SMG and UOX-DMG TFET structures, we have used identical thickness for the gate oxide (t OX ,) and the oxide under the gateon-drain overlap (t OX,OL ). For DOX-DMG TFET, the oxide thickness under the gate-on-drain overlap is higher than the gate oxide thickness. In the case of UOX-DMG TFET and DOX-DMG TFET, the work function of the gate-on-drain overlap ( OL ) is higher than the gate work function ( G ).
The oxide thickness under the gate-on-drain overlap in the DOX-DMG TFET needs to be optimized with the goal of finding a balance between the lowest OFF-state current as well as ambipolar current. Fig. 3 shows the ambipolar current (I AMB ) at V GS = −1.0 V and the OFF-state current (I OFF ) at V GS = 0.0 V versus the oxide thickness under the gate-on-drain overlap (t OX,OL ) for three different drain doping concentrations. In Fig. 3 (a), we observe that the ambipolar current continuously decreases while the OFFstate current remains nearly constant with increasing t OX,OL . Therefore, we have chosen t OX,OL = 10 nm for DOX-DMG TFET for N D = 1 × 10 18 cm −3 . In Fig. 3 (b), we observe that the ambipolar current decreases while the OFF-state current increases with increasing t OX,OL . We note that, at t OX,OL ≈ 5 nm, the ambipolar current and OFF-state current are at an optimum value for N D = 5 × 10 18 cm −3 . In Fig. 3 (c), we observe that the ambipolar current initially decreases up to t OX,OL = 5 nm and increases for higher t OX,OL , while the OFF-state current increases continuously with increasing t OX,OL . We note that, at t OX,OL ≈ 3 nm, the ambipolar current and OFF-state current are at an optimum value for N D = 1 × 10 19 cm −3 . Therefore, to examine the short channel behavior of DOX-DMG TFET, we have chosen t OX,OL to be 10 nm, 5 nm and 3 nm for N D = 1 × 10 18 cm −3 , 5 × 10 18 cm −3 and 1 × 10 19 cm −3 , respectively.
In the following sections, we analyze the impact of the gate-on-drain overlap by comparing the short channel behavior of all the four TFETs shown in Fig. 1 by calculating the average SS, point SS and I ON /I OFF ratio from the transfer characteristics.
The average SS for all the TFET structures in this work has been calculated using the following expression [5]: where the threshold voltage (V t ) is the applied gate voltage when the drain current reaches a magnitude of 1 × 10 −7 A/µm, V off is the gate voltage at which the lowest magnitude of the drain current is observed when the gate voltage V GS ≥ 0.0 V, I Vt is the drain current at V t and I Off is the drain current at V Off . The point subthreshold swing is calculated as the reciprocal of the maximum slope of the transfer characteristics as given below [1]: where I DS is the drain current and V GS is the gate voltage where the slope of the transfer characteristics is maximum.
In the following sections, we examine how the gate-ondrain overlap can be effectively used to realize steep subthreshold performance and low OFF-state current.  Figs. 4 (a) and (b), either for L = 50 nm or 10 nm, we observe that the conventional TFET exhibits no ambipolar current. It may be noted that when L is reduced from 50 nm to 10 nm, due to short channel effects, the conventional TFET exhibits an extremely poor average SS and point SS as shown in Figs. 4 (c) and (d), respectively. However, in the case of UOX-DMG and DOX-DMG TFETs with L = 10 nm, the gate-on-drain overlap leads to an average SS and point SS well below 60 mV/dec as compared to UOX-DMG and DOX-DMG TFETs with L = 50 nm. Therefore, the UOX-DMG and DOX-DMG TFETs with a lightly doped drain can indeed lead to TFETs with an OFF-state current ≈10 −16 A/µm, an average SS well below 60 mV/dec, and I ON /I OFF ratio > 10 11 as shown in Fig. 5.  As compared to the conventional TFET, we observe that the UOX-DMG TFET becomes unusable due to its large OFF-state current as shown in Figs. 6 (a) and (b). However, the DOX-DMG TFET exhibits improved performance with a low OFF-state current ≈10 −14 A/µm, an average SS below 60 mV/dec and an I ON /I OFF ratio ≈ 10 10 as shown in Fig. 7 when L is reduced from 50 nm to 10 nm. It is clear that the DOX-DMG TFET with a higher drain doping concentration (N D = 5 × 10 18 cm −3 ) can indeed lead to TFETs with improved performance when compared to conventional TFETs with similar a drain doping concentration.   Fig. 8, either for L = 50 nm or 10 nm, we observe that the conventional TFET exhibits undesirable ambipolar current. For L = 10 nm, the conventional TFET becomes unusable due to the extremely poor I ON /I OFF ratio and its subthreshold swing cannot be calculated due to the same reason. For the four TFET structures, the average and point SS, are shown in Figs. 8 (c) and (d), respectively and their I ON /I OFF ratios are shown in Fig. 9. These results show that as compared to the conventional TFET, the DOX-DMG TFET exhibits an OFF-state current ≈10 −14 A/µm and an I ON /I OFF ratio ≈ 10 10 when N D = 1 × 10 19 cm −3 .
From the above discussions, it is clear that the UOX-DMG TFET with N D = 1 × 10 18 cm −3 and DOX-DMG TFET with N D = 1 × 10 18 cm −3 to 5 × 10 18 cm −3 are promising candidates for realizing TFETs with a low OFF-state current, an average SS less than 60 mV/dec and a high I ON /I OFF ratio. To understand the reason for the sub-60 mV/dec subthreshold swing and a low OFF-state current in the UOX-DMG TFET  and DOX-DMG TFET with a drain doping concentration 1 × 10 18 cm −3 < N D < 5×10 18 cm −3 , we have investigated the impact of channel length on the threshold voltage in the following section.

D. REVERSE SHORT CHANNEL EFFECTS
As shown in Fig. 10, the threshold voltage (V t ), i.e. the V GS when I DS = 1 × 10 −7 A/µm, of the four different TFET structures is extracted at different channel lengths from 50 nm to 10 nm for three drain doping concentrations N D = 1 × 10 18 cm −3 , 5 × 10 18 cm −3 and 1 × 10 19 cm −3 . From Figs. 10 (a) -(c), we observe that the V t of the conventional TFET decreases, as the channel length is scaled down, exhibiting the conventional V t roll-off. The V t for the conventional TFET with N D = 1 × 10 19 cm −3 and L = 10 nm is not shown in Fig. 10 (c), since it cannot be calculated due to the extremely poor I ON /I OFF ratio as seen in Fig. 9. However, as shown in Fig. 10 (a) with N D = 1 × 10 18 cm −3 and (b) with N D = 5 × 10 18 cm −3 , the UOX-DMG TFET and DOX-DMG TFET exhibit a threshold voltage roll-up when L is reduced from 50 nm to 10 nm. This is a clear indication of the presence of the reverse short channel effect as the channel length is scaled down. In contrast, as shown in    though OL > G , the energy barrier height under the gateon-drain overlap decreases, since the oxide thickness under the gate-on-drain overlap (t OX,OL ) in DOX-DMG TFET is larger than its gate oxide thickness (t OX ). This reduction in barrier height is due to the reduced capacitive coupling when compared to the UOX-DMG TFET. It can be observed from Fig. 11 (b) that as the channel length is scaled from 50 nm to 10 nm, the distance between the source-channel junction and the induced barrier height due to the gate-on-drain overlap has also reduced. This proximity modulates the energy profile in the channel region resulting in the drain induced barrier widening (DIBW), at the source-channel junction, a phenomenon observed for the first time in TFETs. DIBW results in an increase in the tunnel width at the source-channel junction in the UOX-SMG TFET, UOX-DMG TFET and DOX-DMG TFET as compared to the conventional TFET as shown in Fig. 11 (b). The presence of drain induced barrier widening at the source-channel junction implies that a higher V GS must be applied in UOX-DMG TFET and DOX-DMG TFET to achieve an I DS equal to that of the 50 nm TFET. We can, therefore, conclude that in order to observe the reverse short channel effect in a TFET i.e. threshold voltage roll-up, the TFET must have a gate-on-drain overlap (with OL > G ) and a channel length, L ≤ 20 nm. Fig. 12 shows the energy-band profiles of the UOX-DMG and conventional TFETs for L = 10 nm and 40 nm, respectively, with N D = 1 × 10 18 cm −3 at V GS = 0.0 V. It is apparent that the tunnel width at the source-channel junction of the UOX-DMG TFET is larger when compared to the conventional TFET, clearly indicating the presence of drain induced barrier widening (DIBW) induced by the gate-ondrain overlap. As reported in this work, DIBW is responsible for the steep subthreshold swing and reduced OFF-state current in TFETs with gate-on-drain overlap.

V. CONCLUSION
With the help of calibrated 2-D simulations, we have successfully demonstrated in this paper how the performance of a TFET can be improved by using a new phenomenon known as the drain induced barrier widening (DIBW) at the source-channel junction. We also demonstrate that due to an increase in the tunneling width at the source-channel junction caused by DIBW, the TFETs exhibit reverse short channel effects. By exploiting DIBW, we have shown how TFETs can maintain a sub-60 mV/dec average subthreshold swing (≈35 mV/dec), a low OFF-state current (≈10 −16 A/µm) and an I ON /I OFF ratio ≈ 10 11 with drain doping concentrations as high as N D = 5 × 10 18 cm −3 . Our results may serve as a strong incentive for the experimental realization of TFETs with improved performance.