Effect of Wafer Tilt During Ion Implantation on the Performance of a Silicon Traveling-Wave Mach-Zehnder Modulator

This paper reports a study of the effect of wafer tilt during dopant implantation on the performance of silicon PN phase shifter and traveling-wave Mach-Zehnder modulator. The PN phase shifter is designed and process simulated to include the effects of different fabrication processes in the device performance. The wafer tilt during implantation is varied from 0° to 3°, 5°, and 7°. The resulting crystal damage during dopant implantation to form the PN junction and the active concentration profile upon annealing, along with the formation of dopant–defect clusters, are discussed. Compared to 0° tilt, 7° tilt results in <inline-formula> <tex-math notation="LaTeX">$1.58\times $ </tex-math></inline-formula> higher phase shift and better modulation efficiency. The overall phase shifter performance is improved using 5° wafer tilt for implantation resulting in <inline-formula> <tex-math notation="LaTeX">$1.23\times $ </tex-math></inline-formula> lower absorption, <inline-formula> <tex-math notation="LaTeX">$1.45\times $ </tex-math></inline-formula> better modulation efficiency, and <inline-formula> <tex-math notation="LaTeX">$3.14\times $ </tex-math></inline-formula> higher 3 dB <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> modulation bandwidth for lumped-driven phase shifter. A traveling-wave electrode to enhance the modulation bandwidth is used, and the modulator performance for non-return-to-zero on-off-keying modulation with–2.5 V bias and 2.5 <inline-formula> <tex-math notation="LaTeX">$\text{V}_{pp}$ </tex-math></inline-formula> drive signal across each arm is evaluated using a dual-arm push-pull drive. The sample with 5° tilt shows better traveling-wave and modulator high-speed characteristics compared to the other samples. Among the four samples with different wafer tilts, the sample with 0° tilt shows the worst phase shifter performance, and the sample with 3° tilt shows the worst modulator characteristics. The best overall performance is obtained for the sample with 5° tilt. Compared to the modulator with implantation at 0° tilt, the 5° tilted sample shows <inline-formula> <tex-math notation="LaTeX">$2.3\times $ </tex-math></inline-formula> higher 6.4 dB electrical bandwidth and <inline-formula> <tex-math notation="LaTeX">$1.36\times $ </tex-math></inline-formula> higher 3 dB electro-optic bandwidth at–2.5 V using a traveling-wave electrode with <inline-formula> <tex-math notation="LaTeX">$1.48\times $ </tex-math></inline-formula> lower energy-per-bit for 5 km transmission at the KP4-forward-error-correction bit-error-rate threshold. The comparison of the effect of wafer tilt angles on various device metrics is presented and discussed.


I. INTRODUCTION
With rapid rate of increase in data traffic, there is a need to realize high link capacities and high-speed data integration. Optical modulators play an important role in integrating data into the light for free-space as well as fiber-optic communications. The global market for optical modulators has an expected growth of USD 8.14 billion for a forecast period 2021-2025 with a compound annual growth rate of 7.13% [1]. On-chip integrated silicon optical modulators have gained much popularity in recent years due to their compact size and low cost. Mach-Zehnder modulators (MZMs), The associate editor coordinating the review of this manuscript and approving it for publication was San-Liang Lee . as compared to ring modulators, have greater fabrication and temperature tolerance at the cost of having a larger footprint. Many studies have been done over the years to enhance the silicon modulator performance and mitigate various tradeoffs. The main component of an MZM is the phase shifter, which in silicon is realized through junction devices using the free-carrier plasma dispersion (FCPD) effect [2].
The modulator performance can be enhanced by using device-level and system-level engineering techniques. System-level engineering techniques include using higher-order modulation formats and different driving configurations to increase the modulation speed. Low bandwidth modulators can be used for high-speed operation VOLUME 9, 2021 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ using higher-order modulation formats like pulse amplitude modulation (PAM) [3], quadrature amplitude modulation (QAM) [4], etc. Generating higher-order modulation signals in the electrical domain leads to increased power consumption due to digital-to-analog converters [5]. Samani et. al. presented different MZM architectures for generating PAM-4 signal in the optical domain using on-off keying (OOK) electrical signals [6]. Ding et. al. used four MZMs driven by four electrical binary signals to generate a 16-QAM signal in the optical domain [7]. Device-level engineering techniques involve ways to enhance the FCPD effect and the modulation bandwidth. Sorianello et al. reported the intensity and phase modulation efficiency of single and double-layer graphene capacitive modulators on silicon for up to 50 Gbps operation [8]. Passoni et. al. showed enhanced modulation efficiency in the range 0.1-0.5 V.cm in slow-light silicon MZM with interleaved PN junctions with waveguide grating structure [9]. He et. al. demonstrated hybrid silicon/lithium niobate MZM with > 70 GHz bandwidth and 100 Gbps OOK modulation with 5 dB dynamic extinction ratio [10]. The authors have previously shown the effectiveness of using germanium in enhancing the performance of silicon modulators [11], [12]. Although multiple studies on improving modulator performance have been reported over the years, very few have reported on ways to improve the modulator performance of pure silicon modulators using device-level engineering techniques without using different materials and hybrid integration techniques. Yong et. al. demonstrated U-shaped silicon PN phase shifters with improved modulation efficiency to realize power-efficient modulators [13]. Li et. al. proposed a substrate removing technique to improve the modulation bandwidth of silicon MZM [14]. The authors have recently shown the dependency of the phase shifter metrics on preamorphization and annealing temperature and time [15]. The modulator performance can be optimized by adjusting various process parameters. A process simulation study can be used to emulate a fabricated device and to observe the effects of various process parameters on device metrics.
In this paper, the effects of wafer tilt during dopant implantation on the phase shifter and MZM performance are evaluated. To the authors' knowledge, this is the first comprehensive study that covers the effect of wafer tilt angles on MZM metrics viz., modulation bandwidth, bit-error-rate (BER) performance, extinction ratio (ER), fiber transmission length, fiber dispersion tolerance, and energy-per-bit. The phase shifter design is given in section II. Section III presents the process study and discusses the implantation damage profile, active dopant concentrations, and dopantdefect cluster formation for different wafer tilt angles during implantation. The phase shifter metrics, along with the lumped element analysis, are given in section IV. Section V presents and discusses the traveling-wave electrode and modulator characteristics along with a comparison of various device metrics for different wafer tilts. Lastly, section VI concludes the paper.

II. PHASE SHIFTER STRUCTURE
The PN phase shifter cross-section is shown in Fig. 1(a). A <100> silicon-on-insulator wafer with 0.22 µm top silicon height (H ), 2 µm buried silicon dioxide thickness (T BOX ), and 500 µm bottom silicon (not shown in figure) is used. The waveguide width (W ) is 0.5 µm with 0.1 µm slab (h). The PN junction is at the middle of the rib with the highly doped contact regions 1.75 µm from the junction on either side (W s = 1.5 µm). The top cladding (pre-metal dielectric) has a thickness (T PMD ) of 1.7 µm. The electrode dimension (W t × H t ) is 5.0 µm × 1.8 µm. The waveguide height and width are along the x and y axes with light propagation along the z axis. The wafer tilt angle (θ) is shown in Fig. 1(b) and is defined as the angle between the ion beam and the normal to the wafer.

III. PROCESS SIMULATION
The phase shifter is designed using the process simulator, Silvaco R Athena. The Monte Carlo implant module based on the binary collision approximation (BCA) is used for dopant implantation with 5000 ion trajectories at room temperature (300 K). BCA is used to simulate the interaction of dopant atoms with the host material and is based on a series of two-body interactions [16]. A brief history of different ion implantation models and the efficiency of BCA code can be seen in [17]. The wafer tilt angle, θ, is varied from 0 • to 3 • , 5 • , and 7 • . The beam divergence is 1 • . To form the P and N regions, boron and phosphorus are used with a dose of 5 × 10 13 cm −2 and 2 × 10 13 cm −2 at an energy of 17 keV and 30 keV respectively. A dose of 1 × 10 15 cm −2 each of boron and phosphorus is used at an energy of 17 keV and 30 keV to form the P++ and N++ regions. Each implantation step is followed by rapid thermal annealing at 1100 • C for 10 seconds in nitrogen ambient. An anisotropic uniform etch of 120 nm is done to form the P and N slab regions of thickness 100 nm. Oxide is deposited to form the upper cladding (PMD) layer. Vias are created to form the contact electrodes, and aluminum is deposited.
Implantation results in the dopant atoms taking interstitial sites and damaging the crystal order depending on the dopant dose and implantation energy. High-dose implants can lead to the formation of amorphous pockets in the crystal lattice. The amorphization threshold dose of boron and phosphorus in silicon is > 10 14 cm −2 and occurs when the defect density is >10% of the atomic density [18]. In this study, subamorphization doses of boron and phosphorus have been used to form the P and N regions. Annealing is done to recrystallize the damaged lattice and activate the dopant atoms, i.e. the interstitial dopant atoms substitutes a host atom [19]. Dopant implantation results in a Gaussianlike profile, the shape of which depends on the wafer tilt angles. For a <100> oriented wafer, considerable ion channeling will occur along the crystallographic axes. Tilting the wafer reduces the degree of ion channeling [20]. Initial annealing results in greater diffusion of the implanted dopant Gaussian tail relative to the high concentration Gaussian peak, known as transient enhanced diffusion [21]. Dopant diffusion is aided by silicon interstitials and vacancies that are created during the dopant implantation step [22]. During annealing, defect recombination and defect clustering occur. Also, dopant-defect clusters may form, leading to A m V n or A m I n pairs, where A is the dopant atom, and V and I represents vacancies and interstitials, respectively. Detailed defect reactions can be found in [18].
The lattice implant damage upon boron and phosphorus implantation is shown in Fig. 2(a) and (b) for different values of θ. At higher tilt angles, due to lower ion channeling, the damage concentration increases near the surface as few atoms channel towards the bottom silicon-oxide interface. As θ increases, most of the interstitial dopant atoms occupy the top half of the waveguide at a distance of 0.11 µm from the surface. The active boron and active phosphorus concentration upon annealing is shown in Fig. 2(c) and (d) for different values of θ. The Gaussian implantation profile is maintained at high tilt angles. The dopant diffusion during annealing is large for 0 • tilt with the highest active boron concentration of ∼2.6 × 10 18 cm −3 at a depth of 220 nm from the surface. The highest active phosphorus concentration for 0 • tilt occurs at a depth of 100 nm with a concentration of ∼9.5 × 10 17 cm −3 . The peak active boron and phosphorus concentration increase at higher θ, with the subsequent peak occurring at lower depths with increasing θ. In this study, a single step implantation is used to form the P and N regions of the phase shifter. The x, y, and z axes of Fig. 1(a) are the equivalent <100> directions. As shown in Fig. 1(b), positive θ indicates a clockwise tilt, which represents a rotation about the z axis. Since a single implantation step is used, the wafer itself is not rotated about the x axis. For modulator length along the y axis, the wafer would have to be tilted about the y axis. For negative θ, the same performance can be obtained by forming an N++ -N -P -P++ junction instead of P++ -P -N -N++ junction.

IV. PHASE SHIFTER ANALYSIS
The designed phase shifter is analyzed using Silvaco R Atlas device simulator. An applied reverse bias across the PN junction leads to majority carrier extraction, resulting in the increase of depletion width. The corresponding change in the refractive index ( n) and absorption ( α) with change in the carrier concentration at 1550 nm wavelength of operation is given as [24] n(x, y) = −8.8 × 10 −22 N e (x, y) where N e and N h are the respective changes in the electron and hole carrier concentrations with voltage. The effective refractive index (n eff ) and absorption loss (α eff ) is determined from the overlap of the mode field with the carrier distribution in the waveguide and is given as [25] where |E| 2 is the normalized mode power in the rib waveguide.
where L is the phase shifter length and λ is the free-space wavelength of light. The surface plot of the free-carrier concentration at 0 V bias across the waveguide rib for θ = 0 • , 3 • , 5 • , and 7 • is shown in Fig. 3(a)-(d), respectively. The cross-sectional mode intensity profile from Silvaco R Atlas simulation at 1550 nm wavelength is shown in the figure inset with the PN junction outlined. Atlas solves the 2D vector Helmholtz equation to determine the effective refractive index and effective absorption of each mode [26]. The difference in the modal distribution across the waveguide with θ is negligible. However, the carrier distribution across the rib waveguide changes as θ varies. The free-carrier concentration decreases with waveguide height at higher θ, which can also be seen from Fig. 2(c) and 2(d). In the waveguide rib, the P region becomes wider compared to the N region as θ increases. This can be visualized from Fig. 1(b). Also, the enhanced boron diffusion along the tail of the implanted profile leads to a right shift of the PN junction near the bottom of the waveguide. This leads to a larger modal overlap with the P region compared to the N region as θ increases.
The phase shift and absorption loss as a function of the reverse bias voltage are shown in Fig. 4(a) and 4(b), respectively. The positive voltage in Fig. 4(a)-(d) is the voltage applied to the cathode of the PN phase shifter, making it reverse biased. The phase shift increases with voltage as the depletion width widens, causing a larger change in the free carrier concentration across the PN junction. The phase shift increases with θ, and a larger change can be observed from 3 • to 5 • tilt from Fig. 4(a). This is due to the larger overlap of the mode field with the P depletion region. Holes lead to a larger change in the refractive index compared to electrons, as evident from (1a). The phase shift at 5 V reverse bias for 7 • tilted wafer is ∼67 • /mm compared to ∼42 • /mm phase shift for 0 • tilt, showing an improvement of 1.6×. The absorption loss shown in Fig. 4(b) decreases with an increase in the reverse bias voltage as the free carriers concentration decreases with a widening depletion region. The absorption depends on the modal overlap with the free carriers, and the carrier distribution in the waveguide rib determines the effective loss. The absorption loss is highest and lowest for θ = 0 • and θ = 5 • , respectively. The slope in the absorption loss for different values of θ is similar to the corresponding slope of the phase shift curves. The 5 • and 7 • tilts have a higher slope for both phase shift and absorption loss compared to 0 • and 3 • tilts. The depletion region becomes longer at higher tilts as the PN junction becomes two-dimensional, as can be observed from Fig. 3(a)-(d). The absorption loss at −5 V of the 5 • tilted phase shifter is ∼1.64 dB/mm compared to ∼2.02 dB/mm of the 0 • tilted phase shifter, showing an improvement by a factor of 1.23. The square root dependency of the depletion width on the voltage leads to the non-linear phase-voltage and absorption-voltage curves.
For light extinction in an MZM, the relative phase difference between the two arms should be an odd multiple of 180 • or π radians. The length of the phase shifter required to attain π phase shift is denoted by L π and is calculated to be 4.24 mm, 4.16 mm, 2.92 mm, and 2.68 mm for θ = 0 • , 3 • , 5 • , and 7 • , respectively at −5 V operation. The modulation efficiency is the product of the voltage and length for π shift and is 2.12 V.cm, 2.08 V.cm, 1.46 V.cm, and 1.34 V.cm for θ = 0 • , 3 • , 5 • , and 7 • at |V | = 5 V. The phase shifter created with θ = 7 • has the best modulation efficiency, while that with θ = 0 • the poorest. Another figure of merit taking both phase shift and absorption loss into effect is the αVL π product which gives the total loss (αL π ) at the voltage required for light extinction. For θ = 0 • , 3 • , 5 • , and 7 • , αVL π is 42.88 V-dB, 38.03 V-dB, 23.95 V-dB, and 24.32 V-dB, respectively. Although θ = 7 • shows the best modulation efficiency, θ = 5 • has better overall phase shifter performance. The phase shifter resistance and capacitance determine the RC modulation bandwidth when the MZM is driven as a lumped element. The small-signal analysis is done to determine the phase shifter admittance matrix, from which the frequency normalized impedance is calculated. The phase VOLUME 9, 2021 shifter capacitance (C pn ) and resistance (R pn ) at different reverse bias voltages are shown in Fig. 4(c) and 4(d), respectively. C pn and R pn have units of pF/cm and .cm respectively. The large depletion width at higher reverse voltages leads to lower capacitance. The different carrier distribution across the waveguide for different θ leads to different capacitance and resistance curves. C pn reduces and R pn increases as θ becomes large. In addition to the 1D diode capacitance, the total capacitance has multiple components due to the fringing electric field and widened depletion near the silicon-oxide interfaces [27]. The 1D diode capacitance per unit length depends on the depletion width and the length over which the depletion occurs. With large θ, the depletion width narrows along the top and widens along the bottom of the waveguide due to the high and low carrier concentration at the top and bottom, respectively. The phase shifter capacitances at −5 V for 0 • , 3 • , 5 • , and 7 • tilts are 903 fF, 800 fF, 276 fF, and 310 fF, respectively. The resistivity depends on the doping concentration and the carrier mobility. As θ increases, the P rib width increases, which leads to larger resistance as the hole mobility is lower than the electron mobility. Also, the slab resistance has a larger contribution to the overall phase shifter resistance since the slab height is much lower than the slab width. At larger θ, the slab resistance increases due to a reduction in the carrier concentration. The resistance is much larger for θ = 7 • compared to θ = 0 • , 3 • , and 5 • . This can be attributed to multiple reasons -the P region is much larger than the N region in the waveguide rib, and the carrier concentration is lower in the slab region.
The equivalent electrical circuit for lumped analysis is shown in Fig. 5 with a source resistance (R s ) and termination resistance (R t ) of 50 each [28]. The 3 dB RC bandwidth (f 3 dB ) for the lumped element is calculated as where R eq is the equivalent resistance seen from the right side of Fig. 5. Using R pn and C pn to determine f 3 dB results in a much larger value of the intrinsic RC bandwidth and is independent of the phase shifter length. However, the source resistance of the electrical driver and the on-chip termination resistance results in a length dependence of f 3 dB , whereby R eq is given as The 3 dB RC bandwidth at −5 V for the circuit of The phase shifter device simulation shows that among the wafer tilt angles taken, the 5 • tilt shows the best performance in terms of the αVL π product and 3 dB RC bandwidth. Varying the tilt angle during dopant implantation can be used to tailor the carrier distribution in order to enhance the phase shifter performance.

V. TRAVELING-WAVE MZM CHARACTERISTICS
On-off keying modulation is used with a dual-arm pushpull operation to drive the modulator. Each PN phase shifter arm has a length of 4.24 mm, 4.16 mm, 2.92 mm, and 2.68 mm for θ = 0 • , 3 • , 5 • , and 7 • with a V π = -5 V. The phase shifters are biased at -2.5 V, and a 2.5 V pp radiofrequency (RF) signal is applied to both arms to obtain π phase shift. The limitation in the modulation bandwidth when driven as a lumped element is overcome by using a travelingwave electrode (TWE) structure. The TWE configuration is shown in Fig. 6. The TWE is treated as a transmission line with a coplanar waveguide structure [29], whose inductive impedance cancels the phase shifter capacitance. TWEs are used to enhance the modulation bandwidth. The transmission line elements, viz., R tl , L tl , G tl , and C tl can be determined from the electrical equivalent circuit of the traveling-wave MZM. The calculation of the electrical elements are given in detail in [29]- [32]. The TWE parameters can be found in section II of this paper.
The transmission line impedance (Z tl ) and admittance (Y tl ) can be calculated as where ω is the microwave angular frequency, and R tl , L tl , G tl , and C tl are the transmission line resistance per unit length, inductance per unit length, conductance per unit length, and capacitance per unit length, respectively. R tl and L tl is same for all values of θ, whereas G tl and C tl varies with θ due to different R pn and C pn . The transmission line admittance, where f (X ) denotes function of X . With G tl = Re(Y tl ) and C tl = Im(Y tl )/ω, For all θ, ω 2 R 2 pn C 2 pn < 1. As ω increases, G tl increases and C tl decreases. The characteristic impedance (Z 0 ) and propagation constant (γ ) of the transmission line can be calculated as [33] Z 0 should ideally be equal to R s and R t so that back reflection does not occur. The microwave signal attenuation (α TWE ) as it travels through the electrode can be calculated from γ as [33] α TWE = 20 log e Re(γ )L π (10) Z 0 and α TWE for different tilt angles are shown in Fig. 7(a) and 7(b), respectively. Since R tl and L tl are same for all θ, Z 0 and α TWE is determined by G tl and C tl . In all the cases, ωC tl > G tl , and Z 0 follows C tl . The power dissipation in the TWE follows G tl . For the 5 • tilt, the impedance matching is better as well as the TWE attenuation is low. The worst-case occurs for 3 • tilt with > 19 dB signal loss at 45 GHz compared to ∼6 dB loss in case of 5 • tilt.
The electro-electro (EE) S-parameters are used to evaluate the TWE performance. EE S 11 gives a measure of the back reflection, and EE S 21 , the measure of the signal transmission loss. The EE S-parameters are calculated as [33] where the voltage reflection coefficient, when R s = R t . The EE S-parameters of the designed TWE for different values of θ are shown in Fig. 7(c) and follows the trend of Fig. 7(a) and 7(b). The lowest back reflection (EE S 11 ) occurs for 5 • tilt and is <-16 dB over 45 GHz range. The highest back reflection is -11.1 dB for 0 • tilt at ∼3.8 GHz. Another important TWE metric is the microwave index which should be matched to the optical group index. This indicates that both the high-frequency microwave voltage signal and the optical mode travels at the same group velocity. In the absence of velocity mismatch, the 3 dB electro-optic (EO) bandwidth can be determined from the 6.4 dB EE S 21 point. It can be observed from Fig. 7(c) that the 6.4 dB EE bandwidth is largest for θ = 5 • , which is > 45 GHz. The lowest bandwidth is for 3 • tilt at ∼ 16 GHz. Velocity mismatch between the microwave and optical group index leads to a 3 dB EO bandwidth different from the 6.4 dB EE bandwidth and is shown in Fig. 7(d). The 3 dB EO bandwidth is highest for 5 • tilt (∼ 41 GHz) and lowest for 3 • tilt (∼ 22 GHz), showing an improvement of 19 GHz. Compared with 0 • tilt, the 6.4 dB EE bandwidth and the 3 dB EO bandwidth for 5 • tilt are 2.3× and 1.37× higher, respectively.
The block diagram representation of the system-level simulation setup is shown in Fig. 8. A 10 mW continuouswave (CW) laser with 10 kHz linewidth operating at 1550 nm wavelength is used as the light source. A single-mode fiber (SMF) with 0.2 dB/km attenuation, 16.75 ps.nm −1 .km −1 dispersion, 0.075 ps.nm −2 .km −1 dispersion slope, 0.2 ps/km differential group delay, and 80 µm 2 effective area is connected between the modulator and receiver. The receiver is a photodiode (PD) with a responsivity of 0.7 A/W, 50 nA dark current, thermal power density of 10 −22 W/Hz, Gaussian shot noise distribution, and 30 GHz modulation bandwidth. A pseudo-random binary bit stream of order 13 is generated by a bit-error-rate (BER) test set, whose outputs are mapped to the driving voltage levels by an NRZ generator. S-parameter filters are used to include TWE data [34]. A clock recovery block is used at the output of the PD with a reference signal from the NRZ generator to compensate for the time delay in the received  signal. The data recovery block maps the electrical signal amplitude to a binary stream that is fed back to the BER test set. The eye viewer is used to generate the eye diagram. Multiple visualizers not shown in the picture are used to see electrical and optical time-varying signals and power levels. Generic data files containing the phase and absorption loss data at different voltages are imported in the MZM model. The system-level simulation is done using OptiSystem v17.1. With -2.5 V DC bias across the phase shifters in each MZM arm, a push-pull operation is used where one arm undergoes +2.5 V and the other arm -2.5 V. The maximum voltage difference is 5 V leading to π phase shift.
The SMF length is varied from 1 km to 5 km, and the effect of θ on the BER and the extinction ratio (ER) is shown in Fig. 9(a) and 9(b), respectively at 40 Gbps transmission. The BER is a measure of the number of error bits received relative to the total bits transmitted. BER ranges from 0 to 1, 0 being the best and 1 being the worst. The fiber dispersion leads to broadening of the data pulse, as a result of which the BER increases with fiber length. It can be seen from Fig. 9(a) that best performance is obtained for θ = 5 • . The 3 • tilt represents the worst case among the four samples. For error-free operation (BER = 10 −12 ), the transmission distance at 40 Gbps for θ = 0 • , 3 • , 5 • , and 7 • are < 1 km, ∼ 0 km, ∼ 3.7 km, and ∼ 2.5 km, respectively. The ER represents the ratio of light intensities for representing bit '1' and '0'. The maximum DC ER is > 25 dB for all the four tilt angles. The change in the dynamic ER with fiber length for 40 Gbps transmission is shown in Fig. 9(b). High dynamic ER implies low BER and vice-versa. The ER curve follows the BER curve with 5 • tilt having the highest ER and 3 • the lowest for any fiber length. Similar to the BER, the difference in ER reduces among different samples with an increase in fiber length. The BER and ER curves for different θ follow the TWE bandwidth curves of Fig. 7(c) and 7(d). Since the bandwidth is large for θ = 5 • , the BER is low and ER is large for the same data speed and fiber length compared to the other samples.
The BER as a function of the modulation speed is shown in Fig. 10 for 5 km SMF transmission. As the speed increases, the bit period decreases, due to which the effect of dispersion is more pronounced, leading to high BER and low ER. The BER increase as the speed is varied from 35 Gbps to 50 Gbps. For KP4-forward-error-correction threshold (BER = 2.2 × 10 −4 ), the speed for θ = 0 • , 3 • , 5 • , and 7 • is limited to 38.5 Gbps, 36.5 Gbps, 43.8 Gbps, and 41 Gbps, respectively. Again, the sample with θ = 5 • can reach higher speeds for the same BER compared to others due to its large 3 dB bandwidth.
The eye diagram of the four traveling-wave MZMs is shown in Fig. 11(a)-(d) for 3 km 40 Gbps transmission. A much wider eye-opening with large ER and low BER is  observed for 5 • tilt. The asymmetricity of the eye is due to the non-linear phase-voltage relation in silicon phase shifters as +2.5 V push and -2.5 V pull in the two arms do not lead to the same amount of phase shift. The effect of fiber dispersion on the BER and ER of the four MZMs are simulated and shown in Fig. 12(a) and 12(b), respectively. The BER and ER response to the change in fiber dispersion is similar to the change in fiber length. At any BER, the 5 • (3 • ) tilt MZM has the highest (lowest) dispersion tolerance. Also, the ER is largest for the 5 • tilt within the simulated dispersion range.
The energy-per-bit (E b ) of a modulator represents the electrical energy required to send an optical bit and is given as [35] where V TWE is the RF voltage across the TWE, and BR represents the bit rate. Considering a KP4-FEC threshold at the receiver for 5 km SMF transmission, the modulation speed is different for different tilt angles (Fig. 10). Z 0 at  So far in the system-level simulation study, the phase shifters are biased at -2.5 V and the voltage applied across the MZM arms are +/-2.5 V for |V π | = 5 V. Due to the non-linear phase-voltage relation of silicon PN phase shifters, -2.5 V bias doesn't bias the MZM at quadrature. Also, for different samples, the same bias point results in different phase points keeping the |V π | same with different L π . Also, 2.5 V push-pull drive results in different corresponding phase shifts in different samples. For comparison, the DC bias and the RF voltage are kept the same for all samples. The variation of BER with the RF drive voltage is shown in Fig. 13 for different tilt angles. The RF voltage across each TWE arm is varied from 1 V to 2.5 V for 3 km 40 Gbps SMF transmission. It can be observed from Fig. 13 that the sample with 5 • tilt has a much larger BER tolerance to the RF voltage amplitude compared to the other samples. The sample with 3 • tilt exhibits the worst performance followed by 0 • tilt. The BER improves as the RF voltage increases, as expected.
A comparison of the different phase shifter and modulator metrics for the four samples with different values of θ is given in Table 1. The best case is marked by 'blue' and the worst by 'red.' It can be seen that for the phase shifter performance, the 7 • tilt shows better phase shift and modulation efficiency whereas, lower absorption and higher 3 dB RC bandwidth of a lumped phase shifter is obtained for the 5 • tilt. In all the metrics, the 0 • tilt showed the worst performance. The best TWE and MZM performance is obtained for the 5 • tilt with the 3 • tilt representing the worst-case, followed by the sample with 0 • tilt. The sample with 5 • tilted implantation shows overall better performance compared to the other samples.

VI. CONCLUSION
A silicon PN phase shifter is process simulated, and the wafer tilt angles during dopant implantation are varied from 0 • to 7 • . The corresponding effect of the wafer tilts on the lattice damage, dopant concentration, and formation of dopant-defect clusters are investigated. The four samples with different wafer tilt angles are used in an MZM with traveling-wave architecture for on-off keying modulation. The TWE characteristics and high-speed characteristics for different samples are presented and discussed. The overall best performance is exhibited by the sample with 5 • tilt with 1.45× higher phase shift and modulation efficiency, 1.23× lower absorption, and 3.14× higher 3 dB bandwidth for lumped MZM at -5 V bias compared to 0 • tilt. For a 2.5 V push-pull operation at -2.5 V bias with a travelingwave arm, the sample with 5 • tilt has 2.29× (2.97×) higher EE bandwidth, 1.36× (1.84×) higher EO bandwidth, and 1.48× (1.53×) lower energy-per-bit compared to the sample with 0 • (3 • ) tilt. A 5 • tilt during implantation shows better performance compared to other samples with 0 • , 3 • , and 7 • tilt and has larger dispersion and drive voltage tolerance. Adjusting the wafer tilt during implantation can be used to tailor the carrier distribution across the waveguide resulting in enhanced phase shifter and modulator performance in pure silicon modulators.