A Lightweight and Real-time Hardware Architecture for Interference Detection and Mitigation of Time Synchronization Attacks Based on MLP Neural Networks

Stationary GPS receivers provide time information for critical infrastructures, such as phasor measurement units (PMUs), communication networks, and financial systems. Therefore, they are prone to a specific type of spoofing attack called time synchronization attack (TSA), which affects time information such as clock offset and clock drift. The receiver’s position remains constant during the attack; hence, attack detection and mitigation are challenging. Various countermeasures have been suggested to mitigate TSA effects. However, they are mainly software-based and are exploited to protect software implemented software-defined radios (SDRs). In this research, two hardware protection approaches are contributed for hardware-based SDRs based on multi-layer perceptron neural network (MLP NN) with sigmoid activation function. The most challenging part of MPL NN implementation is the activation function approximation. Therefore, two lightweight architectures are proposed for sigmoid function implementation. Linear approximation and look-up table (LA-LUT) and piece-wise linear approximation (PLA) are exploited for this task. The synthesis results demonstrate that the PLA approach has a slightly higher resource utilization in comparison to LA-LUT, while this method is more accurate. The mean squared error (MSE) of the PLA approach is equal to 0.019, which is 57% better than the LA-LUT approach with an MSE of 0.033. Furthermore, the designs are evaluated by two conventional types of TSA. According to the results, both methods are lightweight, and they only consume less than 0.3% of slice registers, 5% of slice LUTs, and 8% of DSP48E1Ss. Furthermore, they are real-time, and can mitigate the attack consequences; however, the PLA architecture has a better performance compared to LA-LUT.


I. INTRODUCTION
Nowadays, many crucial infrastructures, such as power grids [1], communication towers, and financial systems, depend on global positioning system (GPS) for acknowledging the accurate time [2]. GPS signals are weak at the earth's surface, and the signal structure is known publicly. Furthermore, civil GPS signals have no protection and correction mechanisms; therefore, an experienced adversary can easily alter the timing information of the target receivers [3]. The receivers in the mentioned infrastructures are stationary; thus, the adversary can place a receiver-spoofer device near the target receiver, transmitting a manipulated version of the signal with a slightly higher power [4]. The receiver-spoofer device extracts the code phase and Doppler frequency of the genuine signal; therefore, the resultant spoofing signal is very similar to the authentic one. This type of attack is known as time synchronization attack (TSA) and is considered an intermediate spoofing attack. Generally, TSA only manipulates the time information while the receiver position remains constant [5]. Due to the hidden nature of TSA and the similarity between the spoofing signal and the genuine one, almost all commercial GPS receivers can be spoofed easily [6].

A. ATTACK SCHEME
A commercial GPS receiver utilizes the GPS signals to obtain its position, velocity, and time, which is generally known as PVT solution. In stationary receivers, the position is constant, and velocity is zero; therefore, only the time information concerns the application. The GPS receivers exploit low-cost crystal oscillators to maintain the time, which cannot provide high accuracy time information. Regarding the clock oscillators behavior [7], the receiver clock has an offset in comparison to the GPS clock [8]: where is the receiver clock offset. The erroneous clock offset leads to incorrect receiver time. In critical infrastructures such as phasor measurement units (PMUs) and smart grids, accurate time information is employed for attaching timestamps to the voltage and current measurements of the network. Inaccurate timestamps can cause false alarms or misdeclaration of critical situations in the network, which results in disastrous and catastrophic incidents [9]. In the attack scheme, as shown in Fig. 1, the adversary receives the genuine signals of the in-sight satellites and alters the clock offset information of the receiver by modifying the pseudoranges of the satellites [5]. It can transmit the spoofing signal to the target receiver utilizing the spoofer part of the device. The higher power of the spoofing signal and its similarity to the authentic one convince the receiver to track the spoofed replica as the genuine signal. In this attack, manipulating the pseudoranges of all satellites results in the unchanged receiver position and modified clock offset, which leads to erroneous timestamps [6].

B. COUNTERMEASURES
As experienced spoofers seek new ways to create novel spoofing attacks, researchers contribute countermeasures to repulse the attack and mitigate its effects. The contributed researches can be classified into four main categories [10]: signal processing approaches [6], [11], [12], multi-antenna receivers [13]- [16], validations with other GNSS signals [17], [18], and cryptographic techniques [19], [20]. The cryptographic techniques require a structural update of the GPS signal; thus, it has not been operated practically on civil signals. Furthermore, the multi-antenna receivers and GNSS validations entail more pieces of equipment and increase the defense and protection costs. Signal processing is the most popular method due to its ease of use and minimum requirements, and a firmware update can convey the newest protection techniques to the receiver. This method suggests a dynamic solution to encounter the evolving nature of TSA by offering firmware updates. The GPS receivers generally include hardware components, which are not adaptable and updatable. In contrast, upgradability is one of the main features of the softwaredefined radios (SDRs); thus, the signal processing techniques are mainly implemented on SDRs [21]. However, the SDR approach cannot compete with the computational power of hardware receivers [22], and often their solutions are not real-time. Consequently, SDRs utilize programmable hardware resources to increase their computational resources and maintain upgradability. A novel classification of GNSS SDRs has been presented in [21] to classify SDRs based on their implementation approaches in four categories. The first category includes the prototyping softwares (P-SWs), where the baseband signals of the GNSS RF part are passed through the SW-implemented blocks: acquisition, tracking, and navigation solution. This prototyping approach is implemented in high-level programming applications, such a Matlab [8], [23] or Matlab and Simulink [24], LabVIEW [25], [26], and open-source tools [27]. Although this prototyping approach is fast and easy to exploit, it is not real-time most of the time [28], [29]. In the second category, known as the host PC method, the high-level programming framework is omitted, and the host PC mainly executes acquisition, tracking, and navigation blocks. Linux OS [30], graphical user interfaces (GUIs) [31], application programming interfaces (APIs) [32], GPU libraries [33], and C++ based software [34] are among the popular SDRs in this category. The host PC solutions can be real-time, non-real-time, or both. Note that elimination of high-level applications leads to less flexibility and exploitation ease. DSPs and embedded general purpose processors (GPPs) are included in the third category, along with a host PC to exhibit the results. The methods in this category utilize DSP accelerators [35] and bit-wise operations [36] to expedite the SDR procedure. An example of GPP exploitation for LSTMbased GNSS spoofing detection is also presented in [37]. DSP boards are the main realization tools in this category; thus, the implemented SDR is generally real-time. The last category includes the FPGA-based implementation, which has the least flexibility and utilization ease in the classification of [21]. In this approach, the required correlations are implemented in the FPGA platform, and the host PC determines the hardware configurations. Although FPGA implementations of SDR are the least flexible ones, the upgradability nature of SDR is still preserved. Therefore, even this type of SDR can receive firmware updates to protect the receiver against potential malicious attacks. Furthermore, these approaches can be executed in real-time [38], non-realtime [39], or both ways [40].

C. PAPER CONTRIBUTION
Although various types of SDRs have been proposed in the last few years, a few pieces of research have focused on the TSA mitigation techniques to develop a resilient receiver. Any protection against TSA in critical infrastructures should be real-time to provide high accuracy for the application. Protection procedures require dedicated computational resources to operate in real-time; hence, the P-SW and host PC approaches are not suitable for these implementations. In this research, an open-loop FPGA-based architecture of [41] is proposed to assist in filling this research gap. The suggested method in [41] is a TSA detection and mitigation approach utilizing an multi-layer perceptron neural network (MLP NN), which is classified in signal processing techniques and P-SW implementations. According to the reported results, the method has been outperformed the extended Kalman filter [42], Luenberger observer [43], and robust estimator [5]; therefore, it is a proper candidate for hardware implementation. The contributions of this research can be listed as follows: • The proposed algorithm in [41] is modified to reduce its sensitivity to approximation errors under attack conditions. • The defense algorithm can detect and mitigate TSAs which affect the clock offset and drift information. • Two high-precision approximations of sigmoid function are presented to provide the highest possible accuracy along with the least resource utilization. • The proposed hardware architecture has been designed as an open-loop extension; therefore, any compatible and configurable hardware SDR can employ its protection features. • The proposed designs are lightweight; therefore, they can be implemented on the FPGA-based SDRs easily. • The design exploits integers instead of floating-point numbers; hence, the computational overhead is decreased drastically. • The concurrent feature of FPGA implementation accelerates the protection algorithm execution. Therefore, the proposed architecture can be exploited in real-time, non-real-time, or both ways. This research is organized as follows: Section II surveys the sigmoid approximation methods and introduces the proposed approximations. Section III includes the proposed hardware architecture and design considerations, while section IV discusses overall performance evaluations and resource utilization. Furthermore, section IV assesses the performance of the architecture under the conditions of two TSA attacks. Eventually, section V concludes the research.

II. SIGMOID APPROXIMATION
Real-time execution and accuracy are among the main features of any protection algorithm. While the accuracy mainly depends on the innovations of the algorithm, the execution speed relies on the implementation platform. In neural networks (NNs), precision emerges from its design configurations, such as the number of layers and neurons, type of the activation function, and selected input features. The proper choice of implementation platforms based on the application has a significant impact on the execution time.
Since the NN structure provides the parallel implementation opportunity, a hardware implementation platform accelerates the execution time. So far, the hardware implementation has a significant advantage in comparison to software-based approaches; however, there is a considerable problem in hardware implementation of NNs: activation function approximation. Generally, NNs utilize sigmoid and hyperbolic tangent functions as activation functions. The direct implementation of these functions consumes a massive amount of hardware resources, and for deep (or large) NNs, it is almost impossible. Many pieces of research have been proposed various solutions to overcome this problem. The exploitation of look-up tables (LUTs) is the first and the most feasible solution. In this approach, a table of activation function samples is stored in memory, and a mapping mechanism maps each input to a specific row of the table. A lightweight LUT-based approximation has been proposed in [42], which is fast and does not consume valuable computational resources. However, its accuracy depends on the number of samples in the table.
As an alternative solution, coordinate rotational digital computer (CORDIC) algorithm, available in Xilinx LogiCORE IP core, provides an opportunity for direct implementation of sigmoid and hyperbolic tangent functions [44]. Although this IP core can implement trigonometric and hyperbolic functions, it consumes a considerable amount of computational resources. Various mathematical approximations have been employed to increase accuracy along with reasonable usage of hardware resources. In [45], a controlled approximation method based on the Taylor theorem is presented that bounds the approximation error by its Lagrange form. A high accuracy approximation method for sigmoid and hyperbolic tangent is contributed in [46], which utilizes the McLaurin series interpolation and Pade approximation, and its reconfigurable implementation is presented in [47]. Second-order and piecewise linear approximations (PLA) are also amongst popular solutions to approximate sigmoid function [48]. Exploiting floating-point numbers in hardware implementations leads to high computational resource utilization. Therefore, in the following subsections, two efficient approaches for fixed-point sigmoid implementation are proposed. The first proposed method is based on LUT and linear approximation combination (LA-LUT), while the second approach focuses on the PLA approach.

A. PROPOSED LA-LUT APPROACH
An efficient binary representation of the sigmoid function is proposed in [49]. However, the exploited sigmoid function in [41] has slight differences from the one presented in [49]. Since the first goal of this research is the efficient implementation of the proposed MPL NN of [41], the sigmoid function is modified to the binary version for further comparisons and sampling of LUT and linear approximation combination (LA-LUT). Consider the sigmoid function, exploited in [41], as (2): The exponent base e is replaced with 2 to represent binary numbers, variable x is substituted with n to demonstrate integers, and −2 is replaced by 2 −( 2 log (2) ) , as suggested in [49]: As mentioned in [49], a proper scaling factor 2 results in a function with integer outputs. Inspired by [48], k=10 is selected to scale the function: The effective input range of the sigmoid function represented in (2) is (-8, 8), and the output is in the range of (-1,1). After scaling, as shown in (4), the inputs are in the range of (-8192, 8192), and the function output range is (-1024, 1024). It should be noted that the inputs between two integers are rounded to the higher value, which causes a slight degradation in the approximation precision. This issue will be discussed in section IV. The binary scaled version of the sigmoid function presented in (4) is the basis of the proposed LA-LUT approach. Furthermore, the sigmoid function of (4) is symmetrical: Therefore, sampling the positive half is adequate to constitute the LA-LUT. For n< " ", the function can be approximated by a simple line: For n> " ", the function has been sampled to fulfill (7) based on the required precision for PMU application: In which, the estimation error ( ) is defined as: where n is an integer as function input, ( ) is the output of (4), and ( ) is the approximation result. In addition, the corresponding derivative error can be expressed as: The estimation error threshold has been selected to achieve an optimum balance between precision and resource usage, and it is obtained through a set of tests. Eventually, 110 samples of (4) fulfill (7). LA-LUT estimation, estimation errors, and corresponding derivative errors are exhibited in Fig. 2, and the mean squared error (MSE) of the LA-LUT approach is equal to 0.033.

B. PROPOSED PLA APPROACH
In the piece-wise linear approximation (PLA), ten lines have been exploited for sigmoid approximation, as shown in Table  I. Furthermore, the approximation results, such as comparison to the main function, estimation errors, and derivative errors, are demonstrated in Fig. 3. LA-LUT and PLA both have fulfilled the condition of (7), regarding Fig. 2 and Fig. 3. However, PLA has a lower ( ) and ( ) in comparison to LA-LUT. The MSE of the PLA approach is equal to 0.019, which is 57% better than the LA-LUT approach. Generally, LUT-based approaches are known for their fair resource usage in comparison to other methods. Although, a LUT with higher rows requires a more sophisticated mapping mechanism, which might affect the overall resource usage. In the next section, two hardware architectures for each method are proposed, which focus on reducing resource usage and increasing precision.

III. PROPOSED OPEN-LOOP ARCHITECTURE
In this section, an open-loop architecture for a three-layer MLP NN based on [41], is proposed and discussed in detail. The design aspects of MLP NN are also available in [41]. Furthermore, two sigmoid hardware realizations are presented regarding approximations of section II. In the third subsection, the detection and mitigation algorithm of [41] is modified to tolerate the inaccuracies caused by the hardware implementation and approximations.

A. FEEDFORWARD CALCULATIONS
The overall scheme of the proposed architecture is demonstrated in Fig. 4. The MLP NN presented in [41] has three input nodes that receive the clock offset samples = [ +1 +2 ]. They are passed through a MinMax unit which scales and offsets them. This unit operation can be expressed as: 6 In the next step, the first layer weights ( ) and biases ( ) should be applied to the unit output to form the stimulation of the activation functions: The results are passed through the hardware realization of sigmoid function: Afterward, each neuron output is multiplied in the corresponding weights ( ) and the second layer bias (b) is added to the result: Eventually, the results are passed through a reverse MinMax unit to achieve the predicted clock offset +3 : Note that the network is trained offline. Therefore, the first and second layer weights, biases and coefficients of MinMax units are predetermined and stored in LUTs of the proposed architecture.

B. PROPOSED ARCHITECTURES FOR SIGMOID HARDWRE REALIZATION
As mentioned earlier, one of the main goals of the proposed design is the utilization of fixed-point numbers. Therefore, the clock offset samples are scaled and rounded to maintain the network inputs in the range of [0, 1024). A 10-bit representation is adequate for the inputs; however, 16 bits have been employed to cover the probable overheads in the arithmetic procedures. Furthermore, if an arithmetic operation produces overhead bits, the result is truncated by eliminating the least significant bits to stay in the 16-bit frame. Obviously, the truncation causes precision degradation, which is discussed in the next section. Fig. 5 demonstrates the architecture of the proposed LA-LUT approximation based on the samples of (4). Similar to LUT implementations, 16-bit comparators have been exploited to specify the range of input. The first comparator ( 3 < "00 ) controls the multiplexer and determines the output is whether obtained by the LUT or linear approximation. Generally, a line can be defined by its slope and y-intercept. These parameters are extracted from Table I and stored in a LUT for implementing PLA. A shown in Fig. 6, the 16-bit comparators are also employed in PLA architecture to specify the corresponding line approximation and control the 16-bit multiplexers. In order to reduce the computational overhead, only a multiplier and an adder have been employed. The multiplier receives the stimulation of the sigmoid function, and the multiplexer determines the slope of the approximation line. The multiplication result is fed to the adder to be aggregated with the corresponding y-intercept to produce the approximation output. It should be noted that although the architecture of LA-LUT seems more straightforward than the PLA's, the high number of its comparators can consume a considerable amount of hardware resources. In section IV, the overall resource usages of these two architectures are compared to each other to determine the most suitable design.

C. DEFENSE ALGORITHM MODIFICATION
The estimated clock offset ( + ) has to be passed through a TSA detection algorithm to mitigate the probable effects of the attack. The algorithm proposed in [41] is based on high precision estimations of the software version of MLP NN. Achieving the required precision of [41] consumes a considerable amount of hardware resources, which cannot be implemented on the same chip as SDR. Therefore, trade-offs have to be made to reduce the computational resource usage while maintaining a suitable precision, such as sigmoid approximation, rounding, and truncation. The added inaccuracies affect the error-sensitive defense algorithm of [41]. Consequently, the algorithm is modified as presented in Fig. 7 to tolerate reasonable amounts of inaccuracies. According to [5], TSA has two main behaviors. The first type of TSA is identified by an abrupt change in clock offset information, while the second type includes a gradual modification of the clock offset information. The algorithm of [41] mainly relies on the estimation errors to detect and mitigate the attacks. In the modified version, the differences between the estimated and clock offset samples are also exploited to reduce the sensitivity. Furthermore, another correction coefficient called correction sum is added to mimic the behavior of added signal in the second type of TSA attack. Moreover, the attack declaration threshold can be determined by the application. Section IV demonstrates the evaluation

IV. Architecture Assessment
This section is dedicated to the performance evaluation and resource usage of the proposed architectures. Furthermore, the provided protection of each design is assessed through two typical TSAs. Both proposed architectures are implemented on Xilinx XC7Z020, which is the main chip of Xilinx ZedBoard. This chip is a popular choice for NN and SDR implementations; thus, many SDRs can employ the proposed designs based on their specifications and required precision. The evaluation dataset has been recorded on April 24, 2014, at Valiasr Street, Tehran, Iran. The sampling frequency of this stationary receiver has been equal to 5.7143 MHz, and the dataset duration is 32.5 seconds, which is adequate for the test. The reason behind the adequacy is the employment of a temperature-compensated crystal oscillator (TCXO) in the GPS receiver board. According to [7], TCXO is not an accurate crystal oscillator; thus, in normal conditions, the receiver has to update the clock and its offset in almost 20second periods. Regarding the clock update routine, a 32.5-second dataset contains all of the required information of clock offset behavior. The update behavior will be discussed more in upcoming subsections. In the first subsection, computational resource utilization is discussed, while the second and third subsections contain the evaluation results in the normal and under-attack conditions, respectively.

A. COMPUTATIONAL RESOURCE UTILIZATION
The proposed architectures are implemented by ISE Design Suite 14.2 and VHDL language. Three .txt files are employed to feed the clock offset information to the implemented architecture. These files are structured as: Third file 3 4 … In which d represents the clock offset information. The results are also stored as a .txt file. Matlab R2016a has been exploited to organize the input files and display the output of the implemented design. The sigmoid approximations are implemented based on the schemes presented in Figures 5 and 6, and the results of advanced HDL synthesis for a single neuron activation function are depicted in Fig. 8. According to this figure, the number of exploited elements in the LA-LUT architecture is more than PLA. However, the device utilization report determines which design has been consumed more resources. The overall design implementation is conducted based on Fig.  4. Therefore, three replicas of each activation function are generated to mimic the behavior of the sigmoid function. The advanced HDL synthesis results and device resource utilization are demonstrated in Tables II and III.  Regarding the results of Table II, the number of arithmetic operators is almost the same; however, PLA has relied more on arithmetic resources than LA-LUT. The main difference between PLA and LA-LUT is the utilization of registers, comparators, and multiplexers. The register utilization of PLA is almost three times higher than LA-LUT, which is a result of employing one adder and multiplier for the implementation of linear approximations. On the other hand, the LA-LUT mainly relies on comparators and multiplexers, which explains their high utilization amount in comparison to PLA. Fig. 8 also confirms this contrast between the two architectures.

B. PERFORMANCE OF THE ALGORITHM IN NORMAL CONDITIONS
The NN is trained by a generated dataset that has a similar slope as recorded data, and the training process is conducted offline via Matlab R2016a software. The slope and the behavior of the clock offset trend are highly dependent on the quality of the crystal oscillator. Therefore, it can be stated that as long as the oscillator is not changed, there is no need to retrain.
In the first step of design evaluation, the architecture and the modified algorithm are tested in normal conditions. The assessment results are demonstrated in Figures 9 and 10. The clock offset information of the recorded dataset is displayed on the top panel of both figures. The bottom panel demonstrates the NN estimation error. The clock offset trend has experienced an abrupt reduction near the 30th sample due to the receiver's clock update. In other words, when the clock offset passes a certain threshold, the receiver's clock is updated regarding the offset, and the clock offset is reduced based on the new clock. This routine is performed periodically to maintain the correct time and hold the clock offset in a predetermined range. Therefore, only one period is selected to evaluate both designs. According to Fig. 9, the PLA approach has been followed the clock offset trend accurately. However, the LA-LUT approximation has slightly deviated from the authentic trend around the 40th sample, which caused an error near 15 .
Although this deviation is under the attack detection threshold, it certainly affects the prediction accuracy and overall root mean square errors (RMSEs), as demonstrated in the second column of Table IV. In normal conditions, the PLA approach has the advantage of accuracy and precision. In the next subsection, both methods will be evaluated in the presence of two TSAs.

C. EFFICIENCY OF DESIGN IN PRESENCE OF TSA
According to [5], two types of TSA are more likely to happen. The first type is identified by an abrupt modification in the clock offset trend, while the second type of TSA consists of gradual alterations. The attacks are generated by altering the pseudoranges of each in-sight satellite. Therefore, the position of the receiver remains intact, but the clock offset information is changed. The detection and mitigation performance of the PLA and LA-LUT approaches are exhibited in Fig. 11 in the presence of the first type of TSA. An abrupt change in the top panel is observed around the 10th sample, which is an indication of the attack type. The bottom panel demonstrates the NN estimation error . It can be observed that PLA and LA-LUT have mitigated the effects of the attack. According to Figures 2 and  3, the precision of PLA sigmoid approximation is higher than LA-LUT; thus, the PLA approach has higher accuracy compared to the LA-LUT, which can be observed in the bottom panel. It should be noted that although the receiver's clock update is similar to the first type of TSA, the algorithm has stored all of the correction coefficients and prevented the network from misdetection of the situation. The same conclusion can be stated for attack detection in normal conditions. In the second type of TSA, the modifications are made in the clock offset trend slowly and gradually; therefore, attack detection and mitigation are very challenging. With a degradation in accuracy and precision of MLP NN, the algorithm presented in [41] has not been able to mitigate the effects of the attack. Therefore, the differentiations have been exploited to reduce the sensitivity to approximation errors, as stated in Fig. 7. This factor has significantly reduced the sensitivity to the point that both LA-LUT and PLA have similar performances in the presence of the second type of TSA, as shown in Fig. 12. The RMSE of each design is compared to the software implemented approach of [41] and an MLP NN with rounded and truncated weights and biases in Table IV. These comparisons are made to demonstrate the effects of roundings, truncations, and sigmoid function approximations. According to the table, roundings and truncations of weights and biases have almost doubled the RMSEs in comparison to [41]. The proposed hardware architectures based on clock offset monitoring are the first ones of their kind; thus, there is no other hardware implementation to compare the results. The RMSEs of the PLA approach are close to the rounded and truncated version. Therefore, it can be concluded that the excess error is mainly caused by rounding and truncation of the weights and biases of the network. On the other hand, although the RMSE of LA-LUT is equal to PLA's in the second type of attack, it has higher RMSEs compared to PLA in two other cases.

V. CONCLUSION
GPS signals provide position, velocity, and time information or PVT solutions for various users. The position and velocity information is vital for vehicles' navigation; however, the stationary users have a different implication. Considering the fact that the position of stationary receivers is constant and their velocity is zero, the time information has a high significance in this type of receiver. These receivers are generally exploited in critical infrastructures for accurate time measurement; therefore, any interference can result in disastrous incidents. One of these intentional insecurities is the Time synchronization attack which manipulates the clock offset information of the receivers while keeping the receiver's position constant. Although various software-based countermeasures have been suggested to mitigate the attack consequences, only a few hardware-based protection algorithms are proposed for FPGA-based SDRs. Therefore, this research contributed two different hardware architectures to secure the receivers against TSAs. The first proposed design is based on LUTs, which are very popular for sigmoid approximation, and the second is a high precision PLA. Both architectures are implemented on Xilinx ZedBoard with different resource exploitations. The LA-LUT design has lower precision in comparison to PLA and consumes more logic resources, such as multiplexers and comparators. On the other hand, PLA is mostly arithmeticbased and consumes more slices of DSP48E1S; thus, it is 57% more accurate than LA-LUT. Both designs are lightweight and real-time, and they can be selected for SDRs' protection based on the accuracy or resource utilization priorities. Concerning the nature of TSA, the proposed designs can mitigate the attack effects on the clock offset information. The knowledge of MLP NN and the modified detection and mitigation algorithm is the basis of this method. However, the network performance should be studied more with new attacks. The new ways of TSA generation will be studied as future works to create maximum protection against TSAs and timing threats. Furthermore, the possibility of applying new structures of NN to mitigate the attack effects will be investigated in the next steps of this research.