Common-Mode Voltage Suppression Strategy Based on Fast MPC for a Five-Level Nested Neutral Point Piloted Converter

This paper, regarding a five-level nested neutral point piloted (NNPP) converter as the research object, analyzes the working mechanism of an NNPP five-level converter and determines the switching commutation circuit and switching principles. To solve the problem of common-mode voltage (CMV) in NNPP five-level converters, a control strategy based on fast model predictive control (MPC) is proposed to effectively suppress common-mode voltage. The control method proposed in this paper is divided into two main parts. First, 19 zero common-mode voltage (ZCMV) vectors are selected from 125 voltage vectors, and 19 ZCMV vectors are optimized to select the best ZCMV vector. Next, according to the switching principles, the effective switching combinations are selected as the effective candidate control set, and proper switching combinations of the optimal ZCMV vector are determined. The effectiveness and validity of the proposed suppression strategy based on fast MPC in terms of the steady state and dynamic performance is confirmed by simulation and experimental results of the five-level NNPP converter.


I. INTRODUCTION
Multilevel converters have been widely used in high-voltage high-power and alternating current speed control systems. However, limited by the withstand voltage level of power devices, three-level converters based on diode clamping will be limited in practical industrial applications. Therefore, higher-level converters are needed to improve the output voltage. Five-level converters have become a research hotspot in multilevel converters due to their advantages of multiple topologies, fewer components and higher cost performance. The traditional five-level topologies include neutral-point clamped five-level (NPC-5L) converters [1], flying-capacitor five-level (FC-5L) converters [2], [3] and cascaded H-bridge five-level (CHB-5L) converters [4].
The existence of common-mode voltage (CMV) in the multilevel converters will produce high amplitude shaft voltages and bearing currents, which will shorten the service The associate editor coordinating the review of this manuscript and approving it for publication was Zhehan Yi . life of the motor. In addition, the CMV can also produce high-order harmonics, increase the active and reactive power losses, and affect the power quality [5]. In the literature, various filters for eliminating the CMV of the inverter have been reported, which can produce a CMV with the same amplitude and opposite phase as the output voltage to suppress the CMV [6], [7]. For the CMV of multilevel inverters, various methods of using multiple space vector pulse width modulation to reduce the CMV can be found in many references [8]- [15]. In [8], a near-state pulse width modulation method was proposed to reduce the CMV of a three-phase pulse width modulation (PWM) inverter. Compared with traditional PWM modulation, the proposed the large vectors, medium vectors, and zero large vectors technology through large, medium and zero vectors can reduce the CMV that causes leakage current [9]. The modulation method of eliminating CMV for multilevel inverters is generally based on the principle of three-zero CMV. Compared with the existing PWM, a method based on carrier pulse width modulation for optimal output current ripple can effectively reduce the current ripple and total harmonic distortion [10]. Phase-shifted sinusoidal pulse width modulation can significantly reduce CMV compared with traditional SPWM [11]. Aiming at the problem of common-mode spikes in CMV reduction PWM, a method of the injected zero-sequence voltage is proposed to eliminate CMV spikes [12]. A CMV reduction PWM, which can limit the CMV of the three-level neutral point clamped inverter to less than one-sixth of the dc-link voltage, is researched in reference [13]. For the CMV of three-level converters, a double modulation wave carrier-based PWM strategy is proposed in [14]. The work reports a modified T-structured threelevel inverter that can eliminate CMV, which is considered in [15]. In reference [16], the PWM scheme is adopted to eliminate the CMV of the five-level inverter, and the method has been improved in [17]. In reference [18], a novel SVPWM algorithm based on line voltage coordinates are proposed to address the shortcomings of the traditional algorithm, and the CMV of the five-level active neutral-point-clamped inverter is suppressed by selecting the appropriate switching state. Furthermore, ZCMV vectors can be used to eliminate CMV, presenting a space vector pulse width modulation (SVPWM) technique, which eliminates the CMV of a five-level active neutral-point clamped inverter by using the ZCMV vectors in [19]. However, considering that the above PWM methods are applied to multilevel inverters above three levels, the complexity and computational amount are increased due to the sharp increase in the number of space voltage vectors.
In recent years, the model predictive control (MPC) [20], [21] provides a new solution to the CMV problem due to its advantages such as simple structure, flexible control and multi-objective control. At present, MPC has been used to suppress CMV in some references [22]- [26]. References [22] and [23] propose an improved MPC strategy that can significantly reduce the CMV for voltage-source converters but increase the THD of the switching loss and current waveform. In the MPC strategy proposed in [24], four nonzero vectors are used for optimization in each cycle to suppress the CMV and reduce the switching frequency and calculation amount. Reference [25] proposes a double-vector MPC strategy to reduce CMV and current ripples for a threelevel T-type converter. Reference [26] uses a model predictive control method combined with ZCMV vectors to eliminate the CMV of a five-level active neutral-point clamped inverter. When the output level of the inverter increases, the amount of calculation increases, which increases the operating burden of the MPC method. Therefore, it is necessary to reduce the candidate control set of MPC and reduce the amount of system calculation.
Recently, a nested neutral point piloted five-level (NNPP-5L) converter is derived from the three-level neutralpoint piloted (NPP) topology. The NNPP converter does not need extensive clamping devices, and the power switching voltage stress is equal and has the characteristics of high-power density and high efficiency [27]. There is no MPC research on CMV suppression in five-level NNPP converters at present. This paper proposes a fast MPC control algorithm based on the switching principles. The contributions of this paper are as follows: 1) In order to reduce the CMV, 19 space voltage vectors are selected from 125 space voltage vectors, and all switch combinations corresponding to the 19 voltage vectors are the candidate control set. 2) In order to further reduce the candidate control set of the switch combinations, a two-step prediction is adopted for the fast MPC control strategy based on the switching principles. 3) According to the control strategy, the cost function is designed in two steps, which reduces the number of weighting factors to a certain extent. This paper is organized as follows. Section II presents the operating principle and switching combination principles of the five-level converter. The conclusion that switching principle at different time is obtained. In Section III, the selection of zero CMV and determination of the control set are obtained. Section IV proposes a fast MPC algorithm based on the switching principles to reduce the common-mode voltage. In Section V, the simulation and experimental results are presented. Finally, Section VI concludes this paper.

II. OPERATING PRINCIPLE AND SWITCHING PRINCIPLE OF THE FIVE-LEVEL NNPP CONVERTER A. ANALYSIS OF OPERATING PRINCIPLE
The main circuit topology of the three-phase five-level NNPP converter is shown in Fig. 1.
Taking the single-phase topology as an example, i xo , i cfx1 , i cfx2 and i x are the neutral point currents on the dc-link, two flying capacitor currents and the output phase current. If the total voltage on the dc-link bus is 4E, the voltages of dc-link capacitors C 1 and C 2 are 2E, and the voltages of flying capacitors C fx1 and C fx2 are both E. Taking the neutral point of the dc-link as a reference, the five levels are -2E, -E, 0, E, 2E, which are represented by numbers 0, 1, 2, 3 and 4. There are nine different switch combinations for the five levels, which can be expressed as (S x11 S x21 S x13 S x14 S x23 S x24 S x15 S x25 ), where x represents different phases (x = a, b, c). The switches S x11 , S x12 , S x15 and S x16 , S x21 , S x22 , S x25 and S x26 cannot be turned on at the same time, and the switches S x11 (S x12 ) and S x14 , S x15 (S x16 ) and S x13 , S x21 (S x22 ) and S x24 , S x25 VOLUME 9, 2021 (S x26 ) and S x23 are complementary, respectively. The specific switch combinations are shown in Table 1 [28], [29], where 1 and 0 indicate the turn-on and off states, respectively.
As Table 1 shows, when the output level is E, there are two switch combination s A 2 and A 3 , which have the opposite effects on the higher flying capacitor voltage. Among these combinations, the effect of switch combination A 3 on the higher flying capacitor voltage and the neutral point voltage of the dc-link is the same. When the output level is 0, there are three switch combinations A 4 , A 5 and A 6 , among which switch combinations A 4 and A 6 have opposite influences on the upper and lower flying capacitor voltages, while switch combination A 5 only works on the neutral point voltage of the dc-link.
When the output level is -E, corresponding to switch combinations A 7 and A 8 , the effect of switch combinations A 7 and A 8 on the lower flying capacitor voltage is opposite, and the function of A 8 on lower flying capacitor voltage and the neutral point voltage of the dc-link is different. Therefore, even if the output level is the same, the charging and discharging characteristics of the switch device are different when different switch combinations are selected.
Assuming that the output current i x is positive, when the output level is -E, switch combination A 7 discharges the lower flying capacitor voltage, while A 8 charges the lower flying capacitor voltage and discharges the neutral point voltage of the dc-link. Similarly, when the output level is 0, switch combination A 4 charges the upper and lower flying capacitor voltages, switch A 6 discharges the voltage of the upper and lower flying capacitors, and A 5 discharges only the neutral point voltage of the dc-link. Therefore, considering that there are many switching states in the five-level converter, a switch combination may affect both the voltage of the flying capacitor and the neutral point voltage of the dc-link, so there is coupling between the voltage of the flying capacitor and the neutral point voltage of the dc-link, which makes the balance of the capacitor voltage more difficult to control.
In addition, the switching between different switch combinations will produce different levels. To avoid unreasonable level jumps, it is necessary to select the switch between adjacent levels corresponding to the switching principle. Taking the switching between the 0 and -E levels as an example, there are three redundant switch combinations in the 0 level and two redundant switch combinations in the -E level, so there are six switching modes between 0 and -E. If switch combinations A 4 and A 8 are selected as circuit mappings for the 0 level and -E level, respectively, switch combinations A 4 and A 8 are selected, and a certain dead zone is added. When i x >0, the mapping circuit is 10100101(0) switched to 00110101(-E) through 00100101 (-E), as shown in loop F 1 , switch S x13 is normally on, and switches S x14 and S x25 (S x26 ) flow through the antiparallel diode. When i x <0, the mapping circuit is 10100101 (0) switched to 00110101(-E) through 00100101(0), as shown in loop F 2 , switches S x25 (S x26 ) are normally on, and switches S x11 (S x12 ) flow through the antiparallel diode. According to the above analysis, when combinations A 4 and A 8 are switched, there is no level jump, and the level is limited between 0 and -E. However, if the 0 level and -E level, respectively, select combinations A 6 and A 8 as circuit mapping, that is, switch between combinations A 6 and A 8 , and add a certain dead zone. When i x >0, the mapping circuit is 01011010(0) switched to 00110101(-E) through 00010000(-2E), as shown in loop F 3 , and switches S x15 (S x16 ) and S x25 (S x26 ) both flow through the antiparallel diode. When i x <0, the mapping circuit is 01011010(0) switched to 00110101(-E) through 00010000(E), as shown in loop F 4 , switch S x14 normally conducts, and switches S x13 and S x21 (S x22 ) flow through the antiparallel diode. When switching between combinations A 6 and A 8 , there is a jump between level 0 and -2E or E to -E. The specific switching loop is represented in Fig. 2.

B. PRINCIPLES OF SWITCHING COMBINATION
The analysis method of Fig. 2 is used to analyze the remaining switching circuits. For example, when switching between level E and level 0, there are six switching modes. When the switch combination is A 2 and A 4 , A 2 and A 5 , A 3 and A 5 , A 3 and A 6 , a total of four kinds of switching modes, at this time, there is no level jump between level E and level 0. However, when switching between A 2 and A 6 or between A 3 and A 4 , there is a -E or 2E level jump between the two modes. The voltage stress of the switching device will be increased if the switching levels jump. To avoid the level jump and reduce the loss of switching devices, in the case of meeting the switching principle, that is, in the process of switching, the switch is on and off only once.
The switching mode between adjacent levels in the switch combination can be analyzed, and the switching principles of the switch combinations for a single-phase five-level NNPP converter at different times under different conditions can be derived, as shown in Table 2. Here, the effective switch combinations corresponding to switch combination A 5 are defined as A 2 A 4 A 5 A 7 , so the maximum number of effective switch combinations for each phase is not more than 4 and the maximum number of three-phase effective switch combinations does not exceed 64.

III. SELECTION OF ZCMV AND DETERMINATION OF THE CONTROL SET
The five-level NNPP converter has five level states for each phase, which are represented by 0, 1, 2, 3, and 4, so there are 125 level states in the three phases. The spatial voltage vector distribution composed of 125 level states is shown in Fig. 3. Meanwhile, since the five level states of each phase correspond to nine switch combinations and a total of 729 switch combinations for three phases, there are 729 different mapping types when the switch states are mapped to the hardware circuit. If the traditional MPC is used, the difficulty of selecting the switch state and switch combination is greatly increased.

A. SELECTION OF ZERO COMMON MODE VOLTAGE VECTOR
To solve the problem of common mode voltage in a fivelevel NNPP inverter, the optimal ZCMV vectors are selected based on the traditional space voltage vectors. According to the fast MPC control strategy proposed in this paper, namely, according to the switching principle, all possible switch combinations corresponding to the optimal ZCMV vector are taken as the control set and output the optimal switch combination according to the cost function. This method can realize the balance of dc-link capacitance and flying capacitor voltage and curb the common mode voltage. The method does not need extensive function calculations, which reduces the number of iterations and is easy to implement flexibly.
From the NNPP main circuit topology in Fig. 1, the threephase five-level output voltage can be expressed as: where the common-mode voltage V no, which is the voltage between the load neutral point and reference point potential, can be described as: where V ao , V bo and V co are the three-phase output voltages of the inverter. Assuming that the dc-link voltage is V dc , the switch state is marked as S x (x = a, b, c). The five level states of the three-phase output can be expressed as follows: According to (3), the relationship between the three-phase output voltage and the switching state can be deduced as: Therefore, combining (2) and (4) can obtain the relationship between the common mode voltage and switching states: The five-level NNPP inverter output voltage is expressed by the DC-link voltage, which can output five levels: -V dc /2, -V dc /4, 0, V dc /4, and V dc /2. To suppress the common-mode voltage, space voltage vectors with ZCMV can be applied in the control. By substituting all possible switching states of the three phases into formula (5), 19 ZCMV vectors can be obtained. As shown in Fig. 4, 19 ZCMV vectors are selected from 125 space voltage vectors to suppress common-mode voltage, greatly reducing the number of control vectors.

B. CONTROL SET BASED ON SWITCHING PRINCIPLE
The five-level NNPP inverter has many switching states. Because the five level states of the three-phase output correspond to 729 switch combinations, the traditional MPC will make the calculation more complicated. Based on the principle of switch combination, a fast MPC control strategy is proposed to reduce the computational burden and avoid unnecessary level jumps. As seen from Table 2, if the switch combination corresponding to the output level at k is known, all possible switch combinations at k + 1 can be obtained. There are nine possible switch combinations at k, and the maximum number of switch combinations corresponding to each switch combination at k +1 is not more than 4. To further reduce the number of switch combinations at k + 1, based on the switch combination corresponding to the known optimal ZCMV vector and combined with the principle of switching transitions, the number of switch combinations can be further reduced. Taking the ZCMV vector V 5 (123) as an example, the actual corresponding switch combinations are shown in Fig. 5.
If the switching principle is considered, as shown in Fig. 6, suppose at time k, the switch combinations of phase a are A 4 , those of phase b are A 2 , and those of phase c are A 8 . Table 2 shows that the switch combinations of phase a should be A 2 , A 4 , A 5 , and A 8 at time k + 1. Similarly, the switch combinations of phase b should be A 1 , A 2 , A 4 , and A 5 at time k + 1 and those of phase c should be A 4 , A 5 , A 8 , and A 9 at time k + 1. Fig. 5 shows that the actual switch combinations of phase a for the ZCMV vector are A 7 and A 8 ,  the actual switch combinations of phase b are A 4 , A 5 and A 6 , and the actual switch combinations of phase c are A 2 and A 3 . According to the above analysis, switch combination A 8 not only satisfies the switching principle of phase a but also satisfies the actual switch combination, so A 8 is regarded as the effective switch combination of phase a at time k + 1. Similarly, A 4 and A 5 satisfy both the switching principle of phase b and the actual switch combinations, so A 4 and A 5 are regarded as the effective switch combinations of phase b at time k + 1. In particular, A 2 and A 3 do not satisfy the switching principle but are the actual switch combinations of ZCMV vector V 5 (123) in phase c. In this case, the actual switch combinations A 2 and A 3 are selected as the effective switch combinations of phase c at time k +1. According to the above derivation process, the effective switch combinations of the ZCMV vector V 5 (123) under all circumstances at time k + 1 can be obtained, as shown in Table 3. These effective switch combinations will be used as a candidate control set to participate in MPC control, and the optimal switch combination will be output. Table 3 shows that at time k + 1, phase a has 1 or 2 switch combinations, phase b has 2 or 3 switch combinations, and phase c has 1 or 2 switch combinations. Therefore, there are at most 12 switch combinations and at least 2 switch combinations for three phases, compared with Table 2, which reduces the control set of MPC to a certain extent and reduces the amount of calculation.

IV. FAST MPC BASED ON SWITCHING PRINCIPLE A. MATHEMATICAL MODEL OF PREDICTIVE CONTROL
Aiming at eliminating common-mode voltage, keeping capacitor voltage balance and reducing the calculation burden of the five-level NNPP inverter, a fast MPC control strategy based on the switching principle is proposed, that is, according to the switching principles at k + 1, to select effective switch combinations of the ZCMV vector as the candidate control set and output the optimal switch combination that minimizes the cost function.
According to the topology of the five-level converter, the relationship between the phase voltage and the switching states is as follows: From the balance mechanism of the flying capacitor and the dc-link capacitor voltage, substituting V c1 = 2E, V c2 = 2E, V cfx1 = E, and V cfx2 = E into (6), the following equation can be obtained: Under RL load, continuous-time model of load current is Introduce the sampling period T s into (8) and adopt the forward Euler approximation: The discrete-time model of the output currents in the αβ coordinate system is Similarly, the continuous-time models of the flying capacitor voltage and the dc-link capacitor voltage are (11) and (12), respectively: Using the forward Euler approximation for (11) and (12) and introducing the sampling time T s , the discrete-time models of the flying capacitor voltage and the dc-link capacitor voltage can be predicted as (13) and (14): Particularly, there may be a one-beat delay in the predictive control when the algorithm is implemented. To solve this problem, two-step prediction can be adopted to compensate for which value of k +1 is taken as the feedback value of k +2, and the value of k + 2 is substituted into the cost function to obtain the optimal switch combination.
The reference current i * at k + 2 can be estimated as where i * (k+2), i * (k), i * (k-1), and i * (k-2) are the current reference values at k + 2, k, k-1, and k-2, respectively. In the αβ coordinate system, the discrete-time model of the output current at instant k + 2 is as follows: At instant k + 1, the current passing through the flying capacitors and the dc-link capacitors can be expressed as The discrete-time models of the flying capacitor voltage and the dc-link capacitor voltage at instant k +2 are expressed as

B. THE DESIGN OF THE COST FUNCTION
The weight coefficients in the cost function require repeated trial and error, which is relatively cumbersome. In traditional current prediction control, it is necessary to achieve current tracking and balance the dc-link capacitor voltage and flying VOLUME 9, 2021 capacitor voltage at the same time. Therefore, the cost function is usually. (21) where i * α(k+2) and i * β(k+2) are the values of the reference current located in the αβ coordinate at moment k + 2. λ 1 and λ 2 are the weight coefficients of the dc-link capacitor voltage and flying capacitor voltage in the cost function, respectively. The reference value V cref of the flying capacitor voltage for each phase is V dc /4. To reduce the number of weight coefficients in the cost function, the MPC control strategy based on the switching principle proposed in this paper can be divided into two stages. The first stage is in the current predictive control. Nineteen ZCMV vectors need to be substituted into the cost function g 1 for optimization in each sampling period, and the candidate voltage vector with the minimum value of the cost function g 1 is selected as the optimal voltage vector to realize fast current tracking. Therefore, the cost function g 1 can be designed as: To make the system have good dynamic and steady-state performance, while considering the balance of the flying capacitor voltage and the dc-link capacitor voltage, all the switch combinations of the optimal voltage vector are substituted into the cost function g 2 in the second stage, and the switch combination with the minimum cost function g 2 is output, reducing the number of weighting coefficients in the cost function to a certain extent. The cost function g 2 can be designed as where the weight coefficient λ is 0.5, and the reference value of the flying capacitor voltage for each phase is V dc /4.

C. IMPLEMENTATION STEPS
The implementation process of the fast MPC strategy proposed in this paper to suppress common-mode voltage is divided into two main stages, as shown in Fig. 7.
In the first stage, the instant reference currents i * α (k+2) and i * β (k+2) are predicted by using Lagrange extrapolation. Second, the load current and ZCMV vectors at k + 1 are predicted, and load currents i α (k+2) and i β (k+2) are predicted in two steps. Then, the optimal ZCMV vector can be obtained from the cost function g 1 . In the second stage, the candidate control set of switch combinations is obtained by combining the optimal voltage vector with Tables 2 and 3, the predicted values at k + 2 of the dc-link capacitor voltage and flying capacitor voltage are predicted in two steps, and the optimal output switch combinations are obtained by the cost function g 2 . The flow chart of the control algorithm is shown in Fig. 8.

A. SIMULATION PARAMETERS
To verify the feasibility of the theory and control strategy proposed above, the simulation of a five-level NNPP inverter was built according to the circuit structure in Fig. 1. The main parameters of the simulation are shown in Table 4. Fig. 9 and Fig. 10 show the simulation results of the dc-link capacitor voltage, flying capacitor voltage and common-mode voltage when the load resistance is 10 . The traditional MPC control without reducing the common-mode voltage and the fast MPC control with common-mode voltage VOLUME 9, 2021  suppression proposed in this paper are compared in the steady state.

B. STEADY-STATE ANALYSIS
By comparing the line voltage and phase voltage of traditional MPC control strategy, the line voltage and phase voltage proposed in this paper have also been effectively improved. As shown in Fig. 10(a) and (b), the waveforms of the line voltage and phase voltage are smoother and higher in quality. Traditional MPC and the MPC strategy proposed in this paper stabilize the upper and lower capacitor voltage of the dc-link at approximately 260 V (V dc /2), but the fluctuation range of the dc-link capacitor voltage in Fig. 10(d) is within 0.5 V. Compared with the fluctuation range of 2 V in Fig. 9(d), the proposed control strategy can better suppress the fluctuation of the bus capacitance voltage. Likewise, the three-phase five-level NNPP inverter has upper and lower flying capacitors, which can be charged and discharged frequently during the control period. As shown in Fig. 9(e) and Fig. 10(e), the voltage of the upper and lower flying capacitors is stable at approximately 130 V (V dc /4).
In addition, by comparing the waveforms of the commonmode voltage in Fig. 9(f) and Fig. 10(f), Fig. 9(f) shows that when the traditional MPC is adopted, the system has a larger common-mode voltage, with a maximum amplitude of up to 173 V (V dc /3). Fig. 10(f) shows that the fast MPC proposed in this paper can effectively suppress the common-mode voltage of the system, and the common-mode  voltage can be suppressed within the range of upper and lower 3 V.
In order to verify the robustness and stability of the proposed control strategy under steady-state, the output currents simulation waveforms with the 40% overestimated and 40% underestimated inductance as well as the correct resistance are shown in Fig. 11 and Fig. 12, respectively. It can be obtained that the three-phase output current fluctuations under the two control strategies are small when the inductance changes, and the robustness and stability of the proposed control strategy are verified. In addition, comparing with the traditional MPC control strategy, the proposed fast MPC in this paper not only has good robustness and stability, but also reduces the control candidate set and suppresses the commonmode voltage.

C. DYNAMIC -STATE ANALYSIS
The dynamic response test is carried out to further verify the effectiveness of the proposed control strategy, the simulation waveforms of the system are shown in Fig. 13 and Fig. 14.
Under the different control strategies and load conditions, both control strategies stabilize the capacitor voltage on the dc-link at 260 V (V dc /2). After the current amplitude increases at t = 0.05 s, the capacitor voltage can be kept stable, and the neutral-point potential can be balanced. At the same time, the conventional MPC control strategy maintains a large  fluctuation range of common-mode voltage with a maximum amplitude of 175 V under different load conditions. However, the proposed fast MPC strategy maintains the common-mode voltage within the range of upper and lower 3 V under different load conditions, as shown in Fig. 14(d), indicating that the CMV is well suppressed.  In order to verify the robustness and stability of the proposed control strategy under dynamic-state, the output currents simulation waveforms with the 40% overestimated and 40% underestimated inductance as well as the correct resistance are shown in Fig. 15 and Fig. 16. The proposed control strategy still has good robustness and stability under dynamic-state, comparing the three-phase output current fluctuations under the two MPC strategies.

D. EXPERIMENTAL RESULTS
To further verify the traditional MPC control strategy and the proposed fast MPC strategy, an experimental system of a five-level NNPP converter was established. The power switches used in the experimental system are Infineon FF100R12RT4 switches. The proposed fast MPC algorithm is implemented in the control system of the digital signal processor (TMS320F28335) and the field programmable gate The steady-state experimental waveforms of traditional MPC and fast MPC are shown in Figs. 17 and 18, respectively. The reference frequency is 50Hz, the dc-link voltage is 200V and the load resistance is 10 . It can be obtained that the experimental waveforms generated by two strategies coincide with the simulation results. No matter the traditional MPC control or the fast MPC control, the voltages of flying capacitor and the dc-link capacitor are balanced. The flying capacitor voltage are well controlled around the value 50 V. The dc-link capacitor voltages are well controlled around the value 100 V. Furthermore, the common-mode voltage of the fast MPC strategy is obviously less than that of the traditional MPC strategy. The common-mode voltage of the traditional MPC strategy is about 50V, but the common-mode voltage of the fast MPC strategy is lower than 5V. It can be summarized from the steady-state experimental results shown in Figs. 17 and 18 that the proposed fast MPC algorithm has good steady-state performance and capacity in reducing the CMV.
Figs. 19 and 20 show the dynamic experimental results of the load currents changing suddenly. Fig. 19(a) and Fig. 20(a) are the experimental waveforms of common-mode voltage, phase voltage, phase-a and phase-b output currents under the two control strategies, respectively. Fig. 19(b) and Fig. 20(b) are the experimental waveforms of the flying capacitor  voltage, dc-link capacitor voltages and line voltage under the two control strategies. Fig. 19 and Fig. 20 show that, the phase currents of the two control strategies track well before and after the load mutation. The voltage of the flying capacitor is maintained at 130V, the voltage of the dc-link capacitor is maintained at 260V, and the voltages of the flying capacitor and the dc-link capacitor are balanced. However, the common-mode voltage in Fig. 19 fluctuates between up and down 50V before and after the load mutation, while the common-mode voltage in Fig. 20 does not exceed 1V before the load mutation, and remains within 2V after the load mutation. Similarly, before and after the sudden change of load, the waveform quality of the phase voltage and line voltage in Fig. 20 is obviously better than that of phase voltage and line voltage in Fig. 19.
According to the experimental results of the two control strategies, the fast MPC method based on the switching principle can keep the dc-link capacitor voltages and flying capacitor voltages stable, and has good performance with almost no change in the common-mode voltage under the steady-state and dynamic-state.

VI. CONCLUSION
A fast MPC method based on the switching principle is proposed to solve the problem of the common-mode voltage of the 5 L-NNPP inverter and realize the balance of the dc-link capacitor voltage and flying capacitor voltage. The working mechanism, switching states and switching transitions of the converter are given. The common-mode voltage is suppressed by selecting 19 ZCMV vectors, and the fast MPC candidate control set is reduced according to the switching principle, which greatly reduces the computational burden. In addition, the fast MPC strategy based on the switching principle adopts two-step control, which can reduce the number of weight coefficients and simultaneously realize that the voltage ripples of the common-mode voltage, dc-link capacitor voltage and flying capacitor voltage are controlled very well within a small range. He is currently a Professor of electrical engineering with Anhui University, China. His research interests include control of electric vehicle with wheel hub motor and power quality control.
MINGLI ZHOU was born in Anhui, China, in 1997. He received the B.S. degree in electrical engineering and automation from the School of Control Engineering, Chengdu University of Information Technology, Chengdu, China, in 2020. He is currently pursuing the master's degree in power electronics and power drives with the Laboratory of Electrical Engineering, University of Shanghai for Science and Technology, Shanghai, China. His current research interest includes multi-level converters. VOLUME 9, 2021