A Bidirectional Isolated Integrated AC–DC Converter Based on an Interleaved 3-Level T-Type Power Converters

This paper presents an integrated single-phase bidirectional ac–dc converter based on a dual-active-bridge (DAB) topology. The primary side is based on a multi-state switching cell (MSSC) with a T-type (TNPC) cell, which is composed of two three-level interleaved legs and coupled inductor, while the secondary side is a single-phase full-bridge (FB). Moreover, a comparative analysis between an isolated ac–dc converter with a neutral point clamped (NPC) converter on the primary side is presented. The basic converter operating principles and experimental results of a 850 W prototype are presented in order to validate the theoretical analysis. The control strategy is implemented on the TMS320F28379D DSP. The proposed topology achieves a maximum efficiency of 91.40% at 300 W output power, and 89.40% at rated power. From the experimental results, it can be stated that the converter based on the T-type topology is more efficient than the structure based on the NPC.


I. INTRODUCTION
In the last decades, the concern over the emission of greenhouse gases has prompted the automotive industry to look for alternatives to replace fossil fuel-powered engines for the ones powered by alternative energy sources [1], [2]. Thereby, as found in the literature, bidirectional, single-phase, and isolated topologies for battery chargers applied in electric vehicles have gained prominence. Then, a categorization of such converters should be adopted in order to organize their characteristics. For this study, it is adopted the categorization by the number of energy conversion stages, resulting in two families: dual-stage and single-stage [3].
For instance, Fig. 1 shows the generalized structure for a single-stage converter. This kind of converters are attractive due to their bidirectional power flow and power factor The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao . correction (PFC), besides a higher power density can be archived when compared to the dual-stage ones, as well the possibility of higher efficiency due to the fewer number of active semiconductors and soft-switching regions operation, [4]- [6]. For these last ones, a resonant filter is usually inserted into the high-frequency isolation link, [7], [8]. Moreover, soft-switching operation also allows an increment of switching frequency, resulting in weight and volume reduction of magnetic elements, however leading to losses increment on semiconductors. Then, an optimal configuration among softswitching operation, switching frequency, and power density should be considered for those topologies.
There is another kind of categorization, originally discussed in [9], known as integrated-stage structures, and can also be addressed with single-stage topologies. These structures employ interleaved multilevel converters with coupled inductor on the primary side, and also contain a dc-link that is not used as an intermediate energy store for power transfer [10], [11], as usually happens on dual-stage converters. Thus, multilevel converters have been an alternative quite interesting to high power and medium voltage industrial applications in the last decades [12].
Moreover, the use of the interleaving technique with coupled inductor provides good distribution of semiconductor losses, since its current is half of the input current, and can also reduces weight, and volume of magnetic components when compared to the configuration with interleaved legs and uncoupled inductor [13].
In particular, the three-level multilevel neutral point clamped (NPC) inverter has received more attention in power electronics field due to its advantages. When compared to the two-level inverter, three-level NPC one has some advantages, such as lower total harmonic distortion (THD) of the output voltage, reduction of the blocking voltage on semiconductors, reduced losses on switches, and higher efficiency [14].
The three well-known types of neutral point clamped are: conventional NPC [15], [16], active NPC (ANPC) [17] and NPC T-type (TNPC) [18]. The TNPC shows improvements over the NPC and ANPC, such as reduced conduction losses, fewer switches, volume reduction, and simpler operation. Indeed, recent works have shown interest in the study of the five-level TNPC single-phase inverter [19], [20], due to the aforementioned characteristics.
In this sense, since the T-type presented high performance [21], [22], and also assuming that it behaves better than NPC [23], a power converter using the T-type configuration providing bidirectional power flow in an ac-dc integrated stage is proposed, experimentally investigated, and compared with the structure based on the NPC configuration [24].
Thus, this paper mainly focuses on presenting the proof of concept of the proposed converter through the following organization: operation principle, design considerations and losses analysis are presented in Section II, while the mathematical model and control scheme are described in Section III and IV, respectively. Experimental results are shown in order to validate the proposed structure, as the comparative power analysis of both topologies (T-type based and NPC one based) are presented in section V. Finally, the conclusion is presented in Section VI.

A. CONVERTER STRUCTURE
The proposed structure is shown in Fig. 2a, consisting in a T-type converter associated with coupled inductor (CI) on the primary side (ac side) and a full-bridge on the secondary side (dc side), with a high-frequency transformer providing galvanic isolation. In this figure, L f is the input filter inductor, L a and L b are the self-inductances of CI, L s is the power transfer inductor, and φ is the phase-shift angle responsible for the power flow operation modes. The proposed topology is called I2TDF1: I (interleaved), 2 (dual), T (T-type), D (dualactive-bridge), F (full-bridge), 1 (single-phase), whereas the topology based on the NPC converter, proposed in [24], is called I2NDF1, where 'N' stands for NPC in the adopted acronym, and is presented in Fig. 2b. It can immediately be observed that the advantage of the T-type converter over the NPC one is the suppression of the diodes D1 to D4, should implies a reduction of conduction losses, and simpler implementation.
Furthermore, the modulation, the model, and the control requirement are the same for both converters, as evidenced in the following sections.

B. OPERATION PRINCIPLE
Both converters use level-shifted pulse width modulation (LSPWM) with carriers in-phase disposition (IPD) on the primary side, as indicated in Fig. 3. Carriers cr a1 and cr a2 are level displaced, but are in phase, while carriers cr b1 and cr b2 are shifted by 180 degrees from carriers cr a1 and cr a2 , respectively. It is adopted the phase-shifted pulse width modulation (PSPWM) on the secondary side, where the carriers cr c1 and cr c2 are shifted by 180 degrees among each other. Thus, the behavior of complementary switches (S xy , S xy ) is determined by comparing the modulating signal v mz with carrier cr xy , so the switching function s xy can assume two possible states: where x ∈ {(a, b) legs on ac side, (c) full-bridge on dc side}, and y ∈ {1, 2}. For the applied modulation, there are seven possible combinations of switching states on the primary side, and four ones on the secondary side, as listed in Tables 1 and 2, respectively. For ideal conditions, the voltages across capacitors C 1,p , and C 1,n is V dc,1 /2. Thus, the multilevel and transformer primary voltage can be expressed, respectively, as follows: The voltage on the primary side of the transformer can also be expressed as: where: If v ma ≤ 1 and v mb ≤ 1, the amplitudes of the fundamental frequency voltages v a and v b are linearly proportional to v ma and v mb , respectively. Then: where m is the ac fundamental modulation signal, and m o is the offset to maintain the dc bias current [25], which in this work is supposed to be null. Similarly, on the dc side, the voltage across capacitor C 2 is V dc,2 , also under ideal conditions. Thus the transformer secondary voltage is expressed as: where v mc is the absolute value of m. The input current is obtained by summing the currents flowing through the inductances of windings L a and L b , which is given by: Therefore, the frequency of the filter inductor current f ap is double of the switching frequency f s .
The circulating current is defined as: Its average value per frequency cycle has to be zero and its variation has to be low to avoid magnetic saturation and size and volume reduction of the CI [26].
Then, after established the basic equations for the proposed converter, it is possible to address its theoretical model, as presented in the following section.

C. DESIGN CONSIDERATIONS 1) INPUT FILTER INDUCTOR
According to [26], the input filter inductance is given by: (12) where I L f is the current ripple through the inductor L f . Fig. 4 presents the effective duty ratio of the high-frequency link primary side voltage v 1 , whose analytical description is given by:

2) POWER TRANSFER INDUCTOR
, ω o is the grid angular frequency, and m a is it the modulation index. The power transfer inductor, obtained by the active power fundamental model at switching frequency, can be calculated as: where n is the transformer turns ratio, and P o is the rated power [27]. Note that there is no closed-form solution for L s , and a numerical method is required.

3) COUPLED INDUCTOR AND TRANSFORMER
The coupled inductor and the high-frequency transformer are obtained taking into account the maximum voltage, the rms current, and the switching frequency on these elements, using the criteria established in [28].

4) FILTER CAPACITORS
The capacitance design is performed considering their accumulated energy [29]. The capacitances of the primary and secondary buses are determined, respectively, as:

5) DESIGN PROCEDURES
The design specifications of the I2TDF1 are listed in Table 3, and using the presented considerations, the components used in the implementation of the experimental prototype are listed in Table 4.

D. LOSSES ANALYSIS
The calculated losses of the I2TDF1 and I2NDF1 converters with rated power are shown in Fig. 5. The analysis of the semiconductors losses was estimated using the methodology described in [30]- [32]. The IGBT conduction power losses during one switching period T s are given by: where v CE is the collector-emitter voltage, and i CE is the collector current. VOLUME 9, 2021 The conduction losses of the anti-parallel diodes (body diode) or the I2NDF1 converter diodes are given by: where v F is the diode forward voltage, and i F is the diode forward current. The IGBT switching losses can be estimated from equation below: where E on and E off are, respectively, the turn-on and turn-off switching energy losses. Moreover, the losses of magnetic components were calculated using the procedure presented in [28], as the copper losses are defined as: where I s,rms is the rms current flowing through the conductor, and R s is the conductor resistance.
The core losses are given by Steinmetz's Equation: where k, α and β are parameters related to the properties of the core (empirical values), while f is the magnetic field frequency, and B is the magnetic flux density [13]. Therefore, taking into account the parameters listed in Tables 3 and 4, and considering the values presented in datasheet of the IGBT IRGP50B60PD and the diode SCS230AE2, a MATLAB routine was used to perform the calculations of (17) to (21), during the entire grid electrical period.
Considering the rectifier operation mode, Fig. 5a presents the overall losses of the I2TDF1 and I2NDF1 converters, which is equal to 75.43 W and 82.22 W, respectively. Whereas, considering the inverter operation mode, the overall losses of the I2TDF1 and I2NDF1 converters are equal to 84.14 W and 94.79 W, respectively, as shown in Fig. 5b. In both situations, the I2TDF1 has presented lower losses than the I2NDF1 converter. Furthermore, through Fig.5, it can be seen that the major losses are due to the semiconductors on the primary side.

III. CONVERTER MODEL
This section presents the model of the proposed converter, divided into two parts: one related to the modeling of the converter on the primary side, a T-type converter, and the other one in relation to the secondary side, a full-bridge converter.

A. PRIMARY SIDE CONVERTER MODEL
The model of the inversely coupled inductor is used to obtain an uncoupled relation between the circulation current and the input current. In order to model the differential and primary bus voltage, it is considered the current flow through capacitors C 1,p and C 1,n . Fig. 6a shows the CI equivalent circuit, containing the following variables: individual windings resistance R w ; dispersion inductance L k ; mutual inductance M ; voltages and current of each converter arm, respectively (v a and v b ) and (i a and i b ); and input voltage (v ac ) and current (i ac ). These voltages and currents can be defined in terms of common-mode and differential-mode, as follows:

1) DIFFERENTIAL-/COMMON-MODE CURRENT
Thus, the input and circulating currents are defined as: From Fig. 6a, it can be inferred the following equations: where L (L a = L b ) represents the self-inductance and is given by the sum of the leakage inductance L k and the mutual inductance M .
Combining (22) and (23) with (28) and (29): Summing and subtracting (30) and (31), it can be obtained the common-mode and differential-mode voltages, respectively. Moreover such relations are represented in Fig. 6b and Fig. 6c, and analytically expressed as: As it can be seen from Fig.2a, the voltage across the filter inductor L f is: Replacing (26) in (34): Combining (35) and (32): Performing the Laplace transform of (33) and (36), assuming zero initial conditions, the transfer functions of the differential-mode and common-mode currents can be obtained and are defined, respectively, as: Last, considering (7) and (8), the voltages V dm (s) and V cm (s) are given by: 2) DIFFERENTIAL AND PRIMARY BUS VOLTAGE As can be seen from Fig. 7, the currents flowing through capacitors C 1,p and C 1,n , as well as the currents exiting in the neutral point node, can be expressed as: where i Ta and i Tb are related to the legs of the three-level T-type converter, and i ac is the input current.
Considering that capacitors C 1,p and C 1,n have the same capacitance C 1 , and the currents i Ta and i Tb are internal disturbances of the system, the differential equation for the differential voltage is given by: where v dif = v C1,p −v C1,n represents the differential voltage. Taking the Laplace transform of (42), with zero initial conditions, it can be written the following equation: Following a similar approach to the one developed for the differential voltage loop, the transfer function between the primary bus voltage and the input current can be expressed as: The representation of the converter from the point of view of the output is shown in Fig. 8, where it can be noted that the converter behaves as a voltage source controlled by a phaseshift, and thus this must be the variable to be adjusted. The linearization process to determine the gain K DAB consists on calculating the angular coefficient of the line equation from the two phase-shift conditions near to the operating point (i.e., rated phase-shift φ). Then, for small variations of φ, it can be obtained: where I dc,2 is the rated load current. According to Fig. 8, the differential equation that models the K DAB behavior is obtained as follows: So the transfer function that relates the secondary bus voltage with the phase-shift angle is given by:

IV. CONTROL METHOD
This section presents the control strategy used in the proposed converter. The proposal is also divided into parts for the sake of clarity: the first one is for primary side control, while the other one is for the secondary side [24], as indicated in Fig. 9. Also, three distinct control loops can be identified: two loops related to the primary side, and one to the secondary one.

A. PRIMARY SIDE CONTROL STRATEGY
The block diagram with the controllers responsible for regulating the voltages and currents on the primary side of the converter is shown in Fig. 9. The controllers (I) and (II) are responsible, respectively, for the control of the circulating (i cir ) and input (i ac ) currents, the strategy used is adapted from [25], [33]. On the other hand, the controllers (III) and (IV) are responsible, respectively, for the bus voltage control V dc1 and the capacitors voltages balancing v C1,p and v C1,n , as adaptation of the strategy presented in [34].

1) CURRENT LOOP
It is presented in [33] an optimization method of proportionalintegrative (PI) controllers that enables the increase of proportional gain k P and decreases the integral time constant τ I , thus increasing the integrative gain k I , while taking into account the effects of transport and sampling delays T D = 3/(4f s ), by given a desirable phase margin φ M . This strategy is used in the current control of a multilevel converter with coupled inductor, because it presents, as an advantage, the possibility of controlling, through two distinct processes, the common-and differential-mode currents, since these currents are uncoupled [25]. In the proposed converter, only PI controllers are used, due to the simplicity of equation and digital implementation. The PI controller for the differential-mode current presented in the loop (I) is defined as: The open-loop transfer function of the differential-mode current with compensator OLTF idm wc (s) is given by: where K conv is the converter gain and is equal to V dc,1 /2. The phase angle of OLTF idm wc (s) at the crossover frequency ω C , in radians, is given by: Typically, ω C τ dm P ≈ π/2, thus, from (51), the integral time constant can be defined as: And since the gain of OLTF dm wc (s) is equal to 1, at the crossover frequency, the proportional gain is given by: Typically, ω C τ dm P 1, and ω C τ dm I 1 so the proportional gain is reduced to: On the other hand, regarding the loop (II), the PI controller for the common-mode current is defined as: The open-loop transfer function of the common-mode current with compensator OLTF icm wc (s) is given by: Comparing OLTF icm wc (s) and OLTF idm wc (s), the differences relays on the plant transfer function. In this way, the methodology to find the proportional gain, as well as the integral time constant for G cm C , is similar to the one developed for the differential-mode controller. Thus: For the cascade control system presented in Fig. 9, it is important to notice that the current closed-loop system is considered by the voltage loop simply as a constant, defined as the inverse of the current sensor gain, which assumed as unitary, simplifies the system, as similarly investigated by [35]. The open-loop transfer function of the differential voltage with compensator OLTF vdif wc (s) is defined as: where G f (s) is the transfer function of the first order low-pass filter, and τ f is the filter time constant equal to 1/(2πf o ).
The phase angle of OLTF vdif wc (s) at the crossover frequency ω C , in radians, is given by: So, by rearranging (60), the integral time constant is given by: And since the gain of OLTF vdif wc (s) is equal to 1, at the crossover frequency, the proportional gain is: Similar to the development of the differential voltage loop, the integral time constant and the proportional gain for the primary bus voltage loop are given, respectively, by:

B. SECONDARY SIDE CONTROL STRATEGY
The block diagram with the controller responsible for regulating the voltage of the secondary side (dc side) of the converter is also shown in Fig. 9.
The open-loop transfer function of the secondary bus voltage OLTF vdc2 wc (s), the loop (V), is given by: Similar to the development of the voltage loops at primary side, choosing the phase margin and the crossover frequency, the integral time constant and the proportional gain are given, respectively, by: The phase margins and crossover frequencies were chosen with the commitment between system speed response and the possibility of embedded implementation, considering the assumptions found in the literature, similarly to the ones found in [35]. The differential-/common-mode current controllers gains have been chosen in order to keep the phase margin as f s /10, and the crossover frequency as 50 • , as shown in Fig. 10. The crossover frequency for the primary and secondary bus voltage loops have been chosen as f o /4 = 15 Hz, while the phase margin is 75 • , as presented in Fig. 11 and Fig. 12, respectively. Moreover, the crossover frequency for the differential voltage has been chosen as f cvdif = f o /10 = 5 Hz and the phase margin is 75 • , as presented in Fig. 11. Using the values listed in Tables 3 and 4, and considering the aforementioned specifications, the controllers gains are presented in Table 5.

V. EXPERIMENTAL RESULTS
To verify the feasibility of the proposed converter, a prototype has been built and tested according to the specifications listed   in Tables 3 and 4, as presented in Fig. 13. The control platform is a TMS320F28379D DSP from Texas Instruments. The currents and voltages signals acquisitions are obtained through sensors HO 25-NP/SP33 and LV 20-P, respectively, both from the manufacturer LEM. The switches on the primary and secondary sides are IGBT IRGP50B60PD from SEMIKRON SKHI61R driver, while diodes SCS230AE2 are used on the primary side of the NPC.

A. PRIMARY BUS PRELOAD
The initial configuration consists on loading the primary bus voltage before initiating the secondary bus control. This process aims to reduce undesirable voltage derivatives, and consequently, current peaks on the magnetic elements, and thus preventing the IGBTs from being damaged or the converter protections to act early.
Initially, in order to avoid that, the switches are all turnedoff, and the voltage across capacitors C 1,p , and C 1,n are equal to the peak ac side voltage. Then to preload the capacitors, the control is enabled to obtain the rated voltage on the primary bus. Thus, when the steady state occurs, there is balance situation at the neutral point, as the voltages, C 1,p , and C 1,n , present the same average value of V dc,1 /2. Once this process is finished, the secondary bus control is activated.

B. DYNAMICS TESTS 1) STEP-LOAD AT RECTIFIER OPERATION MODE (ROM)
To verify the control loops stability, it was performed a load step from 50% to 100% of the rated load, as presented in Fig. 14a. It is important to notice the DC voltages undershoots: V C,2 stabilizes at, approximately, 40 ms, while V C1,p and V C1,n voltages at, approximately, 160 ms. Fig. 14b indicates the load step from 100% to 50%, where bus voltage V C,2 stabilizes around 40 ms, while V C1,p and V C1,n stabilize at, approximately, 120 ms. It can observed from both steps that the control loops worked as expected.

2) STEP-LOAD AT INVERTER OPERATION MODE (IOM)
As observed during the load steps at the ROM, the control loops were also able to stabilize the variables in their reference values at the IOM, according to Figs. 14c and 14d. As can be noted, the main difference is a greater voltage and current oscillations on the primary side while the process return to their rated voltages. Input current i ac , channel 1 (5 A/div); voltage across the capacitor C 1,p , v C 1,p ; channel 2 (50 V/div); voltage across the capacitor C 1,n , v C 1,n ; channel 3 (50 V/div); voltage across the capacitor C 2 , v C 2 , channel 4 (50 V/div).

C. BIDIRECTIONAL TESTS
Initially, the converter is working at ROM, until the power flow is reversed, at 40 ms, as shown in Fig. 15a. It can be noted that bus voltages are stabilized, which proves the voltage VOLUME 9, 2021 control loop good performance. The power flow inversion is noted at 60 ms, when the current is phase shifted from the reference voltage waveform at 180 • (curve in light gray). On the other hand, Fig. 15b shows a similar process to the previously one, but, the converter is in IOM, initially. The inversion occurs around 20 ms after the beginning of the process. It can also be noted that the voltage loops regulate the DC buses. FIGURE 15. Power flow inversion: input current i ac , channel 1 (2 A/div); voltage across the capacitor C 1,p , v C 1,p ; channel 2 (50 V/div); voltage across the capacitor C 1,n , v C 1,n ; channel 3 (50 V/div); voltage across the capacitor C 2 , v C 2 , channel 4 (50 V/div). (a) ROM to IOM. (b) IOM to ROM.

D. POWER ANALYSIS
Power analysis takes into account the following aspects: power factor, efficiency, total current harmonic distortion (THDi) and current harmonic content measurement for both modes of operation (ROM and IOM) considering the international standard IEC 61000-3-2 for class A equipment. The tests were performed considering an initial output power of 200 W, with increments of 100 W, until reaching the rated power at 850 W, for both I2NDF1 and I2TDF1 converters.
Two power analyzers (YOKOGAWA WT310) were connected to the input and output from both converters. The power factor reaches almost 0.996 in both modes, as can be seen in Fig. 16. At ROM, the power factor increases and reaches its maximum value at 300 W, and decreases down to 0.993 at the rated power of 850 W. On the other hand, at IOM, it reaches its maximum at 400 W and then decreases to 0.994, again at the rated power. Both converters present a high power factor and similar trend regarding to the variation of theirs operation power levels.   17 shows the efficiency curves for the rectifier and inverter modes for both converters. It can be seen that the I2TDF1 topology performed slightly better than the I2NDF1 one for the entire operating power range, presenting a better result at the nominal output power of around 1%. More particularly, the I2TDF1 converter presented its maximum efficiency around 300 W, being 91.398% and 90.602% in the rectifier and inverter modes, respectively. As for the rated power, the efficiencies are 89.397% and 87.515%, respectively, and on average, was 1.23% less than the estimated efficiency, as detailed in Fig 5. It is worth to mention that the efficiency can be further improved with the use of modern materials for magnetic elements and semiconductor devices.  For the harmonic analysis results, in the rectifier mode, the THDi is less than 5% for almost the entire operating range, as can be observed in Fig. 18. Moreover, this value is still kept low while the operation is around to 200 W. Above 300 W, both converters present THDi less than 5% for both operation modes. It was also verified that, when load power is reduced, the 11th harmonica is greater than the one predicted in the standard IEC 61000-3-2. More clearly, in the ROM, such behavior is verified until 350 W, while at IOM, until 400 W. From Figs. 19a and 19b, it is possible to verify that both converters are in accordance with the international standard IEC 61000-3-2 for both rated power operating modes.

VI. CONCLUSION
This paper presented a bidirectional isolated ac-dc converter based on the multi-state switching cell (MSSC) with a T-type (TNPC) cell on primary side. Converter modeling is a fundamental point for its correct functioning and understood, as the model found is also used for both converters. Furthermore, a great advantage of these type of converters are the possibility of employing a relatively simple control method, as uses classic control techniques on its structure.
The experimental results with rated conditions showed a high power factor on the AC grid, of approximately 0.993, and a low THDi, less than 3%, for both rectifier and inverter operation modes. Dynamic and bidirectional tests have been performed in order to validate the proposed structure and compared with the NPC converter. It was noted that the I2TDF1 topology achieved a better performance than I2NDF1, being more efficient as it employs only active switches and no additional diodes. Indeed, it was observed that the efficiencies were, on average, less than 1.23% of the estimated values obtained from elaborated losses analysis.
Therefore, the proposed converter must be seen as an attractive solution to replace the NPC-based power converter topologies in applications such as Solid State Transformers in MV Traction, and in battery charging, where a bidirectional power flow, as well as power factor correction are mandatory.