An Asymmetric Short-Circuit Fault Ride-Through Strategy Providing Current Limiting and Continuous Voltage Supply for Three-Phase Three-Wire Stand-Alone Inverters

The three-phase three-wire stand-alone inverter is required to have short-circuit fault ride-through ability to achieve continuity of power supply. Generally the inverter works in current-controlled mode in symmetric short-circuit conditions, but voltage limiting and harmonic distortion will appear under this method when asymmetric short-circuit fault occurs. Several existing methods for asymmetric fault ride-through can achieve current limiting without voltage limiting, however, none of them can guarantee that the healthy phase voltage keeps constant before and after fault. This article proposes a fault ride-through strategy for asymmetric short-circuit conditions, which not only keeps the healthy phase voltage constant with different loads, but also makes the fault phase current limited and controllable. This goal is achieved by a simple control structure combining $\alpha $ -axis voltage control and $\beta $ -axis current control at the same time. Furthermore, the voltage and current characteristics of this method under different load conditions have been analyzed, the analysis results indicate that the impact of different loads on fault ride-through performance is almost negligible. The correctness of theoretical analysis and the effectiveness of proposed strategy is verified by experimental results.


I. INTRODUCTION
With the development of industrial technology, the threephase stand-alone inverter is playing a more and more important role in various applications, such as Uninterruptible Power Supply (UPS), distributed power system, microgrid and so on, which requires high commands on power quantities, power supply continuity and reliability [1]- [5]. The inverter should supply the load continuously and steadily. It is required to cope with abnormal conditions and have fault ride-through ability. In numerous abnormal conditions, short-circuit fault is the most severe one, the fault current must be limited to avoid damaging the power semiconductor The associate editor coordinating the review of this manuscript and approving it for publication was Venkateshkumar M . devices [6]- [9]. Normally one inverter would supply multiple loads, which may include some critical loads. For these critical loads, there are high reliability requirements, and the loss of output voltage is unacceptable. Thus, selective protection is necessary, and the inverter needs to have the ability to achieve fault ride-through without shutdown [10], [11]. When one of the loads suffered a short-circuit fault, appropriate control strategy should be adopted to cooperate with the protection devices to clear the fault branch quickly, and then resume normal power supply after the fault is cleared, thereby the selective protection has been realized [10]- [12]. Moreover, the three-phase inverter including three-phase threewire inverter usually feeds some single-phase loads, and their power supply should not be affected by other phases, even if other phases fail. VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ Several references have investigated the short-circuit fault ride-through method [11]- [14]. Usually the dual loop controller (outer voltage loop and inner inductor current loop) in synchronous reference frame (dq frame) is adopted in threephase stand-alone inverter. The inverter works in voltagecontrolled mode (VCM) in normal condition, while working in current-controlled mode (CCM) during the short-circuit fault [13]. The inverter will return to the VCM from CCM after the fault is cleared. Current limiting can be guaranteed by the saturation block of voltage loop [15]. This control method could work well in three-phase symmetric shortcircuit fault. However, voltage limiting and harmonic distortion would appear under asymmetric faults [16]. As a result, the output current cannot be controlled as expected, and the power semiconductor devices may be damaged.
Focusing on the fault ride-through issue under asymmetric short-circuit situation, firstly this article makes the goals of fault ride-through process clear, which are: 1) the healthy phase voltage should keep constant before and after fault and under different loads; 2) the fault phase current should be limited and controllable to trigger the action of protection devices like breakers to clear the fault branch.
These goals are easy to achieve in three-phase four-wire system since the fault phases could work in CCM while the healthy phases continue to work in VCM during the fault [17]- [19]. But in the three-phase three-wire system, there are physical constraints on the voltage and current between the three phases, so the three phases cannot be controlled separately, which makes the asymmetric fault ridethrough problem more difficult.
In order to accomplish the current limiting control of three-phase three-leg stand-alone inverter during asymmetrical fault without output voltage limiting, the mechanism of the voltage limiting under asymmetrical fault was investigated in [20] and a current limiting strategy with the current limiting references regulated by an introduced phase angle was proposed. However, all phases worked in CCM with different references, which means the voltage of healthy phase could not keep constant in different load conditions, also there is no guarantee of immutability before and after the fault. So that the power supply of healthy phase load will be affected. In [21], a current limiting strategy with parallel virtual impedance was proposed. The drawback of this method is that the design procedure of virtual impedance is complicated and the system stability issue should be concerned carefully due to the introduction of virtual impedance.
These controllers proposed in [20] and [21] are both implemented in abc frame. Another way is to control in dq frame. A sequence-based control strategy with current limiter was proposed in [22]. There are separate controllers in dq frame in positive-and negative-sequence to deal with the unbalanced voltage and current signals while the current limiter is accomplished in abc frame. However, this control structure is too complicated since the controllers are established in both positive-and negative-sequence, and a total of ten coordinate transformation operations are needed. Besides, all the methods proposed in [20]- [22] have a common problem, the RMS value of healthy phase voltage cannot keep constant before and after fault, and it also cannot keep constant if the load changed during the fault ride-through process. Thus, the power supply continuity and reliability of healthy phases cannot be guaranteed even though the fault occurs in other phases.
In order to achieve these goals of asymmetric fault ridethrough process, this article proposes a fault ride-through strategy, whose control structure is established in αβ frame. The main idea is to assign different tasks of α-axis and β-axis controller, the β-axis controller worked in CCM to limit current during the fault, while the α-axis controller still worked in VCM to supply the load of healthy phase continuously and steadily. Another advantage of this proposed method is that its control algorithm is very simple. The theoretical analysis and experimental verification prove that the proposed fault ridethrough strategy could work well and is a pretty good solution in asymmetric short-circuit fault ride-through occasions.
The rest of this article is organized as follows. Section II presents the proposed asymmetric short-circuit fault ridethrough strategy and explains its principle. The voltage and current characteristics under this method and its influence on selective protection and fault ride-through are studied in Section III. Experimental verifications are shown in Section IV. Finally, conclusions are drawn in Section V.

II. PROPOSED FAULT RIDE-THROUGH STRATEGY
There are three types of asymmetric faults in the three-phase power supply system: single line-to-ground fault, double lineto-ground fault and line-to-line fault. For a three-phase threewire system, there is no ground terminal connected to the loads [23]. The insulation fault to ground is another type of fault, the control system of the inverter cannot help to clear the fault and cannot play a role in fault handling in this case, and the leakage protection devices are needed to work. Thus, only the line-to-line fault is addressed in this article.
As mentioned above, the goals of the fault ride-through process should be defined clearly first. When the asymmetric short-circuit fault occurs, the fault phase current should be limited to protect the power semiconductor devices, then the protection devices like breakers will be triggered to clear the fault branch, so that the selective protection can be realized. In the meanwhile, the healthy phase needs to be supplied continuously and steadily. Thus, these goals require that the healthy phase should be controlled as voltage source while the fault phase should be controlled as current source.
This section first derives the circuit model of the threephase three-wire stand-alone inverter under asymmetric short-circuit fault, then a fault ride-through method is proposed, whose control structure is established in αβ frame. The β-axis controller works in CCM while the α-axis controller still works in VCM during the fault.

A. CIRCUIT MODEL
If the short-circuit fault occurs between phase B and phase C, the equivalent circuit is shown in Fig.1, and the other cases can be analyzed in a similar way. In Fig.1, u a , u b , u c represent the arm voltage of each phase, and i LA , i LB , i LC represent the inductor current of each phase. The output voltage and current can be expressed as (1) Suppose that the impedance of each phase is Z before the fault occurs. Then BC phase short-circuit fault occurs and Z s represents the impedance of BC phase during the fault. This article only discusses the metallic short-circuit fault, which is the severest situation, and Z s is almost equal to 0 in this case.
Note that the healthy phase should be controlled as voltage source while the fault phase should be controlled as current source to achieve the aims of the asymmetric short-circuit fault ride-through. However, there are physical constraints on the voltage and current between the three phases. Actually there are only two control degrees of freedom due to the coupling between the three phases. The control goals of healthy phase and fault phase are different and independent. It is difficult to achieve the control target that the healthy phase works in VCM and the fault phase works in CCM if the controller is implemented in abc frame. Moreover, it should be noted that the output currents of phase B and phase C are not only related to the short-circuit current (i BC ), but also to the load, which means that they contain the information of both the fault phase and the healthy phase. This makes their physical meaning unclear, and it is difficult to determine the voltage and current references in abc frame to achieve the purpose of current limiting. Consequently, the controllers can be implemented in αβ frame. The voltage and current of α and β axis can be controlled separately.
Transforming the mathematical model to αβ frame, the expressions of output voltage and current in αβ frame are given in (4) and (5).
From (4) and (5), it can be known that the voltage and current of α axis reflect the information of healthy phase. The current of α axis depends on the load of healthy phase. While the voltage and current of β axis reflect the information of fault phase. Its voltage is almost equal to 0 due to the shortcircuit fault, and its current is related to the current of phase BC, which should be limited.

B. PROPOSED CURRENT LIMITING AND FAULT RIDE-THROUGH STRATEGY
Based on the above analysis, a current limiting and fault ride-through strategy is proposed in this article. The control diagram in the normal condition is shown in Fig.2(a), outer output voltage loop and inner inductor current loop in αβ frame is adopted, and the control structures of α and β axis are the same. When a short-circuit fault occurred in phase BC, the dual loop is still adopted in α axis to supply the load of healthy phase, while current limiting control is adopted in β axis to protect the power semiconductor devices from damage and trigger the action of protection devices like breakers to clear the fault branch, as shown in Fig.2(b), where the PR controller is adopted to eliminate steady-state error. The design method of PR controller has been widely studied [24], [25], this article will not repeat it.
The references of control system in the normal condition are given in (6), where V N is the RMS value of rated line-toline voltage, and ϕ α is the initial angle.
In order to supply the load of healthy phase continuously and steadily during the fault, the line-to-line voltage VOLUME 8, 2020 (RMS value) of healthy phase, namely the value of V AB , should keep constant. Thus, the amplitude of v * α should be 2/ √ 3 times before the fault according to (4). The phase angle of v * α can keep constant before and after fault, which means v AB will have a phase change. To simplify the control algorithm, the phase angle of i * β keeps consistent with v * β_pre , and the output current behaviors in abc frame will be analyzed in Section III. Thus, the references of control system during the fault are given in (7), where I * L_Limit is the current limit value.
If the short-circuit fault occurs in phase AB or phase CA, this strategy still works, only needs to change the reference angles of αβ coordinate system, as shown in Fig.3. In these two cases, the new coordinate system is named α β and α β coordinate system, respectively. Equation (7) needs to be rewritten as (8) and (9) in phase CA and phase AB shortcircuit conditions, respectively. The whole control process of the proposed fault ridethrough method is shown in Fig.4. Firstly the fault phase should be identified. When an asymmetric short-circuit fault occurs, the output voltages and currents of healthy phase and fault phase will be different, and the output currents of fault phase will increase significantly. Therefore, the fault type can be identified quickly, and the selection of the coordinate system (αβ, α β , or α β coordinate system) can be determined accordingly. Also the voltage and current references can be determined based on (7)- (9). After the close-loop calculation and the inverse Clark transformation, the modulation signals in abc coordinate system can be obtained.
From (6) and (7), it can be seen that only the references of controllers have been changed though the control structure of β axis has been changed before and after fault. If the reference coordinate system needs to be changed from αβ to α β or α β , the historical error data and output data of the 211066 VOLUME 8, 2020 controllers need to be cleared. Then, the smooth switching between the normal operation and the fault operation can be guaranteed.

III. FAULT CURRENT CHARACTERISTICS ANALYSIS
Since the control system is established in αβ frame, the voltage and current characteristics in abc frame, especially the fault phase current characteristics, should be analyzed to get a comprehensive understanding. Morever, the influence on fault ride-through and selective protection under this proposed method will be assessed in this section.

A. FAULT CURRENT CHARACTERISTICS UNDER THE PROPOSED METHOD
The rated current is expressed as (10), where Z N is the rated load ( -connected). The current references in abc frame are shown in (11).
Usually the current limit value is set as 2-3 times the rated value [21]. In this article, it is set as two times the rated value, as shown in (12).
It can be assumed that the actual values can track the reference values ideally if the controllers could achieve zero steady error. Generally the capacitance value of filter capacitor of the inverter is small, thus the capacitor current in the steady state is very small compared with the inductor current and can be ignored [20]. Therefore, the inductor current is equal to the output current if the capacitor current is ignored.
Within the scope of this research, the power factor (PF) of load is from 0.8 (lag) to 1. According to the analysis in section II, I Oα is determined by the load. The instantaneous current reference i * Lα is equal to i Oα according to the above assumption. Thus, the range of I * Lα is expressed as (13).
Firstly, the pure resistive load case is considered, the load of healthy phase changed from no load to full load. The phasor diagrams before and during the fault are given in Fig.5, where V AB , V BC and V CA are the output line-to-line voltage vectors, while V A , V B , V C , I OA , I OB and I OC are the output phase-to-neutral vectors. The length of the vector V AB and V CA remain unchanged before and after fault, which means that the RMS values of V AB and V CA keep constant and the load of healthy phase could be supplied continuously and steadily. I * Lα and I * Lβ are the current references, in addition, I * Lα_half and I * Lα_full are the α-axis current references at half load and full load condition, respectively. I * Lβ is the current limit reference. The vector I OB and I OC can be synthesized from I * Lα and I * Lβ according to (11) since I OB (or I OC ) is equal to I * LB (or I * LC ). Also I OB_half (or I OC_half ) and I OB_full (or I OC_full ) are the output currents at half load and full load condition, respectively.
Combining (11)-(13), the output currents of phase B and phase C can be expressed as (14) in this case.
The output current of phase A is only related to load, and it is equal to I oα according to (5), the expression of I OA is shown in (15).
In this case, the maximum and minimum values of output currents will be achieved in full load and no load condition, respectively. Equation (16)   Next, the resistive-inductive load case (the power factor is 0.8) is considered. When the load of healthy phase changed from no load to full load, equation (13) is still effective.
The phasor diagrams before and during the fault are given in Fig.6. Also the RMS values of V AB and V CA can keep constant in different load conditions during the fault. Similarly, the vector I * Lα can be drawn and ϕ is the power factor angle of load. Then, the vector I OB and I OC can be synthesized from I * Lα and I * Lβ . Based on Fig.6, (17) and (18), as shown at the bottom of the next page, can be obtained, and the output current ranges of phase B and phase C can be calculated, as shown in (19), as shown at the bottom of the next page.
It is easily known that the upper border of I OB and the lower border of I OC are achieved in no load condition, while the Actually (17) and (18) are generalized expressions, which means they were effective in any linear load case including the pure inductive load case and the pure capacitive load case (ϕ ∈ [−π/2, π/2]). Similarly, the output current ranges can be expressed as (20) in the pure inductive load case. Fig.7(a) shows the output current values of phase B and phase C in different load conditions, and the maximum and minimum curves of output current (the phase with higher current) in different power factor angles are shown in Fig.7(b)

B. INFLUENCE ON FAULT RIDE-THROUGH
Note that the purpose of current limiting in fault ride-through process are: 1) to prevent the power semiconductor devices from damage due to excessive current; 2) to trigger the action of protection devices like breakers and clear the fault branch to realize selective protection.
The first item requires the maximum value of output current in the whole load range should be limited within the safe range of the power semiconductor devices. The second one requires the minimum value of output current (the phase with higher current) in the whole load range should be larger than the action threshold of protection devices like breakers, so that the fault branch can be cleared by breakers under any load condition. These requirements can be expressed as (21), where I con is the maximum allowable value of power semiconductor devices and I trigger is the action threshold of the breakers.  (21) This article focuses on the pure resistive load and the resistive-inductive load conditions (PF is 0.8-1).
According to the above analysis, it is easily known that output currents of phase B and phase C were related to the load and the current limit value.
Note that min{max[I OB , I OC ]}| no load→fullload is always obtained in no load condition according to TABLE 1 and Fig.7. What's more, it only depends on the set current limit value and is not related to the power factor of load according to (14)- (20), as shown in (22).
The action threshold of the breakers needs to be designed cooperating with the current limit value and the inverter capacity. According to (21) and (22), it can be known that  as long as the set current limit value, I * L_Limit , was larger than 2/ √ 3 times the action threshold of the breakers, the breakers can be activated and the fault branch can be cleared, then the selective protection will be achieved.
In addition, max{max[I OB , I OC ]}| no load→full load is always obtained in full load condition. Its value is related to the power factor of load. It is about 1.8257I N when PF=1, while it is about 2.1292I N when PF=0.8, which is the maximum value within all load ranges. Though the maximum value of output current can not be limited to the set limit value strictly, its variation range is small since this current is mainly determined by I * β , namely, the set current limit value. The maximum value is within acceptable range and it has little effect on device selection. Even in more extreme load cases like the pure inductive load or the pure capacitive load, the maximum value is only about 2.3094I N . The power semiconductor devices will not be damaged due to excessive current. The fault branch can be cleared by the protection devices like breakers, then selective protection can be achieved. Thus, the influence caused by load variation can be ignored. This proposed strategy has a very simple control structure and can perfectly meet the expected goals mentioned in Section II. It can work well in asymmetric short-circuit fault ride-through occasions.

IV. EXPERIMENTAL RESULTS
In order to verify the effectiveness of the proposed asymmetric short-circuit fault ride-through strategy, the experimental results will be presented in this section. This article focuses on the pure resistive load and the resistive-inductive load conditions (PF is 0.8-1) since it is the most typical condition. Thus, only the pure resistive load case and the resistiveinductive load case with a power factor of 0.8 are tested in this section.
A three-phase combined inverter prototype has been developed, whose structure is shown in Fig.8. It can be modeled as Fig.1, and its parameters are listed in TABLE 2.
The experimental results with different load conditions are shown in Fig.9. Fig.9(a) shows the experimental waveforms under no load condition. The inverter worked under no load condition at the initial time, then phase BC short-circuit fault occurred. It can be seen that the fault phase output voltage, V BC , changed to almost 0, while the RMS value of healthy   phase output voltage, V AB , kept consistent with that before fault. Besides, the fault phase currents, I OB and I OC were limited. The control targets of fault ride-through process mentioned above have been achieved. The fault phase worked in CCM while the healthy phase worked in VCM, and the power supply of healthy phase load did not been affected.
Then experimental results under full load condition are given. Experimental waveforms with pure resistive load case and resistive-inductive load (PF=0.8 lag) case are shown in Fig.9(b) and (c), respectively. According to Fig.9, V AB can also keep constant before and after fault in no load and full load condition, which means power supply reliability of healthy phase can be guaranteed. I OB and I OC are equal in pure resistive load case, and they are different when PF =1, which is consistent with theoretical analysis. The fault phase current values in different load cases are presented in TABLE 3. It can be seen that the experimental results are in good agreement with the theoretical values. The output currents are limited as expected, thus, the power semiconductor devices will not be damaged by overcurrent. The fault branch can be cleared with the cooperation of the protection devices like breakers, then selective protection can be achieved. The correctness of theoretical analysis has been verified.
The experimental results in full load condition (resistiveinductive load case, PF=0.8 lag) when the short-circuit fault occurred in phase CA and phase AB are shown in Fig.10(a) and (b), respectively. Comparing Fig.10 with Fig.9(c), it can be found that the healthy phase still worked in VCM and the fault phase worked in CCM, which means the control targets could be met perfectly. Changing the reference angles of the αβ coordinate system, the proposed strategy is still applicable in phase CA or phase AB shortcircuit conditions. The experimental results have validated the effectiveness of this method.

V. CONCLUSION
In order to accomplish fault ride-through in asymmetric shortcircuit situation, the fault phase current should be limited and controllable, while the output voltage of healthy phase should keep constant to supply the load continuously and steadily. To achieve this goal, a current limiting and fault ride-through strategy has been proposed in this article. It has the following features: 1) The controller was built in αβ frame. The current limiting was realized in β axis, while the α-axis controller still worked in VCM. Its control structure is very simple.
2) The output current characteristics in abc frame with different loads under this proposed method were analyzed and the influence on fault ride-through caused by different loads was assessed. Though the output current of fault phase cannot be limited to the set value strictly, it only varies in a small range within safe operation area, the power semiconductor devices still can be protected effectively. The analysis results proved that this method could work well under different load conditions.
3) This method not only limits the output current of the fault phase, but also ensures that the healthy phase worked in VCM, and the healthy phase voltage can always keep constant in the whole fault ride-through process. Thus, the power supply of healthy phase load will not be affected.
All the goals of asymmetric fault ride-through process mentioned in Section I and Section II can be achieved perfectly. Thus, this proposed method is a good solution in asymmetric short-circuit fault ride-through occasions. The correctness of theoretical analysis and the effectiveness of proposed fault ride-through strategy have been verified by experimental results. From 2008 to 2010, he was a Postdoctoral Research Fellow with the Department of Control Science and Engineering, HUST, where he is currently a Professor with the School of Electrical and Electronics Engineering. He has published more than 50 peer-reviewed technical articles and holds more than ten issued/pending patents. His current research interests include renewable energy and energy storage applications, wireless power transmission, and power electronics applied to power systems.
SHANXU DUAN (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Huazhong University of Science and Technology, Wuhan, China, in 1991, 1994, and 1999, respectively.
Since 1991, he has been a Faculty Member with the School of Electrical and Electronics Engineering, Huazhong University of Science and Technology, where he is currently a Professor. His research interests include stabilization, nonlinear control with application to power electronic circuits and systems, fully digitalized control techniques for power electronics apparatus and systems, and optimal control theory and corresponding application techniques for high-frequency pulse width-modulation power converters.
Dr. Duan is a Senior Member of the Chinese Society of Electrical Engineering and a Council Member of the Chinese Power Electronics Society. He was selected as one of the New Century Excellent Talents by the Ministry of Education of China, in 2007. He was a recipient of the honor of "Delta Scholar" in 2009. VOLUME 8, 2020