Design and Implementation of Multilevel Inverters for Fuel Cell Energy Conversion System

Power converter plays a significant role in Proton Exchange Membrane Fuel Cell (PEMFC) energy generation systems, which is an alternative of distributed energy generation systems. So there creates a demand for high-quality power conditioning used in PEMFC systems. This article proposes a converter topology as a power interface and also introduced a multilevel inverter topology for various levels of operation. The converter steps up the input voltage to the rated voltage and transforms to the DC bus, the multilevel inverter converts the voltage to AC and feeds to AC loads. In this article, we develop an entire unit stack, which can produce an output with positive and zero sequences. The addition of H-bridge to the fundamental unit known to be an advance cascaded H-bridge multilevel inverter resulting in the formation of all sequences like positive, zero and negative levels. The conventional multilevel inverters are compared with the proposed inverters in terms of switch count, DC sources, diodes, through which the lesser requirement of components in a multilevel inverter is possible to observe, which results in the reduction in cost, dv/dt stress, component space of the driver circuit. With this implementation, the better possibility of control, increase the quality of output, reliability of the inverter with a reduced THD, and stress. The converter output is tested and verified in MATLAB, and the respective results of the different levels like five, seven and fifteen of a single-phase cascaded inverter are tested experimentally and in MATLAB Simulink.


I. INTRODUCTION
The basic configuration of inverters is of two-level, where the many drawbacks exist like input voltage is twice than that of the output voltage resulting in the severe harmonic distortions, high switching losses & frequency. It restricts these to only low-power applications as the power handling capacity is less [1]. Hence, the evolution of multilevel inverters (MLI) came into existence to wipe out the The associate editor coordinating the review of this manuscript and approving it for publication was Eklas Hossain . described disadvantages and to provide better reliability and higher in quality of output waveform. The multilevel inverter is an ideal choice to choose for high and medium power applications with its harmonic reduction difference with a conventional inverter with the same power in output and avoiding in increasing the switching frequency [2]- [4]. Multilevel inverters usually come in three forms [5], namely neutral clamping point (NPC), clamping diode (DCM) [6], flying capacitor (FLC) and cascaded H-(CHB) [7], [8]. The promising energy sources nowadays are the Renewable sources of energy such as solar panels and the fuel cell for the distributed generation systems [9]- [12]. From solar panel and fuel cell stacks, it uses the energy generation for energy transformation to feed the AC loads using power electronic devices with DC-AC, DC-DC conversion. It maintains the constant DC voltage at the DC bus by the step-up operation of the converter, and the inverter converts DC to AC and transforms the DC bus voltage to the AC loads. The way of electricity generation is from a fuel cell, which is an electrochemical device. The mixture of air and fuel are the standard inputs for the fuel cell, converts to water and the electric nature to the chemical reaction [13], [14]. Hydrogen plays a significant role in the fuel cell, which can operate parallel with internal combustion engines of the vehicles based on its availability. When the vehicles are on load, the battery characteristics are like a fuel cell. Sir William Robert Grove developed his first fuel cell in 1839.
Further, Sir Francis Bacon developed a usable fuel cell in 1950 with a capacity of 5 kW. Since then, these are popular and used for residential, industrial, and commercial purposes as primary power sources. In the current scenario, the attention towards fuel cells automobile industries for the development of eco-friendly vehicles. There are various types of multilevel inverters such as diode clamped (DC) [6], flying capacitor (FC), cascaded H-bridge (CHB), and a neutral point clamped (NPC). In both the flying capacitor multilevel inverters and neutral point clamped MLI, the balancing of capacitor voltage is the main problem because of which these are limited to only five-level not able to cascade, and output voltage reduces to half of the input voltage provides very high switching losses with high switching frequency. The diode clamping and capacitor voltage balancing are unnecessary for the cascaded multilevel inverters (conventional). Even in the CHB inverters, there is a clean possibility to get the higher output levels as these are series-connected: exempting the usage of DC sources is more. The proposed topology requires a smaller number of switches with which we can reduce the requirement of driver circuits compared with the conventional cascaded multilevel inverter [15]. There is a possibility of a reduction in the dv/dt stress on each switch with the usage of more DC sources, and it becomes reliable, straightforward with less circuit space, and the cost gets reduced [16]. There are many fundamental units and it imports various cascaded multilevel inverters [17], [19], [20], [36].
In this article, a fuel cell-based multilevel inverter is proposed. The basic units are in series to have a higher output level and reduced switch count. The addition of H-bridge achieves both positive and negative levels where the FC and DC are absent. The output constraints of the proposed multilevel inverter with five, seven, and fifteen levels are simulated in MATLAB, and it illustrates the results. The leftover part of this article is organized as: The modeling of the proposed system is analyzed in section-2. The 4-level boost converter with PEMFC with ANFIS MPPT technique is presented in section-3. Section-4 explains the simulation and experimental results of developed MLI topologies. Power loss calculations of the developed MLI are done in section-5, parameters comparison among the proposed MLI with various topologies are presented in section-6, and finally, conclusions are given in section-7.

II. PROTON EXCHANGE MEMBRANE FUEL CELL
The basic structure of the fuel cell is, as shown in Fig. 1 [21]. Electrochemical conversion is the principle involved in it. A fuel cell comprises two electrodes known as anode and cathode. When the anode is fed with hydrogen fuel, the catalyst activates with the separation of positive and negative ions. The generation of electricity happens with the mixture of hydrogen and oxygen in the cell in with the electrolyte. It produces only heat and water in this process, which is wastage, and the emission of gasses is absent [22]. It shows the principle involved in the fuel cell operation in Eq. (1).
It shows the operating principle of the fuel cell in Eq. (1).
It shows the chemical equation at cathode and anode in Equations. (2) and (3).
At cathode: At anode: Because of the reaction of O 2 and H 2 , 1.23V is developed theoretically. Ohmic and activation losses reduce the voltage to be less than 1.23V [23].In general, there are various types of fuel cells based on electrolyte materials like Alkaline Fuel Cell (AFC), Molten Carbonate Fuel Cell (MCFC), Phosphoric Acid Fuel Cell (PAFC), Proton Exchange Membrane Fuel Cell (PEMFC), and Solid Oxide Fuel Cell (SOFC) [24], [25]. In these, PEMFC, DMFC, AFC, and PAFC having an operating temperature of less than 250oC. MCFC and SOFC having a high operating temperature of more than 500oC. The automobile field is the most starving of a fuel cell. In this scenario, the popular in automotive is PEMFC where the power density is high, nominal operating temperature, and very precise [26], [27].
The mathematical modeling of PEMFC is: The PEMFC output voltage is [28] where E nernst is the open-circuited thermodynamic voltage; V ohm is the ohmic voltage V act , and V con is the activation and concentrated voltages, respectively. E nernst is determined: [29], [30].
where T FC is PEMFC cell temperature, P H2 and P O2 are the partial pressures, respectively. The expression of ohmic voltage is: [31], [32].  where R C is the resistance of a proton and R M is the equivalent of resistance. R M is given by.
where ρ m is the membrane specific resistivity, L is thickness, A is the area, G is water content, and J is the current density of the membrane. J is defined as It represents the activation voltage in the parametric form of: where ζ 1 , ζ 2 , ζ 3 and ζ 4 are each cell coefficients, it expresses the oxygen concentration CO2 as The concentration overvoltage is given by where F= Faraday's constant, R=gas constant, Jmax = Maximum current density.

III. PEMFC BASED DC-DC CONVERTER
The 4-level boost converter [33] has seven capacitors, one switch and seven diodes, as shown in Fig. 2. V o is the output voltage of the converter which is the product of the number of levels N and the capacitor voltage Vc is given by where V in is the input voltage, D is the duty cycle.
where T on is on-state of the switch, T is the total time period. At the instant of the closure of switch S, the voltage at the capacitance C 6 is less than C 7 , at this point C 7 clamps C 6 voltage using diode D 6 along with the switch. Similarly, if the voltages at C 4 and C 6 are lesser than the capacitances C 5 , and C 7 , at this point C 5 , and C 7 clamp the voltages at C 4 , and C 6 using diode D 4 along with the switch. Correspondingly, C 3 , C 5 , and C7 clamp the voltages at C 2 , C 4 , and C 6 . At the instant when the switch is open, the inductor current follows the diode D 7 and hence the capacitor C 7 gets charged. All inputs, inductor voltage, and C 6 clamp the voltages at C 5 and C 7 through the diode D 5 when D 7 conducts. Similarly, the inductor voltage and V IN , C 4 , and C 6 clamp the voltages at C 3 , C 5 , and C 7 through the diode D 3 . At long last, inductor voltage and V IN alongside C 2 , C 4 , and C 6 clips the voltages crosswise at C 1 , C 3 , C 5 , and C 7 . It is seen that the diodes D 1 , D 3 , D 5 , and D 7 switches constantly. It is supplemented by the diodes D 2 , D 4 , and D6 along with the switch. Table I. shows the experimental parameters.

A. ANFIS MPPT CONTROLLER
A combination of neural networks and fuzzy systems produces an ANFIS system [34]. This system can learn neural networks, which is a significant advantage. There are five layers with dual inputs (x and y) and single-output (F). The if-then rules of the fuzzy system are given below: if x is A 2 and y is B 2 , then F 1 = p 2 X + q 2 Y + r 2 (16) It can vary the system temperature from 300K to 340K in a step of 20K by training ANFIS. By using these data sets, it generates a fuzzy interference system, where the parameters are tuned with a hybrid optimization method with the combination of least square and backpropagation algorithms.  The proposed converter is simulated in MATLAB and validated experimentally with the dSPACE RTI1104 controller. The fuel cell stock input voltage V In FC = 48V, switching frequency 100kHz, inductor 500H, resistance 0.35-ohm, capacitor 10F with duty cycle 53.37% for obtaining V odc = 400V are shown in Fig. 3 Fig. 1. The FC considered is having the output voltage is 48V and is boosted to 400V maintained at DC link using ANFIS [34].

IV. DEVELOPED STRUCTURE WITH PMFC
The proposed PEMFC inverter composed of a DC-DC converter supplied with fuel cell and it feeds the regulated DC output voltage from the converter to DC bus where the rated voltage can be maintained. It shows the fundamental unit VOLUME 8, 2020 The switches (S2, S4), (S1, S2, S3, S5) and (S1, S3, S4, S5) are to take care that these should not turn on at an instant of time, to avoid short circuit. The various positive voltage levels only can be got. The basic units are to be connected in series to increase the voltage levels, along with this arrangement, the voltage of V A is connected in series with a switch SA, and parallel to switch SB shown in Fig. 6, where the lowest amplitude of voltage level can be possible. A short circuit may occur with the simultaneous operation of the switches SA and SB, which is avoided.
The output voltage V 0 (t) is There are only positive levels in the output voltage of a basic unit. To get the negative levels, an H-Bridge is added to the developed arrangement shown in Fig. 6. H-Bridge contains the switches S H1 to S H4 , where the operation of S H1 and S H4 produces the positive levels and the operation of S H2 and S H3 produces the negative levels of output voltage, resembles to be a multilevel inverter.
It cascades the developed fundamental units to get several levels of output like 5-level, 7-level. 15 levels shown below. The 5-level output can be got with the fundamental unit only, the several modes of operation, expected output waveform with the switching pulses could be represented below. Even though the switch count is high in the 5-level MLI, this is tested experimentally with a prototype, and we design further 7 and 15 level MLI with less device count and low THD.

A. PROPOSED 5-LEVEL MLI
The proposed 5-level MLI is designed with a developed fundamental unit without the addition of the circuit components. The circuit contains fewer number of switches compared with the existing topologies. This topology comprises nine switches with three DC sources without capacitors, diodes shown in Fig. 7. The power quality issues like THD, a smaller number of switches, dv/dt stress are minimized with this developed multilevel inverter. The circuit comprises three DC sources V 1 , V 2 , V 3 , and nine switches S 1 , S 2 S 3 , S 4 , S 5 , S H1 , S H2 , S H3 and S H4 are the modules of H-Bridge. The arrangement reduces the additional DC source requirement and also simplifies the number of switches needed. The operating modes of the 5-Level MLI are shown in Fig. 8.
In this section, it illustrates the developed MLI operation with the steady-state voltage levels in several modes of operation. Here, all the DC source voltages are having equal magnitude, i.e., V 1 = V 2 = V 3 = V dc = 133.33V. Mode-1: In this mode of operation, the switches S 1 , S 2 , S 3 , S H1 , S H4 are in conduction state, hence the load current I o path is through V 1 -S H1 -S H4 -D 3 -V 3 -D 2 -V 2 -D 1 . As all the DC sources are of the same magnitude, the addition of V 1 , V 2 , V 3 voltages can produce 3V dc . The operation of switches S H1 and S H4 in an H-Bridge produces a positive level of voltage. The output voltage level is +3V dc i.e., +400 volts.
Mode-2: In this mode, the switches S 1 , S 3 , S 4 , S H1 , S H4 are in conduction state; hence the load current I o path is through V 1 -S H1 -S H4 -D 3 -V 3 -D 4 -D 1 . The voltages V 1 , V 3 act in the circuits resulting in the formation of 2Vdc. The operation of switches S H1 and S H4 in an H-Bridge produces a positive level of voltage. The output voltage is 2V dc , i.e., +266.66 volts. Mode-3: In this mode, the switches S 5 , S H1 , S H4 are in conduction state; hence the path follows: S H1 -S H4 -S H5 . No DC voltage source acts in the circuit produce 0V dc output voltage. Mode-4: In this mode, the switches S 5 , S H3 , S H2 are in conduction state; hence the path follows: S H1 -S H4 -D 5 . As no DC voltage source acts in the circuit, produce 0V dc output voltage. Mode-5: In this mode, the switches S 1 , S 4 , S 3 , S H2 , S H3 are in conduction state; hence the load current I o path is through V 1 -S H3 -S H2 -D 3 -V 3 -D 4 -D 1 . The voltages V 1 , V 3 act in the circuits resulting in the formation of 2Vdc. The operation of switches S H3 and S H2 in an H-Bridge produces a negative level of voltage. The output voltage level is 2V dc , i.e., -266.66 volts. Mode-6: In this mode, the switches S 1 , S H3, S H2 are in conduction state; hence the load of current I o passes through V 1 -S H3 -S H2 -D 3 -V 3 -D 2 -V 2 -D 1 . As the voltage sources V 1 , V 2 , V 3 . Acts in the circuit produced an output voltage of 3V dc . The operation of switches S H3 and S H2 in an H-Bridge produces a negative level of voltage. The output voltage level is −3V dc , i.e., −400V. It shows the standard output voltage waveform in Fig. 8(g). The respective switching table for the developed 7-level MLI is illustrated in Table II. It shows the simulation and experimental obtained results in Fig. 9(a) & (b). The hardware specifications used in the design of five levels of MLI are shown in Table I.

B. PROPOSED 7-LEVEL MLI
The proposed 7-level MLI is designed with a developed fundamental unit with the addition of one extra switch S 6 connected parallel to the series combination of the switch S 1 and  voltage V 1 . The circuit contains a fewer number of switches compared with the existing topologies. This topology has ten switches with three DC sources without capacitors, diodes shown in Fig. 10. The power quality issues like THD, a smaller number of switches, dv/dt stress are minimized with this developed multilevel inverter.
In this module, the developed MLI operation is illustrated in detail in Fig. 11 with the steady-state voltage levels in several modes of operation. Here, all the DC source voltages are having equal magnitude, i.e., V 1 = V 2 = V 3 = V dc = 133.33V. Mode-1: In this mode, the switches, S 1 , S 2 , S 3 , S H1 , S H4 are in conduction state; hence the load current I o path is through V 1 -S H1 -S H4 -D 3 -V 3 -D 2 -V 2 -D 1 . As all the dc sources are of the same magnitude, the addition of V 1 , V 2 , V 3 voltages can produce 3V dc . The operation of switches S H1 and S H4 in an H-Bridge produces a positive level of voltage. The output voltage level is +3V dc , i.e., +400 volts. Mode-2: In this mode, the switches S 2 , S 3 , S 6 , S H1 , S H4 are in conduction state; hence the load current I o path is through V 3 -D 2 -V2-S 6 -S H1 -S H4 . The voltages V 2 , V 3 act in the circuits resulting in the formation of 2V dc .The operation of switches S H1 and S H4 in an H-Bridge produces a positive level of voltage.    i.e., V o = −133.33 volts. Mode-7: In this mode, the switches S 2 , S 6 , S H3 , S H2 , S 3 are in conduction state; hence the load of current I o passes through V 3 -D 2 -V 2 -S 6 -S H3 -S H2 -D 3 . As two voltage sources V 2 , V 3 acts in the circuit produce an output voltage of 2V dc . The operation of switches S H3 and S H2 in an H-Bridge produces a negative level of voltage. The output voltage level is −2V dc , i.e., V o = −266.66V. Mode-8: In this mode, the switches S 1 , S H3 , S H2 , S 3 , S 2 , S 1 are in conduction state; hence the load of current I o passes through V 1 -S H3 -S H2 -D 3 -V 3 -D 2 -V 2 -D 1 . As two voltage sources V 1 , V 2 , V 3 acts in the circuit produce an output voltage of 3V dc . The operation of switches S H3 and S H2 in an H-Bridge produces a negative level of voltage. The output voltage level is −2V dc , i.e., V o = −400V. It shows the typical output voltage waveform in Fig. 11(i). The developed MLI operation can be viewed from the switching pulses generated according to the operation of switches. It can power the state of switches with '1' or '0'. If the state of the switch is in '1', we turn it on. If the state is in '0', it resembles it turns the switch off. The respective switching table for the developed 7-level MLI is illustrated in Table III. We design the MLI with three equal magnitudes of voltages: V 1 , V 2 , V 3 having 133.33V each, therefore the 400V, 4A output voltage, and current with a load resistor of 100 . It shows the simulation and experimental obtained results in Fig. 12(a) & (b). With this arrangement, it is easy to get seven levels of output with which the power quality increases with a reduced THD. Table shows the hardware specifications used in the design of seven-level MLI I.

C. PROPOSED 15-LEVEL MLI
The proposed 15-level MLI is designed with two developed fundamental units in cascade without the addition of circuit components. This topology consists of sixteen switches with seven DC sources without capacitors, diodes shown in Fig. 13. The power quality issues like THD, less number of switches, dv/dt stress are minimized with this developed multilevel inverter. The switches S H1 , S H2 , S H3 , and SH4 are connected in an H-Bridge, where the negative voltage levels can be produced. The 15 levels developed circuit is shown in Fig. 13. The operation of switches is shown in Table III and a few modes of operation of the developed 15 levels MLI is represented in Fig. 14, the expected output voltage waveform is shown in Fig. 14.
The developed MLI operation can be simply viewed from the switching pulses generated according to the operation of switches. It can power the state of switches with '1' or '0'. If the state of the switch is in '1', we turn it on. If the state is in '0', it resembles it turns the switch off. The respective switching table for the developed 15-level MLI is illustrated in Table IV. We design the MLI with three equal magnitudes of voltages: V 1 , V 2 , V 3 having 58V each, therefore the 400V, 4A output parameters with a load resistor of 100 .
We simulate the developed cascaded MLI in MATLAB. The developed two units cascaded fifteen-level multilevel inverter simulation is shown in Fig. 14. It makes all the DC sources to be constant of 58V, concerning this voltage, the waveforms of the voltage and current are got and shown in Fig. 17. Initially, the switches S 51 of unit-1, S 52 of unit-2, and S B are turned on. As it connects no DC voltage source in the circuit, the voltage becomes 0V. The switch S 51 of unit-1, S 52 of unit-2, and S A are turned on, where the voltage source V A acts alone in the circuit forms an output voltage of +57V with the H-Bridge operation of S H1 and S H4 gives positive VOLUME 8, 2020    V 21 , V 31 , V 12 , V 22 , V 32 , and V A acts in the circuit, getting the output voltage of +400V with the H-Bridge operation of S H1 and S H4 producing positive voltage levels. We get hence the positive cycle of output voltage waveform. For obtaining, the negative cycle, the H-Bridge is operated with the switches S H2 and S H3 in all modes of operation of the multilevel inverter. Hence the fifteen levels that can be achieved at the output of MLI with simulation THD are shown in Fig. 15 and Fig. 16 respectively. The simulation and experimental output waveforms and THD can be got shown in Fig. 17, Fig. 18, Fig. 19, and Fig. 20, respectively. With this arrangement, we can get the fifteen levels of output with a smaller number of switches with which the power quality increases with a reduced THD. The developed cascaded fifteen levels multilevel inverter is implemented experimentally and the results with R-Load shown in Fig. 20, with L-Load shown in Fig. 21, with R in parallel with L load shown in Fig. 21, Fig. 22 shows the output waveforms with L in parallel with R load. The load is with a resistance of 100 are verified with a simulation output waveform, and the respective THD from simulation and experimental are got shown in Fig. 23 and Fig. 24. It shows the experimental setup in Fig. 25. It shows the hardware specifications used in the design of fifteen levels of MLI Table I.

V. POWER LOSS CALCULATION
The crucial power loss of switches in MLIs are from conduction and switching losses [13] the switching losses and VOLUME 8, 2020    conduction losses dominate high switching frequencies are more effective in low switching frequency. Conduction loss of IGBT with antiparallel diode is because of the on-state condition of resistance and voltages of both transistors and diode. When V S is applied to switches, R S , R d is the internal resistances of the transistor, diode respectively and V d is the on-state voltage. The conduction losses (P c ) of diode P cd and transistor P cs are determined as follows [18], [39] where β is a constant calculated from characteristics of a power switch. Assuming, there are N s,on switches and N d,on diodes are conduction at the time of instant 't' then the multilevel    (20) In the proposed MLI topology there is a bi-directional switch S a , and it conducts at the time of instant't' then the average  conduction losses are [18], [39]

+ N d,on (t) {V d i (t) + R d i(t) i(t)dt
Consider the output current is sinusoidal, then The simplified average conduction losses of a bi-directional switch can be calculated from equation (20) and (21) Therefore, total conduction losses P c of MLI topology is obtained as equation (20) and (23) P C = P CU + P CB (24) The energy losses especially during on and off-states of the switches results in switching losses for a switching period of a switch. Hence there is a linear variation in voltage and current are related as follows [12], [17] where T is a total time period and P sw,on , P sw,off are on-state, and off-state switching losses, t on , t off are the on, and off-state time periods respectively, and V sw. is the peak voltage of the switch hence total switching losses P sw of multilevel inverter is expressed as P SW = P SW,ON + P SW,OFF Thus, the combination of conduction and switching losses gives the total power loss P L ; it can be expressed as Further, the efficiency η for the proposed inverter is calculated as [18], [39] η = P Out P in = P Out P Out + P L (29) We can get the output power: P out = V rms * I rms (30)

VI. COMPARISON STUDIES
The symmetrical configuration of the presented MLI is compared with various levels like 5 level, 7 levels, 15 levels symmetrical configuration of the multilevel inverters such as Cascaded H-bridge (CHB), Flying capacitors (FC), Neutral point clamped (NPC) and the several topologies presented. The components with their output voltage levels for correspondent topologies considered is calculated from the equations in Table IV and tabulated in the respective levels of operation tables. And the components count per level factor VOLUME 8, 2020 Form Table VI, even though the number of power switches needed to produce five-level staircase outputs for designed topology is nominally high as considered with other topologies, the ambiguousness of the inverter, THD, power losses gets decreased. Considering that the components count per level factor F ccl value is more; then the topology requires more components to build the desired voltage level thus in the recent investigations, the primary aim is to decrease components count per level factor in the design of multilevel inverter. It is noticed that from Table V the proposed MLI is having fewer components count per level factor F ccl as related to other nine-level multilevel inverter topologies. Fig. 24 presents the comparison of the number of switches requires producing five-level output voltage steps. From Fig. 24, the introduced topology utilizes fewer switches to correspondence topologies. Minimization of switches reduces the requirement of gate driver circuits for switches and limits components count per level factor F ccl hence reduce the complexity of the inverter. Fig. 24 represents the comparison result of the components count per level factor F ccl to develop a nine-levels of output. From Fig. 24, the proposed topology uses fewer components count per level factor F ccl in correlation with the different topologies. is less as considered with other topologies. Hence there is a reduction of gate driver circuits, so the ambiguousness of the inverter gets decreased. Considering that the components count per level factor F ccl value is more; then the topology requires more components to build the desired voltage level thus in the recent investigations, the primary objective is to decrease components count per level factor in the design of multilevel inverter. It is noticed that from Table III the proposed MLI is having fewer components count per level factor F ccl as related to other seven-level multilevel inverter topologies. Fig. 10 presents the comparison of the number of switches requires producing seven-level output voltage steps. From Fig. 10, the introduced topology utilizes fewer switches to correspondence topologies. Minimization of switches reduces the requirement of gate driver circuits for switches and limits components count per level factor F ccl hence reduce the complexity of the inverter. Fig. 28 represents the comparison result of the components count per level factor F ccl to develop a seven-level output. From Fig. 28, the proposed topology utilizes fewer components count per level factor F ccl in correlation with the different topologies.

C. COMPARISON STUDIES FOR 15 LEVEL MLI
Form Table VIII the number of power switches needed to produce 15-level staircase outputs for designed topology is less as considered with other topologies. Hence there is a reduction of gate driver circuits, so the ambiguousness of the inverter gets decreased. Considering that the components count per level factor F ccl value is more; then the topology requires more components to build the desired voltage level thus in the recent investigations, the primary objective is to decrease components count per level factor in the design of multilevel inverter. It is noticed that from Table VIII the proposed MLI is having fewer components count per level factor F ccl as related to other nine-level multilevel inverter topologies. Fig. 4 presents the comparison of the number of switches requires producing 15-level output voltage steps. From Fig. 26, the introduced topology utilizes fewer switches to correspondence topologies. Minimization of switches reduces the requirement of gate driver circuits for switches and limits components count per level factor    F ccl hence reduce the complexity of the inverter. Fig. 26 represents the comparison result of the components count per level factor F ccl to develop a 15-level output. From Fig. 26, the proposed topology utilizes fewer components count per level factor F ccl in correlated with the different topologies.
Therefore, the power losses and efficiency are calculated from equations 28 and 29. The total losses of five, seven and fifteen level MLI are 44.12W, 49.05W and 77.6W respectively, which includes conduction losses of 44.072W, 48.96W and 77W and switching losses of 0.054W, 0.088W and 0.315W respectively. The efficiencies of five, seven and fifteen level MLI are calculated as 94.76%, 94.26% and 93.87% respectively and represented in Fig. 27.

VII. CONCLUSION
The hybrid cascaded multilevel inverters with five, seven and fifteen levels with PEMFC powered systems are developed mathematically with simulation and experimental verification. A new control strategy, an adaptive neuro-fuzzy interference system (ANFIS) is implemented for the boost converter with which the output is accurate with the learning ability of the controller and is designed and realized. Efficiency and power loss for each multilevel inverter are calculated mathematically. The proposed topology gives good results in the reduction of power switching components, THD, driver circuits, stress on the devices and switching losses compared with the other topologies of multilevel inverters and generalized representation of these factors is illustrated. Simulation of boost converter for PEMFC input is presented to regulate the fuel flow input to meet the desired output voltage with proper care on the transients occurring in the fuel stack. Single-phase multilevel inverters with hardware prototypes of five, seven, and fifteen levels and a boost converter with a fuel cell input are developed. The hardware results under dynamic loads are validated. To test the robustness of the proposed topology load disturbance test is conducted and observed that it is well stabilized for these conditions. Five, seven, and fifteen level MLI are compared with various existing topologies and provide many advantages in various factors in the design of MLI. The proposed topologies provide efficient results with a fuel cell stack.