Parametric Analysis and Optimization of a DC Current Flow Controller in Meshed MTDC Grids

A DC current flow controller (CFC) in a multi-terminal high-voltage direct current (HVDC) (MTDC) grid has the functionality of adjusting and optimizing the power flow on the DC lines. In this paper, the impact of DC CFC parameters on the system stability and dynamic performance is analyzed with three contributions: 1) a mathematical model and a small-signal model of the DC CFC in a meshed MTDC grid are derived; 2) considering the impact of controller parameters on gain margins, phase margins, and cut-off frequencies, the stability analysis is performed in the frequency domain and a parametric optimization scheme is proposed with the deployment of the control variate method and scanning method; 3) a method is proposed to determine the size range and the voltage reference of the common capacitance based on their influence on dynamic behaviors. Two DC CFC equipped multi-terminal meshed HVDC grids are established in PSCAD/EMTDC. The simulation results justify the effectiveness of the theoretical analysis. The proposed parametric selection scheme is demonstrated by dynamic responses shown in the comparative studies.


I. INTRODUCTION
In the past several decades, there has been an increasing number of high-voltage direct current (HVDC) transmission lines in power systems. Most of the HVDC systems have two terminals, including types of line-commutated converter (LCC) and voltage-sourced converter (VSC) [1]- [3]. Several multi-terminal HVDC (MTDC) systems have emerged to enhance the transmission capacity and reliability, such as the European supergrid project [4] and China Zhou'shan fiveterminal HVDC project [5]. Following the history of AC networks, the DC lines are developing gradually from pointto-point connections to multi-end radial connections, and will finally form meshed DC networks. A generalized MTDC grid, including different types of converters, is shown in Fig.  1.
In comparison with the conventional AC grid, there are still many existing problems for DC power systems after forming meshed topologies, particularly the issue of current/

FIGURE 1. A generalized MTDC grid
power flow control [6]. The control of DC current flow can only be conducted through the regulation of the line terminal voltage and the line resistance, since there is no reactive power, reactance or phase angle in the DC system. In a meshed MTDC network, it is undesired that some DC lines are operating close to its maximum limits or even overloaded, while other DC lines are underutilized. Therefore, it is essential to introduce DC current flow control devices so as to enhance the control degrees of freedom and to optimize the power flow distribution in MTDC grids.
As aforementioned above, the DC power flows in an MTDC network are mainly determined by the line resistances and line terminal voltages. Hence, the DC current flow control approach can be generally classified into two categories, i.e. by means of (a) adjustable resistors; (b) controllable voltage sources.
The concept of method (a) is by changing the equivalent DC line resistance, i.e. inserting variable resistor(s) into a DC line. This method was firstly proposed in [7] and could accurately control the power flow with easy implementation. However, its drawbacks were (i) large power losses due to frequent switching-in resistance and (ii) the lack of capacity to achieve bi-directional control of DC power flow because of the unidirectional increase of line resistance.
For method (b), there are two approaches, i.e. by means of (1) using a DC-DC transformer; (2) inserting an equivalent voltage source. The first approach is to put a DC transformer in series into a DC line so as to adjust the DC power flow by varying the voltage ratio between the transformer [8][9][10]. The DC transformer can also be used to interconnect DC networks with different voltage ratings and to isolate DC faults. However, the application of this approach is mainly limited by the high losses and cost, since all power transferred has to pass the DC-DC transformer during the control process.
In comparison with the former approach, method (2), i.e. inserting an equivalent voltage source, is proved to have advantages of lower operational losses and reduced topological complexity [11][12][13][14][15][16][17][18][19][20][21]. This is due to the fact that the control of DC power flow is achieved by changing the line terminal voltages via inserting an adjustable voltage source, not necessitating the control device to undertake all voltage ratings and power transferred. The adjustable inline voltage source can either be provided by external power sources outside the MTDC grid [12][13][14][15], or be achieved by the energy exchanges between adjacent DC lines [16][17][18][19][20][21]. The latter approach is more favored and deployed in practical applications, since it does not require external equipment, which saves both the cost and space. In [16], a new interline DC power flow controller (IDCPFC) was proposed and bi-directional power flow control was achieved. Since modular design was not applied in the IDCPFC, the scalability of the proposed topology was not facilitated. In [17], an m-port DC power flow controller (MDCPFC), which comprised MMC AC/DC converters and an interconnected three-phase three-winding AC transformer, was proposed for DC power flow control without requiring power exchange with an external AC network. However, the requirement of MMC AC/DC converters and AC transformers increased the total cost and space in the MDCPFC. In [18], a cascaded power flow controller (CPFC) with a two-layer control strategy was proposed. The CPFC was proposed with an average model of a DC-DC converter, i.e. controlled current and voltage sources, in which a detailed topology of the CPFC was not provided. In [19], a two-line DC current flow controller (CFC), which comprised two full-bridge DC-DC converter sharing a common capacitor, was proposed. The controllable voltage sources were implemented by altering the current flowing into the common capacitor. The control strategies of the DC CFC under steady-state operating conditions were proposed in [20]. A small-signal model and control system designed were developed in [21].
This paper further investigates the parametric selection and optimization of the DC CFC in a meshed MTDC grid with the main contributions as follows. 1) Regarding a two-line DC CFC equipped three-terminal HVDC grid, a mathematical model and a small-signal model are derived; 2) The system stability in the frequency domain is analyzed. The impact of parametric selections of the proportional gains and integral gains in the control systems of the DC CFC on the gain margins and phase margins is analyzed. A parameter optimization scheme is proposed; 3) The impact of the parametric selections of the common capacitor of the DC CFC and the capacitor voltage reference setting on the system dynamic performance is analyzed. A principle regarding the selection of the parameters is proposed. The rest of this paper is organized as follows. Section II introduces the system configuration. A comprehensive mathematical model is derived with the calculations of steady-state operating points. A small-signal model is derived in Section III and the system stability is analyzed in the frequency domain. The impact of the control parameters of the DC CFC on the system gain margins and phase margins is analyzed in Section IV and a parameter optimization scheme is proposed. In Section V, the impact of the parameters of the DC CFC on system dynamic behaviors is analyzed. In addition, a principle of the selection ranges of the common capacitor and capacitor voltage reference is proposed. Fig. 2(a) shows a three-terminal meshed HVDC grid equipped a two-line DC CFC. T n (n = 1, 2, 3) denotes each terminal of the MTDC system; MMC-n denotes the MMC at each terminal; SM-k (k = 1, 2) denotes the DC-DC converter in the DC CFC. Fig. 2    According to Fig. 3 and Table I, the relationship between the switching modes, m i (i = 1, …, 4) and the duty cycles, d j (j = a, …, d) can be derived as follows:

A. SYSTEM CONFIGURATION
The inserted voltage source e 12 and e 13 can be controlled by duty cycles of G sc1 and G sc2 , i.e. d c1 and d c2 .
In terms of the common capacitor in the DC CFC, it is charged/discharged under mode 2/3, which yields: The fact that the DC CFC achieves DC network current flow control by means of currents exchanges via the energy hub (common capacitor) can be observed in (4). An equivalent circuit diagram of the DC CFC represented in the form of controlled current sources is illustrated in Fig. 4.

FIGURE 4. Equivalent circuit diagram of a two-line DC CFC
The mathematical model of a two-line DC CFC equipped three-terminal meshed HVDC grid shown in Fig. 2(a) can be derived according to the Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL) as follows: 1  12  12  12  1  2  12  12  12  12   13  13  2  1 3  1  3  13  13  13  13   23  23  23  2  3  23 23 23 It can be abbreviated into the state-space form: The matrices A, B, C and D are listed in Appendix A.

C. STEADY-STATE OPERATING POINTS
Since the main focus of this paper is parametric analysis and optimization of the two-line DC CFC, the dynamics of AC systems and converters at terminals are not considered. Their functions are regarded as equivalent DC voltage/current sources (T 1 and T 2 apply constant current control, while T 3 applies constant DC voltage control). The steady-state relationship between u and y is : Use the expressions of matrices A, B, C and D, yields: where i 1 , i 2 , v 3 are input from the terminals; i 12 , v c are output variables with the references determined by the control objectives of the DC current flow. Taking the parameters listed in Table II

A. SMALL-SIGNAL MODEL
A small-signal model (9) is obtained by adding a small perturbation around the steady-state operating point.
where both d c1 and d c2 are regarded as input variables with perturbations, i.e. ∆u is separated into two parts, ∆uc and ∆ud. The input variables, output variables and state variables in the small-signal model are as follows:   There is one system eigenvalue located in the right-half splane, which indicates the system is unstable. Additional control is required to achieve the correction of the system stability.  The open-loop transfer function of the control system concerning the input variable of Δuc can be obtained. 11 (11) The stability of a minimum phase system (MPS) can be evaluated by the analysis of its Bode diagram. According to the definition of an MPS [22][23], i.e. a minimum-phase system does not have poles or zeros in the right-half s-plane or on the jω-axis, excluding the origin, the poles and zeros of the open-loop transfer function of the two-line DC CFC are calculated to check whether the system is an MPS. The diagonal matrices, gc_op 11 Table IV.   Fig. 6, the phase margin of gc_op 11 is close to 90 degrees, which indicates that the response of i 12 is stable. However, the phase margin of gc_op 22 is -90 degrees, which indicates that the response of v c is unstable, necessitating additional control strategies to correct the performance of v c .
The stability can be improved by providing a phase shift on the associated element of the input Δuc. In addition, to eliminate the steady-state error of both i 12 and v c , a matrix E with PI controller is designed preliminary to the input Δuc as shown in the green area in Fig. 5. The expression of E is: where the diagonal matrix E 22 has a phase shift of -180º which is achieved by timing -1. In the open-loop system with matrix E, the input variable is changed from Δuc to Δer, where Δer is the error signal of the input references and measurements:

Δe Δy
Δy (12) A unity feedback matrix F is used to form a close-loop control system as shown in Fig. 5. In the close-loop system, the input variable becomes Δyref. The addition of the control matrix E can significantly enhance the system stability.   In Fig. 7, the black solid line shows the gain margin and phase margin of i 12 , while the blue dashed line shows the gain margin and phase margin of v c . With matrix E in which the parameters of the PI controllers are K p1 = K p2 = 1, K i1 = K i2 = 50, the phase margin of v c is changed from -90º to 76.7º and both the gain margins and phase margins of i 12 and v c are now positive, which indicates the stability of the system. In addition, the gain margins of both i 12 and v c become infinite after adding matrix E, which indicates that the gain margins of the system are sufficiently large and the changes of the phase margins may have more impact on the system stability and dynamic behaviors. Hence, in the following analysis, the impact of the system parameters on the phase margins is mainly investigated. From Table III, all the eigenvalues of the system under steady-state operating point locate on the left-half s-plane with adding matrix E. Since matrix E defines the dependency of Δuc on Δer, the parametric selection of matrix E is important and has great impact on the system stability and dynamic performance.

A. OPTIMIZATION OF PROPORTIONAL GAINS
A study on the impact of parametric selection of matrix E on the phase margin is conducted. In order to exploit the influence of each parameter, the control variate method and scanning method are deployed. Initially, the parameters of the integral gains K i1 and K i2 are fixed at 50, while the proportional gains K p1 and K p2 are gradually increased from 1 to 20 with an interval of 0.5. The tendency of changes of the phase margins and cut-off frequency can be scanned and observed. The changes of phase margins with the increase of the proportional gains are presented in Fig. 8. Table V presents several typical points of Fig. 8.  When K i is fixed at 50 while increasing K p , the phase margins of both i 12 and v c increase. In addition, the phase margins increase significantly at the initial stage and gradually slow down when K p is greater than 5. The cut-off frequencies almost increase linearly with the increase of K p . Based on the typical selection principle of phase margins in practical engineering [22] and synthesizing the dynamic behavior of the phase margins and cut-off frequencies of both i 12 and v c , the principle of the selection of K p is made to keep the phase margins larger than 70º while the cut-off frequency smaller than 500 rad/s. The eligible ranges of K p1 and K p2 are [2,5] and [1,2], respectively. K p is temporarily selected as 2 for subsequent analysis.

B. OPTIMIZATION OF INTEGRAL GAINS
Similarly, in order to identify the impact of the integral gains on the phase margins, the parameters of K p1 and K p2 are fixed at 2, while K i1 and K i2 are increased between ranges of 0 to 2000 with an interval of 50. The changes of phase margins with the increase of the integral gains are presented in Fig. 9. Table VI   When K p is fixed at 2 while increasing K i , the phase margins of both i 12 and v c decrease. In addition, the phase margins decrease significantly at the initial stage and gradually slow down when K i is greater than 500. The cut-off frequencies almost increase linearly with the increase of K i , while the growing slope is mild. Similarly, the principle of the selection of K i is made to keep the phase margins larger than 70 while the cut-off frequencies smaller than 500 rad/s. The eligible ranges of K i1 and K i2 are [0, 50] and [0, 200], respectively. K i is selected as 50 for the following analysis.

A. PARAMETRIC ANALYSIS OF DC CFC
For a two-line DC CFC, the control of DC power flow is achieved through energy exchange of adjacent DC lines. The energy exchange hub is the common capacitor which connects both full-bridges and can also be regarded as an energy router. The stored energy W c of the common capacitor C cfc due to charging/discharging comply with the following mathematical relationships: (14) where p c is the instantaneous charging/discharging power of the capacitor, v c , i c is the voltage and current of the capacitor, respectively, t is the time period. Regarding other energy storage components, particularly electrochemical energy storage devices, e.g. lead-acid batteries and lithium batteries cannot absorb/release instantaneous high currents, due to the limitations of electrochemical mechanisms [24,25]. For capacitors, they can conduct fast charging/discharging operation. Moreover, they can conduct in-depth charging/ discharging operation, i.e. significant change of voltages [26]. The change of stored energy of a capacitor, ΔW c , is determined by the difference of the squared capacitor voltage, that is: where W c1 and v c1 are the stored energy and voltage at a former stage, W c2 and v c2 are the stored energy and voltage at a later stage. In comparison with other energy storage devices, large power exchange could be achieved with a small capacitor, which meets the requirement of bulk-power transmission via DC lines. In addition, capacitors allow significant changes of voltages within a short period, i.e. high-speed charging/discharging performance or high frequency charging/discharging operation. Thus, it can implement fast distribution of energy among the DC lines. The parametric selections of the capacitance and the capacitor voltage reference are of great importance to the performance of the two-line DC CFC.
 The capacitance indicates the energy storage capability of the common capacitor, as shown in (13). The energy storage capability may not be sufficient to achieve efficient energy exchange with too small capacitance. However, too large capacitance may result in unexpected large overshoots and increase in duration of DC voltages and currents to reach new steady states. In addition, the volume, size and cost of the capacitor will increase.
 Regarding the control reference setting of the common capacitor, it is also an important index for evaluating the energy storage capability of the capacitor, since the energy storage of the capacitor is directly proportional to its voltage square as shown in (13). When the two-line DC CFC is operated to control the DC line currents by means of energy exchange, one full-bridge DC-DC converter (SM-1) applies constant current control to regulate the line current, while the other full-bridge (SM-2) applies DC voltage control to stabilize the voltage of the common capacitor, i.e. SM-2 operates as a slack bus to stabilize the capacitor voltage while sending/receiving power as required. Hence, the stabilization control of the capacitor voltage and mitigation of the voltage fluctuations are essential for stable operation.

B. SELECTION OF THE CAPACITANCE
In order to analyze the impact of the capacitance on the phase margins, the control variate method and scanning method, are deployed. The parameters of K p and K i are fixed at 2 and 50, respectively, while C cfc , the capacitance of the common capacitor, is increased between ranges of 10 µF to 10 mF with an interval of 20 µF. The changes of phase margins with the increase of C cfc are presented in Fig.  10. Table VII presents several typical points of Fig. 10.
When K p and K i are fixed while increasing C cfc , the phase margin of i 12 increases while that of v c decreases. For the phase margin of i 12 , it increases significantly at the initial stage and gradually slows down when C cfc is greater than 2 mF. For the phase margin of v c , it decreases with a slope of 3.5 when C cfc increases from 10 µF to 3.4 mF and decreases significantly with a slope of 10.8 when C cfc increases from 3.4 mF to 4.4 mF, and gradually slows down when C cfc is greater than 4.4 mF. The cut-off frequencies both decrease with the increase of C cfc . Since PM-1 is increasing while PM-2 is decreasing with the increase of C cfc , the intersection point of both PMs can be evaluated if it is appropriate as the optimal C cfc with the same principle. The capacitance at the intersection point is 2.2 mF and the PMs are both 81º with the cut-off frequencies both at 229 rad/s, which satisfy the pre-defined principle. Thus, 2.2 mF capacitance is selected for the subsequent analysis.

C. CAPACITOR VOLTAGE REFERENCE
The impact of the voltage reference settings of the common capacitor on the phase margins is analyzed. Similarly, the parameters of K p and K i are fixed at 2 and 50, respectively, and the common capacitance is fixed at 2.2 mF, while the voltage reference V cref of the common capacitor is increased between ranges of 0.5 kV to 20 kV with an interval of 0.5 kV. The changes of phase margins with the increase of V cref are presented in Fig. 11. Table VIII presents several typical points of Fig. 11.   Fig. 11 shows that the phase margin of i 12 increases while the phase margin of v c decreases, the varying pattern of which is similar to that in Fig. 10. For the phase margin of i 12 , it increases significantly at the initial stage and gradually slows down when V cref is greater than 5 kV. For the phase margin of v c , it decreases with a slope of 1.71 when V cref increases from 0.5 kV to 8.5 kV and decreases significantly with a slope of 24.5 when V cref increases from 8 kV to 8.5 kV, and gradually slows down when V cref is greater than 9 kV. The cut-off frequency of PM-1 decreases initially to a minimum of 186 rad/s (V cref = 2.5 kV) and increases afterwards, while the cut-off frequency of PM-2 decreases with the increase of V cref . Since PM-1 increases while PM-2 decrease with the increase of V cref , the intersection point of both PMs can be taken as the optimal V cref . The V cref at the intersection point is 5.0 kV and the PMs are both 81.0º with the cut-off frequencies at 229 rad/s. Thus, the selected V cref also keeps the preset principle.

VI. SIMULATION SYSTEM AND RESULTS
In order to evaluate the effectiveness of the proposed optimal parametric selection scheme, a three-terminal HVDC system with the integration of a two-line DC CFC on DC Line 12 and Line 13 is established on the timedomain simulation environment PSCAD/EMTDC. The detailed system parameters were provided in Table II. The control strategies of the HVDC converter stations and the DC CFC were described in Section II-C.
Nine case will be studied with three types of incidents, i.e. step changes of i 12ref , disturbances at T 1 , and disturbances on Line 13. In each incident, three different parametric selections will be evaluated, i.e. PI parameters, capacitance of the common capacitor, and voltage reference of the common capacitor. The arrangement of the 9 cases are listed in Table IX.

A. PARAMETRIC SELECTIONS OF PI CONTROLLERS
In this section, three cases are conducted to investigate the system response of the three types of incidents with different parametric selections of PI controllers.

1) STEP CHANGES OF I12REF
In this case, the system response under a step change of i 12 is simulated with different parametric selections of the proportional gains K p and integral gains K i . Initially, the DC CFC is in bypass mode. According to the control reference settings of the converters at each terminal and the DC line parameters in Table II, the initial value of i 12 can be calculated at 1.25 kA. The DC CFC is activated at 0.5 s with i 12ref at 0.8 kA and v cref at 5 kV. At 1.5 s, i 12ref is stepped up to 1 kA and resumes 0.8 kA at 2.5 s. Simulation results with different K p and K i are presented in Fig. 12 and Fig. 13. When the DC CFC is bypassed, no current flows into the common capacitor, thereby resulting zero v c before 0.5 s as shown in Fig. 13. The DC currents are naturally distributed according to the line resistance. Fig. 12 shows that i 12 is 1.25 kA before 0.5 s, which is consistent with theoretical analysis. At 0.5 s, the DC CFC is activated. When K p is 0.2 and K i is 50, both i 12 and v c cannot reach the new steady state within 0.5 s. The oscillations are significant with overshoots of 35% in i 12 and 108% in v c . When K p is 2 and K i is 500, i 12 can be stabilized within 0.3 s with an overshoot of 25% and v c can reach the new steady state within 0.2 s with an overshoot of 80%. Both i 12 and v c can be controlled with stepping up/ down control. When K p is 2 and K i is 5, the overshoots during transients become smaller. However, it takes over 1 s for i 12 to reach a new steady state, while v c can reach a new steady state within 0.6 s. When K p is 2 and K i is 50, both i 12 and v c can be stabilized within 0.2 s with overshoots of 5% in i 12 and 32% in v c . When K p is 20 and K i is 50, both i 12 and v c can be stabilized within 0.1 s with overshoots of 1% in i 12 and 20% in v c . Hence, the simulation results shown in Fig. 12 and Fig. 13 indicate the effectiveness of the proposed optimized parameters (K p = 2, K i = 50) and demonstrate that the dynamic behaviors can be further improved with the increase of K p . This is because with the increase of K p , the cut-off frequency will increase and exceed the preset value of 500 rad/s. It will indeed enhance the dynamic response, while it does increase the cost and difficulty of the control system design. Therefore, it is appropriate to choose the optimized parameters of K p at 2 and K i at 50. Under the conditions of cost permitting and no technical barrier, the gain K p can be further increased to make the system response even faster.  In this case, the system response under disturbances at T 1 is simulated with different parametric selections of K p and K i . At 0.5 s, DC CFC is activated from bypassing mode with i 12ref at 1 kA and v cref at 5 kV. At 1.5 s, a disturbance signal composed of a sinusoidal magnitude of 0.7 kA and frequency of 2 Hz is added on the DC current source i 1 for 1 s. The simulation results are shown in Fig. 14 and Fig. 15.
The set of K p at 2 and K i at 500 presents least antiinterference capability. This is because the phase margins of i 12 and v c will continually decrease with the increase of integral gain K i . The second least anti-interference capability lays on the set of K p at 0.2 and K i at 50, since the phase margins of i 12 and v c are reduced with smaller K p , which is consistent with previous analysis. The set of K p at 2 and K i at 5 presents strong anti-interference capability with small oscillations during the disturbance, while the slow response from one state to a new steady state is its main drawback. This is because small K i will lead to small cut-off frequency, the value of which determines the response speed of the control system. The rest two parametric sets have better performance in both steady state and anti-interference performance where the set of K p at 20 and K i at 50 has the optimal performance with minimum overshoot, least period of reaching the new steady state and strongest capability of anti-interference. Thus, the simulation results justify the correctness of the theoretical analysis.

3) DISTURBANCES ON LINE 13
In this case, the system response under disturbances on Line 13 is simulated with different parametric selections of K p and K i . The initial condition is the same as that of the previous cases. At 1.5 s, a single-pole to ground fault occurs on DC Line 13, resulting in current loss of 0.8 kA and power loss over 250 MW for 0.5 s. The simulation results are shown in Fig. 16 and Fig. 17.
When the fault occurs from 1.5 s to 2.5 s, both i 12 and v c can be stabilized with the five parametric sets. The optimal control performance in both steady state and transient state lays on the parametric set of K p at 20 and K i at 50.

B. PARAMETRIC SELECTIONS OF CCFC 1) STEP CHANGES OF I12REF
In this case, the system response under step changes of i 12ref is simulated with different parameters of C cfc . The initial condition and the incident are the same as those in Case A1. The simulation results are shown in Fig. 18 and Fig. 19. When C cfc is 100 mF, i 12 and v c cannot be stabilized. It is because with the increased C cfc , the cut-off frequency of v c reduces significantly, leading to tardy response of v c and i 12 . When C cfc is 0.01 mF, i 12 can be rapidly stabilized, while v c persists significant oscillations. When the other three C cfc values are applied, i 12 and v c can be well stabilized. The C cfc at 2.2 mF presents optimal control performance with smallest overshoot and least period of reaching new steady states.

2) DISTURBANCES AT T1
In this case, the system response under disturbances at T 1 is simulated with different C cfc . The initial condition and the incident are the same as those in Case B1. The simulation results are shown in Fig. 20 and Fig. 21. Two values, 100/0.01 mF, are not considered, since the system cannot be stabilized. The performance is similar using the other three sets. When the disturbance occurs from 1.5 s to 2.5 s, both i 12 and v c can be well stabilized.

3) DISTURBANCES ON LINE 13
In this case, the system response under disturbances on Line 13 is simulated with different C cfc . The initial condition and the incident are the same as those in Case C1. The simulation results are shown in Fig. 22 and Fig. 23. When the C cfc values 1 mF, 2.2 mF and 3.6 mF are used, both i 12 and v c can be well stabilized when the disturbance occurs from 1.5 s to 2 s. The anti-interference capability using three parameters is similar.

C. DIFFERENT VCREF OF THE COMMON CAPACITOR 1) STEP CHANGES OF I12REF
In this case, the system response under step changes of i 12ref is simulated with different V cref . The initial condition and the incident are the same as those in Case A1. The simulation results are shown in Fig. 24 and Fig. 25.
Considering the settings of V cref at 2 kV and 3.5 kV, i 12 cannot be controlled to 0.8 kA after activating the DC CFC at 0.5 s. This is because the energy stored in the common capacitor is relative to its voltage square according to (13). When V cref is selected excessively small, it will directly lead to the reduction of the energy storage in the capacitor, thereby reducing the instantaneous absorbed/ released power. The rest three parametric sets can all achieve smooth control of i 12 . The set of V cref at 5 kV presents the optimal control performance with smallest overshoot during the transition from one steady state to a new one. For the set of V cref at 50 kV, since the initial value of v c is zero when the DC CFC is bypassed, it needs a certain period to rise to 50 kV. This time-consuming transition results in delayed response of i 12 and significant overshoot at the first stepping up control. In addition, obvious current oscillations can be seen when i 12 reaches new steady states. Hence, the simulation results justify the effectiveness of the optimal V cref proposed.

2) DISTURBANCES AT T1
In this case, the system response under disturbances at T 1 is simulated with different V cref . The initial condition and the incident are the same as those in Case B1. The simulation results are shown in Fig. 26 and Fig. 27. When V cref is 2 kV, significant oscillations can be observed when the disturbances occur. It can be seen that with the increase of V cref , the impact out of the disturbance on both i 12 and v c becomes less significant. Synthesizing the simulation results in Case C1 and Case C2, it can be concluded that with the increase of the capacitor voltage reference, the antiinterference capability is enhanced while the steady state performance is degraded. The simulation results verify the proposed optimal parametric selection of V cref at 5 kV.

3) DISTURBANCES ON LINE 13
In this case, the system response under disturbances on Line 13 is simulated with different V cref . The initial condition and the incident are the same as those in Case C1. The simulation results are shown in Fig. 28 and Fig. 29. For the sets of V cref at 2 kV and 3.5 kV, i 12 cannot remain the reference settings after the disturbance. With the increase of V cref , both i 12 and v c can be well stabilized. Therefore, synthesizing the dynamic performance of Case C1, C2 and C3, the proposal of V cref at 5 kV is valid.

VII. ANALYSIS AND DISCUSSIONS
Due to the fact that the gain margins of both i 12 and v c are infinite after adding matrix E, the parametric impact on the system stability and dynamic behaviors is mainly analyzed on the phase margins. However, it is essential to justify the condition of the gain margin with the proposed optimal parameters, since the stability of a system is fully determined by both the phase margin and gain margin. The bode diagram of the system with optimal parameters is depicted in Fig. 30. With the proposed optimal parameters, the infinite gain margins are maintained and the phase margins are both around 81º, which is consistent with the theoretical analysis in Section V. Hence, it is justified based on the theoretical analysis and simulation results that the principle of parametric selections and optimizations enlarges both phase margins and cut-off frequencies of i 12 and v c . The increase of phase margins will enhance the stability margins of the system, while the increase of cut-off frequencies will expedite the system response. Regarding the parametric selections of three types of variables, i.e. proportional and integral gains, capacitance, and capacitance voltage reference, the increase of the proportional gains will enhance both phase margins and cut-off frequencies of i 12 and v c . Hence, under the permission of technical level and cost, K p can be set up as large as possible. The increase of integral gains will reduce the phase margins of i 12 and v c while increase their cut-off frequencies, resulting in enhancing the system response speed while scarifying the system stability margin and anti-interference capability. Hence, the selection of K i should be moderate, i.e. neither too large nor too small. The increase of the common capacitance will lead to increase of the phase margin of i 12 . However, it will decrease the phase margin of v c and the cut-off frequency of both i 12 and v c . That means the changes of the capacitance will have direct impact on the response speed. Hence, the selection of C cfc should also be moderate. The increase of V cref will optimize the performance of i 12 , i.e. enhance both the phase margin and cut-off frequency of i 12 , which increases its stability margin and response speed. However, it will deteriorate the behavior of v c , i.e. decrease its phase margin and cut-off frequency, which narrows the stability margin and reduce the response speed. Hence, the selection of V cref should be moderate. In addition, the selection of V cref has direct impact on the voltage level in operating the DC CFC and the requirement on the insulation level. The simulation results indicate that the parametric selection of V cref at 5 kV can achieve optimal dynamic behaviors in both steady state and transients. This voltage level is only less than 2% of that of the typical HVDC transmission grid. The design of the DC CFC has the merit of modular structure and the flexible technique of energy exchange applied for the control of DC line currents in the meshed grid, which realize the features of lower cost and easier implementation for practical engineering.

VIII. CONCLUSIONS
In this paper, regarding a two-line DC CFC integrated threeterminal HVDC grid, a small-signal model has been established for stability analysis in the frequency domain. The impact of the proportional gains and integral gains on the phase margins has been quantitatively analyzed with the deployment of control variate and scanning approaches. An optimal parametric selection of K p and K i has been proposed. In addition, the impact of the capacitance and voltage reference of the common capacitor on the phase margins and dynamic behaviors has been analyzed. A principle of the parametric selection ranges regarding the capacitance and voltage reference has been proposed with a set of optimal parameters. Finally, the theoretical analysis and optimized parameters have been evaluated on the PSCAD/EMTDC. The simulation results have justified the effectiveness of the proposed method. The principle of the parametric selection ranges and optimal parametric selection method proposed can be applied for multi-line DC CFCs (see Appendix B).

APPENDIX A
The expressions of A, B, C, D, and A2, Bc, Bd, C2, Dc, Dd are as follows.

APPENDIX B
In order to verify the proposed parametric optimization scheme in more complex DC grids, a three-line DC CFC equipped four-terminal meshed HVDC grid, as illustrated in Fig. 31, is analyzed.

FIGURE 31. A four-terminal meshed HVDC with a three-line DC CFC
In the four-terminal system, T 4 applies DC voltage control to maintain the DC voltage of the MTDC grid, while the other three terminals apply constant DC current control to import/export active power to/from the DC grid. The dynamics of the converters and the AC sides are not considered. It implies that prompt response is assumed for both LCCs and VSCs, and they can maintain ideal states at the DC sides. For the normal operation mode of LCC-based DC lines, the rectifier adopts constant current control, while the constant voltage control or the minimal extinction angle control is employed by the inverter. The same is true for the VSC-based DC lines, where the DC current is controlled by the rectifier and the DC voltage is usually maintained by the inverter. Hence, it is reasonable to adopt constant current source or constant voltage source as the DC equivalence of converter, the type of which does not matter, when the converters at terminals response rapidly. On the other hand, for an AC/DC power system, the task of power flow control can be divided into two levels. At the system level, the AC power flow is optimized and the real power desired to be transmitted by DC lines/networks is determined. Then at the second level, power flow distribution among the DC lines is considered. This paper investigates the method to implement the second level power flow control, i.e. DC current/power flow control. At the present stage, it is necessary to simplify the AC system and the terminals to reduce the complexity in DC current flow control study.
The approach proposed in this paper can be applied for MTDC grids with different types of converters at the terminals, e.g. T 1 can be a rectifier of an LCC terminal, while T 2 , T 3 and T 4 are VSC terminals. As a demonstration, the impact of the PI parameters on the margins of the system undergoing a current step change will be investigated.
The mathematical model and the small-signal model are obtained by the same approach described in Section II and III. In order to achieve full controllability of branch currents in the four-terminal DC grid, the three-line DC CFC has to regulate two out of three DC branch currents, i.e. two of i 12 , i 13 , i 14 . In the following analysis, the three-line DC CFC is used to regulate i 12 and i 13 , and to control the voltage of the common capacitor. The four-terminal system with the DC CFC is verified as an MPS. The system parameters are shown in Table X. The values of d c1 , d c2 and d c3 can be obtained (d c1 = 0.34, d c2 = 0.66, d c3 = 0.50) using the similar approach as (7) and (8). The Bode diagrams of i 12 , i 13 and v c without/with matrix E, in which the parameters of the PI controllers are K p1 = K p2 = K p3 = 1, K i1 = K i2 = K i3 = 50, are illustrated in Fig. 32  In Fig. 32, the gain margins of i 13 and v c are both negative and the phase margin of v c is negative, indicating that the response of i 13 and v c is unstable. With the addition of matrix E with PI controllers, the gain margins and phase margins of i 12 , i 13 and v c present positive margins as shown in Fig. 33, which indicates the stability of the system. In addition, the gain margins of i 12 , i 13 and v c are also infinite after adding matrix E, which indicates that the phase margins may have more impact on the system stability and dynamic behaviors.
Hence, the impact of the PI parameters on the phase margins is mainly investigated. Similarly, via the control variate method and scanning method, initially the parameters of the integral gains K i1 , K i2 and K i3 are fixed at 50, while the proportional gains K p1 , K p2 and K p3 are gradually increased between ranges of 1 to 20 with an interval of 0.5. The changes of phase margins with the increase of the proportional gains are presented in Fig. 34. When K i is fixed at 50 while increasing K p , the phase margins of both i 12 and v c increase, while the phase margin of i 13 increases at the initial stage and decreases when K p is greater than 2. Regarding the proposed parametric selection principle, the eligible ranges of K p1 , K p2 and K p3 are [4.5, 20], [1,20] and [0, 20], respectively. Synthesizing the dynamic behaviors of the phase margins of i 12 , i 13 and v c , it is appropriate to select K p as 15, since the phase margins are over 80º and their dynamics tend to be stable.
In order to identify the impact of the integral gains on the phase margins, the parameters of K p1 , K p2 and K p3 are fixed at 15, while K i1 , K i2 and K i3 are increased between ranges of 0 to 2000 with an interval of 50. The changes of phase margins with the increase of the integral gains are presented in Fig. 35. Considering the fact that the integral gains are inversely proportional to the integral time constant and have influence on mitigating the steady-state error, the system response may be very slow and steady-state errors may emerge if the integral gains are selected too small. Synthesizing the dynamic behaviors of the phase margins of i 12 , i 13 and v c and the character of the integral gains, it is appropriate to select K i as 500, since the phase margins are over 70º and K i is sufficiently large to provide rapid system response and eliminate the steady-state error.
The system response under step changes of i 12ref is simulated, which is similar to that of Case A1 in Section VI. Initially, the DC CFC is in bypass mode. The initial value of i 12 can be calculated at 1.85 kA. The DC CFC is activated at 0.5 s with i 12ref and i 13ref both at 1.6 kA and v cref at 5 kV. At 1.5 s, i 12ref is stepped down to 1.2 kA and resumes 1.6 kA at 2.5 s. Simulation results with different parameters of K p and K i are presented in Fig. 36 and Fig. 37  When the DC CFC is in bypass mode, no current flows through the common capacitor, thereby resulting v c at zero before 0.5 s as shown in Fig. 37. The DC currents are naturally distributed. Fig. 36 shows that i 12 is 1.85 kA before 0.5 s, which is consistent with theoretical analysis. At 0.5 s, the DC CFC is activated. When K p is 0.015 and K i is 50, both i 12 and v c have significant oscillations indicating instability of the system, which is consistent with the theoretical analysis of the Bode diagram in Fig. 34. When K p is 15 and K i is 50, i 12 can be stabilized within 0.8 s. Both i 12 and v c can be controlled with stepping up/down control. When K p is 15 and K i is 500, both i 12 and v c can be stabilized within 0.1 s without overshoot, which demonstrates desired performance with the proposed optimized parameters. When K p is 15 and K i is 5, although the dynamic behaviors of both i 12 and v c are stable, i 12 cannot reach the steady state within 1 s. This is because the integral gain is selected too small resulting in slow system response. When K p is 15 and K i is 5000, obvious overshoots can be observed in both i 12 and v c , since a large integral gain can enhance the system response while may lead to the significant overshoot.
The simulation results shown in Fig. 36 and Fig. 37 verify the effectiveness of the proposed optimized parameters (K p = 15, K i = 500). In addition, the validity of the proposed analytical approach for a multi-line DC CFC in the MTDC grid is also justified. It is identified that the parametric selection of a multi-line DC CFC has more coupling effect on the system dynamic behaviors due to more interactions and energy exchanges within the common capacitor. Therefore, the robustness, reliability and advanced controller design for multi-line DC CFCs deserve further research.