A New Multilevel Inverter Topology With Reduce Switch Count

Multilevel inverters are a new family of converters for dc–ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with a lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology, which consists of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count, exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in this paper to demonstrate the features of the proposed topologies. Several experimental results have been included in this paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes.


I. INTRODUCTION
Over the last few decades, multilevel inverter (MLI) topologies have gained popularity in industrial application because of the superior power quality compared to its conventional two-level counterpart. Lower harmonic distortion and better wave quality resembling a sinusoidal wave and lesser voltage stress on the switches have added to its popularity. For low and medium voltage/power applications, MLI find their applications in almost every field of electrical engineering including renewable energy systems, HVDC applications, distributed generation (DG) system, industrial drive applications, uninterruptible power supplies, etc [1]- [3]. They are widely used in drives and other allied areas in industries. MLI's are an assembly of power semiconductor devices along with different dc links to achieve staircase waveform close to sinusoidal at the output. Neutral Point Clamped (NPC), The associate editor coordinating the review of this manuscript and approving it for publication was Tariq Masood.
Flying Capacitor (FC) and Cascade H-Bridge (CHB) are the three basic and popular MLI topologies used in commercial application since last few decades. Although there are few issues with the conventional MLI like a higher number of source requirement, voltage balancing of the capacitor and large switch requirement in CHB topology, FC topology and NPC topology respectively [4], [5]. Still, their advantages in terms of power quality supersede the shortcomings. Researchers have been trying to solve and mitigate the issues with MLI and have published a large number of papers over the last few years. They have mainly focused on reducing the switch count, source count and voltage balancing control of MLI. The design of MLI mainly depends upon the number of levels required at the output, number of semiconductor devices used, number of dc voltage sources and capacitors utilized, modularity of topology and the total standing voltage (TSV) of topology, etc. Based on these aspects, a number of MLI topologies have been presented and analyzed in the literature [2]- [7].
Another aspect of MLI has been the selection of magnitude of dc voltage sources used in the topology. Based on this, MLIs have been classified as symmetrical and asymmetrical. Symmetrical MLIs uses identical dc voltage sources whereas asymmetrical MLIs employs dc voltage sources having unequal magnitude. Symmetrical MLIs have more redundant states i.e. more number of switching combination are available to get same voltage level. This improves the performance of MLI in terms of balancing the voltage across capacitors and fault tolerant capabilities. However, at the same time symmetrical configured MLIs requires more number of switches, gate driver circuits, and dc voltage links. This increases the inverter size, cost and control complexity for a higher number of levels. Asymmetrical configuration increases the number of levels generated at the output compares to the symmetrical configuration using the same number of components and dc voltage sources [6], [7].
Various variants of conventional MLI have been reported in the literature to overcome the shortcomings while others have mentioned the shortcoming of a conventional multilevel inverter [8]. A higher number of switches are required to generate a staircase multilevel waveform. Moreover, even low rating switches require separate driver circuit along with necessary protective circuitry which adds to the complexity of the system. Authors of [8] have compared the work with several topologies. The results presented show that the number of IGBT required to realize a similar voltage level is lesser [8]. Moreover, the standing voltages are also lesser on the bidirectional switch. The topology of [8] has also been experimentally verified with a suitable design example.
The topology proposed in [9] utilized two novel cascaded multilevel inverters which contain five-level sub-module architecture. The proposed topology has been realized in both the asymmetrical and symmetrical mode of operation. The result shows the structure has advantages in levels of voltage generated for a given number of switches. The topology proposed in [10] requires eight switches to produce 15 level output. But the same voltage level can be achieved by PUC converter proposed in [11] and later in [12] with the lesser standing voltage on the switching devices. The proposed application of topology presented in [10] includes D-STATCOM, hybrid electric vehicle, and PV system. Modular expendables symmetric and asymmetric structures with staircase cascading are reported in [13]. The topology has been compared with [14] and results presented claims to require lesser installation space and cost because of the reduced number of switching devices, switching and conduction losses and total standing voltage. The authors of [13] have also presented the simulation results which are validated by the experimental formulation of its prototype. The topologies of [15], [16] pointed out the disadvantage of H-bridge based multilevel converters topologies because of higher switching stress and total standing voltage. The ST topology is proposed in [16] contain two back to back connected T type switching arrangements (each T-section have two unidirectional and two bidirectional switches) joined together to create a new structure which produces 17 levels without the H-Bridge circuitry for voltage polarity reversal. It utilizes 12 switches. The modules can be cascaded to produce a higher number of voltage level. An improved H-bridge based high step-up multilevel converter has been presented in [17]. The basic unit consists of two unidirectional switches, a capacitor, a power diode, and a dc voltage source. Control of switching devices ensures that the capacitor is charged to twice the voltage of dc source thereby developing output voltage higher than the input voltage. Two basic units along with the improved H-bridge unit constitutes the high step-up MLI. The topology proposed in [18] suggested another basic unit structure composed of four unidirectional switches, two bidirectional switches, and two dc sources. A modified H-Bridge is sandwiched between two such basic units forming a module with two dc sources on left of modified H-bridge and the remaining two are on the right side. The cascaded structure has also been presented. Various graphical representation of performance analysis points towards attractive features of the proposed multiple level converter. Similarly, some other upgraded topologies have been proposed in [19]- [29].
In this paper, work has been carried out with the aim of reducing the number of power semiconductor devices and dc voltage sources, while achieving a higher number of levels at the same time. This paper is organized as follows: Section II describes the proposed topology with its extension for a higher number of level. To set the benchmark of the proposed topology, Section III gives a quantitative comparison of the proposed topologies employing the same number of switches. Section IV elaborates the various experimental results and Section V summarizes the paper.

II. PROPOSED MULTILEVEL INVERTER A. PROPOSED THREE SOURCE 15 LEVEL (3S-15L) TOPOLOGY
The proposed topology is depicted in Fig. 1. It consists of eight unidirectional switches from S 1 -S 8 along with one bidirectional switch S 9 . The switches S 3 -S 6 along with S 9 forms the inner part of the topology with two dc voltage VOLUME 7, 2019 sources with a magnitude of V 2 . The remaining four switches i.e., S 1 -S 2 and S 7 -S 8 and one dc voltage source with magnitude of V 1 forms the outer portion of the proposed topology. The switches (S 1 -S 2 ), (S 3 -S 4 ), (S 5 -S 6 ), and (S 7 -S 8 ) need to operate in a complementary fashion to avoid shortcircuiting of dc voltage sources.
The number of levels depends upon the magnitude of the dc voltage source, i.e., V 1 and V 2 the selection can be done in two ways as:

1) SYMMETRICAL CONFIGURATION
In this configuration, each dc voltage source has the same magnitude, i.e., V 1 = V 2 = V dc . With such configuration, seven levels at the output are achieved.

2) ASYMMETRICAL CONFIGURATION
In the asymmetrical configuration, the magnitude of dc voltage sources have different magnitude, i.e., V 1 and V 2 have a different magnitude. For the proposed topology with asymmetrical configuration, the magnitude of dc voltage sources are chosen in tertiary mode, i.e., V 1 = V dc , and V 2 = 3V dc (3S-15L Topology). With the tertiary configuration, the proposed topology generates 15 output voltage levels, i.e., zero, ±V dc , ±2V dc , ±3V dc , ±4V dc , ±5V dc , ±6V dc , and ±7V dc . The switching table for the proposed topology with the tertiary mode is given in Table 1. Furthermore, the different switching states for the proposed topology with tertiary mode are shown in Figs. 2 (a)-(h). With tertiary mode, the maximum output voltage (Vo,max) of the proposed topology is: The total standing voltage (TSV) is an important factor for the selection of switches. TSV is the addition of the maximum blocking voltage across each semiconductor device. The voltage stress across each pair of the complementary switch will be the same. Therefore, The voltage stress across each unidirectional switch of the bidirectional switch S 9 is given as: As two unidirectional switches are used for the bidirectional switch, each unidirectional switch needs to block the voltage of 3V dc . Therefore,  The proposed 3S-15L topology can be extended by replacing the single dc voltage source of magnitude V 1 with a T-configured two dc voltage sources with same magnitude V 1 as shown in Fig. 3. With the addition of one dc voltage source with magnitude V 1 and a bidirectional switch S 10 , there is an addition in the number of levels. Again, for the symmetrical configuration, the proposed topology can generate nine levels. However, for asymmetrical configuration, the number of levels increases to 25. The 25 level output is achieved by selecting V 1 = V dc and V 2 = 5V dc . The different switching combination for the proposed topology with four dc voltage sources generating 25 levels is given in Table 2.

C. GENERALIZED STRUCTURE OF THE PROPOSED TOPOLOGY
In both proposed topologies with asymmetrical configuration, the magnitude of V 2 is higher compared to V 1 . The proposed topology can be extended in two different ways as explained below.

1) EXTENSION WITH HIGHER NUMBER OF DC VOLTAGE SOURCES WITH MAGNITUDE V 1
In this method, the number of dc voltage sources with magnitude V 1 are increased in the outer T-section as shown in Fig. 4. For achieving higher number of levels, the selection of dc voltage sources is according to asymmetrical configuration. For the maximum number of levels, with k number of dc voltage sources of V 1 = V dc , the magnitude magnitude of V 2 is selected as: The peak output voltage is given as The expression for number of switch requirement, gate driver, number of dc supply as a function of output voltage level is given by (7).
The TSV for the proposed extension can be divided into two parts as: where TSV T is the TSV for the T-section of the proposed extension which is given as: where, TSV V2 is the TSV of the topology with dc voltage sources of magnitude V 2 and is given by Eq. (4) which is: Therefore, from (8)- (10), 2) EXTENSION WITH HIGHER NUMBER OF DC VOLTAGE SOURCES WITH MAGNITUDE V 2 One main issue with the extension 1 (Ext-II) has been the magnitude of dc voltage source V 2 as its magnitude is dependent on k as given in Eq. (5). This problem can be solved by increasing the number of voltage source with magnitude V 2 . Fig. 5 shows the Ext. II of the proposed topology. For a higher number of levels with asymmetrical configuration, the magnitude of dc voltages are selected as V 1 = V dc , and V 2 = 5V dc . The different equations for the Ext. II remains the same as Ext. I as given in (7). The equation for TSV modifies as:

III. COMPARATIVE STUDY
In this section, a detailed comparative study is provided for the proposed topologies. The topology with three dc voltage source, four dc voltage source, and generalized structure have been compared separately with similar topologies. The proposed topologies with three and four dc voltage sources have been compared in terms of number of switches, number of gate driver circuit required, number of levels generated, number of diodes, TSV, and maximum blocking voltage (MBV) of any individual switch. The generalized structure has been compared in terms of number of switches, number of gate driver circuit, number of dc voltage sources and TSV against the number of levels at the output.

A. COMPARISON OF PROPOSED 3S-15L TOPOLOGY
The quantitative comparison among the topologies is given in Table 3. From the table, it is shown that the proposed MLI generates higher voltage levels compared to [13], [19], and [24] and have the same capability of voltage level generation as of [28]. However, proposed topology uses lesser gate driver circuits and have lower TSV and MBV than [28] which lower the cost of the MLI.

B. COMPARISON OF PROPOSED 4S-25L TOPOLOGY
In this comparison, similar topologies have been considered which have four dc voltage sources and configure in a symmetrical configuration. Table 4 gives a quantitative comparison of the proposed topology with other topologies. From the table, it can be deduced that the topologies presented in [15], [16], [27], and [25] generates fewer voltage levels compared to the proposed topology. In addition, the proposed topology utilizes a lesser number of gate driver circuits without any diodes compared to [28] which decreases the system cost and improves the conversion efficiency. Fig. 6 (a) shows the variation of number of power semiconductor switches required againstt the number of levels at the output. From Fig. 6 (a) it is shown that the proposed MLI generates higher voltage levels compared to all other topologies with number of levels more than 15. Furthermore, the proposed inverter utilized less number of driver circuits than all other topologies when voltage level are greater than 40 as shown in Fig. 6 (b). Moreover, with number of levels more than 22, only [29] requires less number of driver circuit compare to proposed topology. In addition, the variation of the number of dc voltage sources against the number of levels is illustrated in Fig. 6 (c). The proposed inverter utilized a lesser number of voltage sources than all other topologies when number of levels are higher than 28. The lower number of switches, driver circuit and dc voltage sources shows the superiority of the proposed topology with other topologies used for the comparison.

IV. RESULTS AND DISCUSSION
To verify the performance of the proposed topology, a laboratory prototype has been developed for the experimental results. In the experimental setup, TOSHIBA IGBT GT50J325 is used as a power switch.   examples of high switching frequency technique. The fundamental switching frequency techniques are more preferable than high switching frequency techniques due to its ability of achieving higher energy conversion with less system cost.  Among fundamental switching frequency techniques, the NLC is normally used due to its easy control and implementation when working on high level inverter.
In this paper, fundamental frequency modulation techniques based nearest level control (NLC) is used for the generation of gate pulse. With NLC, the sampled waveform is generated by comparing the reference signal with the existing voltage level as shown in Fig. 7 (a). Fig. 7 (b) shows the general control diagram for the NLC.
In this paper, the hardware results for the proposed topology with 3S-15L and 4S-25L configuration have been presented.
A. EXPERIMENTAL RESULTS FOR PROPOSED 4S-15L TOPOLOGY As shown in Fig. 8, the proposed topology with three dc voltage sources generates 15 levels at the output having in Fig. 8 (a). Moreover, the voltage stress across different  switches are also shown in Fig. 8 (b) and (c). All these voltage stresses are in consistence with equation (2) and (3).
Furthermore, the proposed topology is tested with different types of loading conditions. Fig. 9 (a) shows the dynamic response of the proposed topology with change in the magnitude of resistive load. Figs. 9 (b) -(d) gives the transient response i.e., showing the change of current as the load magnitude is changed. Furthermore, Fig. 9 (e) -(g) depicts the steady-state response with the resistive load. A similar test has been conducted with series connected the resistiveinductive load. Fig. 10 (a) -(f) shows the different transient and steady-state response for RL load.
A change of modulation index has also been considered while validating the performance of the proposed topology. Fig. 11 (a) illustrate the output voltage and current waveform with a change of modulation indexes from 1.0 to 0.5 with a 58592 VOLUME 7, 2019 resistive load of 100 . With the change of modulation index from 1.0 to 0.5, the number of levels is reduced to seven from fifteen. The smooth change of current and voltage waveform is shown in Fig. 11 (a). Similarly, with a resistive-inductive load, the change of modulation index has been depicted in Fig. 11 (b) with the waveform of voltage and current.

B. HARDWARE RESULTS FOR PROPOSED 4S-25L TOPOLOGY
The proposed 25 level topology has also been tested under various test conditions. As shown in Fig. 3, the topology for 25 level output voltage requires four dc voltage sources. The magnitude of V 1 is set to 10V and the magnitude of V 2 is selected as 50V. This selection results in an output voltage with a peak magnitude of 120V. The 12 voltage levels have a step voltage magnitude of 10V. Fig. 12 (a) shows the 25 level output voltage and to get a clearer view of the output voltage levels, Fig. 12 (b) shows a zoomed view of the output voltage.
Similar to 15 level output voltage, the proposed 25 level output voltage has been tested with the dynamic load variation. Fig. 12 (c) -(e) display the change of resistive load with 25 level output voltage. The load magnitude has been changed from zero to 100 and this variation has been shown in Fig. 12 (d). Similarly, Fig. 12 (e) shows the change of resistance from 100 to 50 . From all these hardware results for 15 and 25 levels, the proposed topologies give satisfactory results under different dynamically changing load conditions.

V. CONCLUSION
This paper presents a new assembly of multilevel inverter topology with consideration of reduced switch count. The proposed topology has been discussed in details with the basic unit with 3S-15L configuration generating 15 levels, and the extension of the proposed topology with 4S-25L configuration to achieves 25 levels. Two generalized structure of the proposed topology has also been proposed. A detailed comparative study has been carried out with the proposed topology and recently reported topologies with three and four dc voltage sources. Finally, several experimental results proves the suitability and workability of the proposed topology with different type of loading combinations considering the change of modulation indexes.