Building programmable integrated circuits through disordered Chern insulators

Bing-Lan Wu, Zi-Bo Wang, Zhi-Qiang Zhang, and Hua Jiang

Phys. Rev. B 104, 195416 – Published 15 November 2021

Abstract

We study the construction of programable integrated circuits with the help of disordered Chern insulators. Specifically, the schemes for low dissipation logic devices and connecting wires are proposed. We use the external-gate-induced step voltage to construct spatially adjustable channels, where these channels take the place of the conventional wires. Our numerical calculation manifests that the external gates can be adopted to program the arbitrary number of wires ( $n$ -to- $m$ connections). We find that their electron transport is dissipationless and robust against gate voltage fluctuation and disorder strength. Furthermore, seven basic logic gates distinct from the conventional structures are proposed. Our proposal has potential applications in low power-integrated circuits and enlightens the building of integrated circuits in topological materials.

Received 5 September 2021
Accepted 5 November 2021

DOI:https://doi.org/10.1103/PhysRevB.104.195416

Physics Subject Headings (PhySH)

Chern insulators Topological Hall effect Topological insulators

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

Bing-Lan Wu¹, Zi-Bo Wang², Zhi-Qiang Zhang^1,*, and Hua Jiang ^1,3,†

¹School of Physical Science and Technology, Soochow University, Suzhou, 215006, China
²College of Physics and Electronic Engineering, Sichuan Normal University, Sichuan, 610066, China
³Institute for Advanced Study, Soochow University, Suzhou 215006, China

^*zhangzhiqiangphy@163.com
^†jianghuaphy@suda.edu.cn

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Vol. 104, Iss. 19 — 15 November 2021

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Images

Figure 1
(a) Schematic plot of a conventional printed circuit board. The orange areas are the background. The solid green lines are the wires and the logic devices are marked in yellow circles. (b) Schematic plot of a programmable integrated circuit based on disordered CIs. The central region is divided into several cyan and gray blocks. The red arrows denote the current directions.
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Figure 2
(a) Schematic of programable circuit device. The central region is divided into $6 \times 6$ blocks with size $100 a \times 100 a$ , where $a$ is lattice constant. (b), (d), (g) Local current density distribution corresponding to (a) with disorder strength $W = 3.5 t$ under different gate voltage configuration. Here, the gate voltage on white and blue blocks are $V_{a}$ and $V_{b}$ , which take the standard values $V_{a} = - 2.8 t$ , $V_{b} = 0$ if not specified. The red arrows denote the chiral interface channels. (c) Differential conductances $G$ of case (b) versus $W$ under different $V_{a}$ . [(e),(f)] and [(h),(i)] are similar to those in (c), except $G$ for cases (d) and (g), respectively.
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Figure 3
[(a),(e)] Schematic of programable circuit devices, which have two and three chiral interface channels, respectively. [(b),(f)] Local current density distribution corresponding to cases [(a),(e)] with gate voltage $V_{a} = - 2.8 t$ , $V_{b} = 0$ and disorder strength $W = 3.5 t$ . [(c),(d)] and [(g),(h)] Conductances $G$ $v s W$ for different $V_{a}$ and $V_{b}$ , respectively.
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Figure 4
[(a),(d)] The schematic diagram of gate voltage configuration to realize two and three branches of current in integrated circuits devices, respectively. The blue circles denote bifurcation points of current. [(b),(e)] Local current density distribution corresponding to [(a),(d)], respectively, with $V_{a} = 0$ , $V_{b} = - 2.8 t$ and disorder strength $W = 3.5 t$ . [(c),(f)] The branch conductance $G_{R 1, L 2}$ , $G_{R 2, L 2}$ , $G_{R 3, L 2}$ , and the total conductance $G vs V_{b}$ with $V_{a} = 0$ and $W = 3.5 t$ .
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Figure 5
(a)–(g) The schematic diagram of seven basic logic gates and the corresponding truth tables. The central region is divided into one, two, or three blocks labeled by $S 1$ , $S 2$ , or $S 3$ , respectively. $A$ and $B$ denote voltage input terminals, connected to the gate on the corresponding block $S 1$ , $S 2$ , or $S 3$ . $Y$ denotes voltage output terminal. $V_{d d}$ and $V_{s s}$ represent supply and source voltage. $L 1$ and $L 2$ or $L 3$ represent the left and right terminals connected to the central region. When the voltage signal $V_{A} = V_{B} = 0$ , the initial Fermi energy in the blue block is $E_{f} = 0$ (i.e., the CI with Chern number $C = 1$ ), and in the white block is $E_{f} = - 2.8 t$ (i.e., the Anderson insulator with $C = 0$ ).
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Figure 6
Differential conductances $G$ versus disorder strength $W$ for OR gate.
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