Dual-Gate Velocity-Modulated Transistor Based on Black Phosphorus

V. Tayari, N. Hemsworth, O. Cyr-Choinière, W. Dickerson, G. Gervais, and T. Szkopek

Phys. Rev. Applied 5, 064004 – Published 9 June 2016

Abstract

The layered semiconductor black phosphorus has attracted attention as a 2D atomic crystal that can be prepared in ultrathin layers for operation as field-effect transistors. Despite the susceptibility of black phosphorus to photo-oxidation, improvements to the electronic quality of black phosphorus devices has culminated in the observation of the quantum Hall effect. In this paper, we demonstrate the room-temperature operation of a dual-gated black phosphorus transistor operating as a velocity-modulated transistor, whereby modification of hole density distribution within a black phosphorus quantum well leads to a twofold modulation of hole mobility. Simultaneous modulation of Schottky-barrier resistance leads to a fourfold modulation of transconductance at a fixed hole density. Our work explicitly demonstrates the critical role of charge-density distribution upon charge carrier transport within 2D atomic crystals.

Received 14 December 2015

DOI:https://doi.org/10.1103/PhysRevApplied.5.064004

Physics Subject Headings (PhySH)

Elemental semiconductors Field-effect transistors

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

V. Tayari¹, N. Hemsworth¹, O. Cyr-Choinière², W. Dickerson¹, G. Gervais², and T. Szkopek¹

¹Department of Electrical and Computer Engineering, McGill University, Montreal, Québec H3A 0E9, Canada
²Department of Physics, McGill University, Montreal, Québec H3A 2T8, Canada

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Vol. 5, Iss. 6 — June 2016

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Images

Figure 1
(a) Optical image of a bP FET in a multiple-terminal geometry prior to top-gate deposition. Scale bar is $20 μ m$ . (b) Optical image of the device shown in (b) including top-gate and methylmethacrylate (MMA) and poly(methylmethacrylate) (PMMA) encapsulation. Scale bar is $20 μ m$ . (c) Atomic-force-microscope (AFM) line scan of a region of bare $bP / {Al}_{2} O_{3}$ of the device in (b), with the MMA and PMMA layers removed. (d) Schematic view of a dual-gate bP FET with ${SiO}_{2}$ back-gate, ${Al}_{2} O_{3}$ top-gate dielectric, source ( $S$ ) and drain ( $D$ ) contacts, and encapsulating layers of MMA and PMMA. (e) Schematic view of the bP FET channel with top- and bottom-hole accumulation layers (red) providing two parallel conduction paths between source and drain.
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Figure 2
(a) Source-drain current $I$ as a function of the source-drain voltage $V_{SD}$ with bottom-gate and top-gate biases of $V_{TG} = 0 V$ and $V_{TG} = 0 V$ indicative of Ohmic contacts. (b) Two-terminal conductance $G_{2 p}$ as a function of top-gate voltage $V_{TG}$ at fixed bottom-gate voltages $V_{BG} = - 50$ , $- 30$ , 0, $+ 30 V$ . (c) Two-terminal conductance $G_{2 p}$ versus back-gate voltage $V_{BG}$ at three top-gate voltages $V_{TG} = - 4$ , 0, $+ 4 V$ at room temperature. Minimal hysteresis is observed at the $1 V / s$ sweep rate used for the back-gate potential. (d) Two-dimensional contour plot of two-terminal conductance $G_{2 p}$ versus gate voltages $V_{TG}$ and $V_{BG}$ at $T = 77 K$ , for the same device. A bias point corresponding to minimal conduction and complete channel depletion located at $V_{TG} = 0 V$ and $V_{BG} = - 30 V$ is indicated by a star symbol. Cuts of constant top-gate voltage and constant bottom-gate voltage used to determine field-effect mobility are shown. (e) The absolute value of bottom-gate field-effect mobility $μ_{BG}$ versus $V_{BG}$ at $V_{TG} = 0 V$ . (f) The absolute value of top-gate field-effect mobility $μ_{TG}$ versus $V_{TG}$ at $V_{TG} = - 30 V$ .
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Figure 3
The band diagrams and volumetric charge-density distribution in a 32-nm-wide bP quantum well determined by Schrödinger-Poisson calculations at $T = 300 K$ for different gate-bias potentials. (a) Asymmetric gate bias inducing a $p − n$ carrier distribution with $p_{BG} = n_{TG} = 10^{12} {cm}^{- 2}$ and an associated inversion in carrier type. (b) Gate bias inducing $p_{BG} = 10^{12} {cm}^{- 2}$ at one bP surface and flat-band conditions at the other. (c) Symmetric gate bias inducing a $p − p$ carrier distribution with a total hole concentration of $p_{BG} + p_{TG} = 10^{12} {cm}^{- 2}$ corresponding to hole accumulation at both bP surfaces.
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Figure 4
(a) The measured two-terminal back-gate transconductance $g_{m}$ of the device shown in Figs. 1 and 2 as a function of hole density $p_{BG}$ induced by the back gate, at fixed top-gate voltages $V_{TG}$ at $T = 300 K$ . A fourfold enhancement of two-terminal $g_{m}$ is observed as $V_{TG}$ is tuned from 0 to $- 4 V$ . (b) The field-effect mobility $μ_{4 p}$ of the same device on a log-log scale versus $p_{BG}$ at fixed top-gate voltages at $T = 300 K$ . A twofold enhancement in mobility is achieved by tuning the top-gate potential. (c) The contact resistance $R_{C}$ of the same device versus $p_{BG}$ at fixed top-gate voltage. A twofold modulation in contact resistance is observed as the top-gate voltage is tuned.
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