An energy and information analysis method of logic gates based on stochastic thermodynamics

Abstract To reduce the energy consumption of logic gates in digital circuits, the size of transistors approaches the mesoscopic scale, e.g. sub-7 nanometers. However, existing energy consumption analysis methods exhibit various deviation for logic gates when the nonequilibrium information processing of mesoscopic scale transistors with ultra-low voltages is analyzed. Based on the stochastic thermodynamics theory, an information energy ratio method is proposed for the energy consumption estimation of XOR gates composed of mesoscopic scale transistors. The proposed method provides a new insight to quantify the transformation between the information capacity and energy consumption for XOR gates and extending to other logic gates. Utilizing the proposed analysis method, the supply voltage of the parity check circuit can be optimized by numerical simulations without expensive and complex practical measurements. The information energy ratio is the first analytical method to quantify the energy and information transformation of logic gates at the mesoscopic scale.

With the fast-growing deployment of the 5th-generation (5G) mobile communication, artificial intelligence (AI) and big data systems, the massive data need to be processed by digital signal processing circuits.The energy consumption of digital signal processing circuits is increased quickly in 5G mobile communication, AI, and big data systems (1,2).Digital signal processing circuits are composed of three types of basic logic gates, i.e.AND, NOT, and XOR gates, all of which are made up of transistors (3).Thanks to the recent advancement of circuit technologies, the size of transistors is coming into the mesoscopic scale, e.g.sub-7 nanometers (nm), and continuing increases have been provided in computing capability (4).However, when the sub-7 nm transistor technology is adopted, digital logic circuits are inevitably becoming more and more susceptible to the thermal noise due to the aggressive voltage and gate length scaling (5), especially at the mesoscopic scale.Traditional energy consumption analytical methods of digital logic circuits take into account the thermal noise from phenomenological approaches (6).Hence, traditional energy consumption analytical methods are difficult to reveal the energy and information transformation mechanism of digital circuits due to the thermal fluctuations of nonequilibrium information processing at the mesoscopic scale (7).To overcome the faultiness of traditional energy consumption analytical methods, the stochastic thermodynamics is introduced to analyze the nonequilibrium information processing of transistors at the mesoscopic scale (8).Recently, the information thermodynamic theory-based energy consumption models were explored for logic gates (9).However, it is a great challenge to design an analysis method to clarify the transformation ratio between the information and energy with a specific process at logic gates, which can be used to optimize the energy consumption of logic gates, such as XOR operations at XOR gates adopted the complementary metal-oxide-semiconductor (CMOS) technology.Considering the complexity of nonequilibrium information processing process of transistors at the mesoscopic scale, it is a great challenge to propose an analytical method of information and energy transformation for logic gates and digital circuits.
To describe the nonequilibrium information process in digital circuits, the information thermodynamic theory has been utilized to explore the thermal, work, and entropy of digital signal processing (7,(10)(11)(12)(13).Freitas et al. (7) established a stochastic thermodynamic model to investigate the irreversible entropy production of nonlinear electronic circuits subject to thermal noise.The mismatch entropy production was proposed to differentiate the entropy of the actual input distribution and the entropy of the optimal input distribution in a thermodynamic system (10).Recently, the energy dissipation of digital circuits has been investigated by the mismatch entropy production and Landauer's principle (11).In particular, Koski et al. (12) characterized the thermodynamic entropy production model of singleelectron transistors and derived a generalized fluctuation theorem.Wimsatt et al. (13) analyzed the physical factors that influence the energy consumption of computation systems, including the computing rate, computing error rate, storage stability, circuit modularity, etc. Sadasivan Shankar et al. ( 14) evaluated the efficiency of an ideal computing architecture using thermodynamics and quantum mechanics principles, which is applicable to both large computing systems and single switches.
Most existing studies on digital circuits focus on relatively simple scenarios extended from Landauer's principle.The interaction between information capacity and energy consumption of logic gates is one of the most basic studies for the design of digital logic circuits.However, the study investigating the interaction between information capacity and energy consumption in logic gates, particularly considering the influence of thermal noise at the mesoscopic scale, is rare in the open literature.Motivated by the above gaps, in this article, we first propose an analysis method to quantify the transformation ratio between the information capacity and energy consumption for logic gates at the mesoscopic scale.The proposed analysis method can be extended to other logic gates and circuits by changing the combination of transistors and adjusting the linear relationship between energy levels and voltages.The key contributions of this article are briefly summarized as follows: 1. Based on the stochastic thermodynamics and information theory, an analysis method, i.e. the information energy ratio, is first modeled to reveal the interplay between the information capacity and energy consumption of XOR gates composed of mesoscopic scale transistors.Moreover, the proposed analysis method can be extend to other logic gates by changing the combination of transistors and adjusting the linear relationship between energy levels and voltages.The proposed analysis method provides a new insight to quantify the transformation ratio between the information capacity and energy consumption for logic gates.Furthermore, an upper bound of the information energy ratio of XOR gates is derived.2. Based on the proposed analysis method, the information energy ratio is used to analyze the transformation ratio between the information capacity and energy consumption for the parity check circuit.3. Utilizing the proposed analysis method to simulate the information energy ratio of the parity check circuit adopting the 7 nm semiconductor process supply voltage, simulation results show that the information energy ratio of the parity check circuit is improved by 266% when the supply voltage is set to a chosen value.These results indicate that the proposed analysis method can be used to optimize the energy consumption of digital signal processing circuits by numerical simulations without expensive and complex practical measurements.

Energy consumption of XOR gates
In this article, an XOR gate is composed of four single-electron NAND gates, as shown in Fig. 1a.The dynamic electron transfer process of each NAND gate is illustrated in Fig. 1b.Fig. 1c shows the schematic diagram of XOR gates.XOR gates can be used to compose a variety of commonly used circuits, such as the parity check circuit, which is shown in Fig. 1d.As shown in Fig. 1d, the parity check circuit is composed of two XOR gates connected in series.Three inputs of the parity check circuit are represented as A, B, and C and the output is represented as Y parity , A, B, C ∈ {0, 1}, Y parity ∈ Y XOR , which is the all output space of XOR gates.In this way, the physical operation process of XOR gates can be abstracted as the electron transfer process.The derivation of the energy consumption of NAND gates is given in Supplementary Material, Appendix S1.The energy consumption of XOR gates is composed of the energy consumption of four NAND gates, which is expressed as where W r NAND (τ) is the energy consumption of NAND r when the propagation delay is τ, r ∈ {1, 2, 3, 4}.The propagation delay is taken as the moment when the difference between the output voltage and the expected voltage exceeds a certain threshold.
Assuming that input sequences are governed by the uniform distribution, Fig. 2a-d  Considering that different previous inputs result in different voltages of capacitors in XOR gates, the energy consumption of XOR gates depends not only on the present input but also on the previous input.A string of double-inputs sequence streams with the length M is represented as which are located at two inputs of XOR gates described as A and B, respectively.Without loss of generality, the set space of a n b n is denoted as a n b n ∈ {00, 01, 10, 11}.When four states of input at the previous time step are configured as {00, 01, 10, 11}, the energy consumption of XOR gates can be calculated as follows where E an−1bn−1→anbn is the consumed energy when the previous input symbol is a n−1 b n−1 at the time step n − 1 and the current input symbol is a n b n at the time step n.The input state transition matrix is where P an−1bn−1→anbn is the transition probability when the previous input symbol is a n−1 b n−1 at the time step n − 1 and the current input symbol is a n b n at the time step n.Based on Eqs. 2 and 3, the average energy consumption of one operation at the XOR gate is given by The traditional energy consumption analysis method of XOR gates due to switching activities is expressed as where ζ is the switching coefficient, C is the load capacitance, V DD is the supply voltage, and f is the operating frequency (15,16).When the technology of transistors is adopted to be 7 nm, the physical gate length is 54 nm.The equivalent load capacitance per unit gate length is C = 3 × 10 −18 farad/nm (17), thus C g = 1.62 × 10 −16 farad.The rest of simulation parameters are configured as ζ = 0.2 and V d = 0.4 Volt, V T = kT/q ≈ 0.026 Volt is the thermal noise voltage, i.e. the unit voltage of the supply voltage.q is the charge of the electron.Fig. 2e shows the energy consumption of XOR gates for one operation with respect to the traditional method, the ST method, and the hierarchical simulation program for integrated circuits emphasis (HSPICE) method (18).As shown in Fig. 2e, the deviation among three methods is within 10% at 7 nm CMOS technology.When the result of HSPICE method is configured as the benchmark, the deviation of the ST method is less than the deviation of the traditional method in the energy consumption estimation of XOR gates.When the gate size of transistors is 0.34 nm and the other parameters are configured as 02 × 10 −18 farad, and ζ = 0.2, Fig. 2f shows the energy consumption of XOR gates for one operation with respect to the traditional method, the ST method, and the experimental data from the graphene side-wall edge gated MoS2 transistor (19), where the XOR gate based on the graphene side-wall edge gated MoS2 transistor consists of 16 transistors.Simulation results in Fig. 2f show that the deviation between the traditional method and the graphene sidewall edge gated MoS2 transistor is 73.47%.Therefore, the traditional method cannot used for analyzing the energy consumption of XOR gates at the sub-7 nm scale.Simulation results in Fig. 2f validate that the deviation between the ST method and the graphene sidewall edge gated MoS2 transistor is 5.92%.Hence, the ST method can still be used for analyzing the energy consumption of XOR gates at the sub-7 nm scale.Moreover, the energy consumption and propagation delay of XOR gates for one operation with different environment temperatures are illustrated in Fig. 2g.When the environment temperature is increased, Fig. 2g shows that the energy consumption is increased and the propagation delay is decreased.The electron transfer rate of the XOR gate increases with the increase of environment temperature.As a consequence, the increased electron transfer rate causes an increase in the drain current of the XOR gate.In the end, the energy consumption of XOR gates is increased.Moreover, the time reaching the steady state is reduced in the electron transfer process of XOR gates when the electron transfer rate is increased.Therefore, the propagation delay of XOR gates is decreased in Fig. 2g.

Information capacity of XOR gates
Figure 3a illustrates the information processing process, wherein the information processing module can be an algorithm, an integrated circuit, or a simple logic gate.In Fig. 3a, the input symbol is x in which belongs to X = {x 1 , x 2 , . . .x in , . . ., x K } and the output symbol is y out which belongs to Y = {y 1 , y 2 , . . .y out , . . ., y K }.When the information processing module is replaced by a XOR gate in Fig. 1c, the input symbols of information processing process are replaced by the inputs of XOR gate, i.e.A and B and the output symbol of information processing process are replaced by the output of XOR gate, i.e.Y XOR .Based on the threshold voltage judgment criterion, the input logic states and the output logic states are mapped as where V in is the voltage of input and V out is the voltage of output, α is the threshold factor.When the output voltage is higher than or equal to αV d , the output symbol is marked as the logic 1.When the output voltage is lower than (1 − α)V d , the output symbol is marked as the logic 0. Otherwise, the output symbol is marked as ∅.The derivation of the mutual information of XOR gates is given in Supplementary Material, Appendix S2. Figure 3b and c simulates the mutual information of XOR gate with respect to the input distribution.Fig. 3b presents the mutual information of XOR gate in a three-dimensional perspective.The coordinates p a and p b represent the probabilities of logic 0 at the input A and B of XOR gate, respectively.The four blue corners below Fig. 3b indicate that two inputs of XOR gate remain unchanged when p a and p b approach either 0 or 1.These results imply that the mutual information of XOR gate approaches 0. The mutual information of XOR gate increases as p a and p b approach 0.5.Fig. 3c shows the heatmap of the mutual information of XOR gate projected onto the p a -p b plane.The red of thermodynamic grid is increased as p a and p b approach the central point, i.e. 0.5.The mutual information of XOR gate increases with the increase of red of thermodynamic grid.
By iterating through all possible input and output of XOR gate, the information capacity of XOR gate is given by where I(AB; Y XOR ) is the mutual information between the input and output of XOR gate for one operation.Supplementary Material, Appendix S3 includes the derivation of the information capacity of XOR gate.Equation 7indicates that the maximum information rate can be achieved by transmitting information with an arbitrarily small error rate.

Information energy ratio of XOR gates
To reveal the relationship between the information capacity and energy consumption of XOR gates at the mesoscopic scale, a new analysis method, i.e. an information energy ratio of XOR gates, is established by η XOR refers to the number of bits processed per unit of kT energy at an XOR gate.A larger information energy ratio indicates that more information can be processed per kT energy.See Supplementary Material, Appendix S4 for details of the information energy ratio of XOR gates.The transformation ratio between the mutual information and energy consumption of XOR gates is first quantified by 8, which can be used to analyze the impact of system parameters, e.g. the supply voltage on the information energy ratio of XOR gates.
Without loss of generality, two pictures are selected to analyze the information energy ratio of XOR gates.Fig. 4 illustrates the information energy ratio with respect to the supply voltage for an XOR gate.Fig. 4a compares the information energy ratio of XOR gates operated with different supply voltages, i.e. 4V T , 5V T , and 15V T .Fig. 4b and c is pictures for comparison.Three-dimensional, Red Green Blue (RGB) pixel points of the picture are converted into three binary bit streams, i.e.RGB binary bit streams, which are sequentially input into the parity check circuit, as shown in Fig. 4d.Compared with the information energy ratio with the supply voltage 4V T , the information energy ratio with the supply voltage 5V T is improved by 31.5% and 31% for the pictures of Fig. 4b and 4c, respectively.Compared with the information ratio with the supply voltage 15V T , the information energy ratio with the supply voltage 5V T is improved by 265.7% and 262.4% for the pictures of Fig. 4b and Fig. 4c, respectively.
The optimization problem to maximize the information energy ratio of XOR gates is expressed as where f (•) is the function based on 8. Based on the results of Fig. 4d, the range of supply voltage V d is configured as 4V T ≤ V d ≤ 6V T for maximizing the information energy ratio of XOR gates.Since 8 is a discontinuous function, the Genetic Algorithm (20) (GA) is adopted to obtain the upper bound of the information energy ratio of XOR gates.In GA, the binary coding is used to encode individuals and then each individual can be regarded as a solution to the above problem (21).In this case, each individual owns a set of chromosomes represented by three variables V d , p a , and p b .The simulation parameters are configured as follows: the length of gene code is 10, the size of population is 80, the evolution times are 100, and the mutation probability is 0.001.The maximum information energy ratio is configured as the fitness function of GA.The upper bound of the information energy ratio can be achieved for XOR gates during continuous iterations.Based on simulation results, we can observe that the upper bound of information energy ratio of XOR gates converges to 0.00026 bits/kT when V d ≈ 5.16V T , p a ≈ 0.39 and p b ≈ 1, i.e. the kT energy can maximally process 0.00026 bits of information for an XOR gate.

Information energy ratio of parity check circuit
The information energy ratio of parity check circuit is proposed as where I(ABC; Y parity ) is the mutual information between the input and output of the parity check circuit, E diss parity is the average energy consumption for one operation of the parity check circuit, which is composed of the energy consumption of two XOR gates.See Supplementary Material, Appendix S5 for details of the information energy ratio of the parity check circuit.
The supply voltage of XOR gate is the key factor to determine the error probability of XOR gate.Moreover, the information energy ratio of the parity check circuit depends on the optimization of the supply voltage.Without loss of generality, when the previous input is a n−1 b n−1 = 00, the error probability of XOR gates with respect to the supply voltage is simulated in Fig. 4e.Simulation results of Fig. 4e show that the error probability of XOR gates is larger than 1% when the supply voltage is less than 4V T .When the supply voltage is larger than or equal to 4V T , the error probability of XOR gates is less than or equal to 1%.Therefore, the XOR gate can function well only if the supply voltage is larger than or equal to 4V T considering that the error probability is required to be less than 1% in many logic operation circuit applications (22).
Based on the results of Fig. 4e, the supply voltage of XOR gates should be larger than or equal to 4V T .When the technology of transistors is 7 nm, the supply voltage of XOR gates is 0.39 Volt (23), i.e. 15V T .Without loss of generality, the range of supply voltage is configured from 4V T to 15V T for the parity check circuit in this article.Compared with the information energy ratio of the parity check circuit with 7 nm semiconductor process supply voltage, i.e. 15V T , results of Fig. 4f show that the information energy ratio of the parity check circuit with the supply voltage 5V T is improved by 266%.
shows the energy consumption of XOR gate as a function of time (unit is βh − , β = 1/kT, where k is the Boltzmann coefficient, T is the temperature, h − is the reduced Planck constant.kT is the unit energy, kT ≈ 4.14 × 10 −21 J when T = 300K).when the time step is n − 1, the input symbols a n−1 b n−1 are configured as {00, 01, 10, 11}, respectively.a n b n are the input symbols at the time step n.In Fig.2a, the curves when the input symbols at the time step n are 01 and 10 show a similar increasing trend, the curve corresponding to a n b n = 11 shows the largest energy consumption, and the curve corresponding to a n b n = 00 exhibits the lowest energy consumption.In Fig.2b, the curves corresponding to a n b n ∈ {01, 10} show a similar increasing trend, the curve corresponding to a n b n = 00 shows the largest energy consumption, and the curve corresponding to a n b n = 01 exhibits the lowest energy consumption.In Fig.2c, the curves corresponding to a n b n ∈ {00, 01} show a similar increasing trend, the curve corresponding to a n b n = 00 shows the largest energy consumption, and the curve corresponding to a n b n = 10 exhibits the lowest energy consumption.In Fig.2d, the curves when the input symbols at the time step n are 01 and 10 show a similar increasing trend, the curve corresponding to a n b n = 11 shows the largest energy consumption when the propagation delay is larger than 1.0 βh − , and the curve corresponding to a n b n = 00 exhibits the lowest energy consumption.

Fig. 1 .
Fig. 1.Models of XOR gates and the parity check circuit.a) Circuit diagram of XOR gates.The two inputs of the XOR gate are labeled as A and B, and the output is Y XOR .b) Kinetic diagram of the gate NAND r , where r ∈ {1, 2, 3, 4}.Each NAND gate is composed of P-type transistors and N-type transistors.Transistors and electrodes are expressed as different energy levels ε j and chemical potentials μ i , respectively, with j ∈ {P 1 , P 2 , N 1 , N 2 }, i ∈ {d, s, g}.V A and V B are the voltages of double-inputs of the NAND gate.The output voltage of NAND r is denoted as V out and the load capacitance is C g .The supply voltage is V d , and the voltage to ground is V s .c) Schematic diagram of XOR gates.d) The parity check circuit can be composed of two XOR gates shown as XOR1 and XOR2.

Fig. 2 .
Fig. 2. Energy consumption of XOR gates.a) The energy consumption curve of XOR gates when the previous input symbol is a n−1 b n−1 = 00.b) The energy consumption curve when the previous input symbol is a n−1 b n−1 = 01.c) The energy consumption curve when the previous input symbol is a n−1 b n−1 = 10.d) The energy consumption curve when the previous input symbol is a n−1 b n−1 = 11.e) Energy consumption of XOR gates for one operation with respect to ζ CV 2 DD f , the ST method and the simulation results based on HSPICE.f) Energy consumption of XOR gates for one operation with respect to ζ CV 2 DD f , the ST method and the 0.34 nm graphene side-wall edge gated MoS2 transistor.g) The energy consumption and propagation delay of XOR gates for one operation with different environment temperatures.

Fig. 3 .
Fig. 3. Schematic diagram of the information processing process and the mutual information of XOR gate with respect to the input distribution.a) Schematic diagram of the information processing process.b) The three-dimensional perspective.c) the heatmap projection on the p a -p b plane.

Fig. 4 .
Fig. 4. Information energy ratio and error probability of XOR gates with respect to the supply voltage.a) The information energy ratio of XOR gates operating with supply voltages 4V T , 5V T , and 15V T when operating picture 1 and picture 2. b) Picture 1. c) Picture 2. d) The preprocessing of pictures.e) The error probability of XOR gates with respect to the supply voltage when the previous input is a n−1 b n−1 = 00.f) The information energy ratio of the parity check circuit with respect to the supply voltage.