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Design of Ogg Vorbis Decoder System for Embedded Platform Atsushi KOSAKA Hiroyuki OKUHATA Takao ONOYE Isao SHIRAKAWA Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.8 pp.2124-2130 Publication Date: 2005/08/01 Online ISSN: DOI: 10.1093/ietfec/e88-a.8.2124 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from the 19th Symposium on Signal Processing) Category: VLSI Design Technology and CAD Keyword: embedded system design, Ogg Vorbis decoder, MDCT, residue decoding process, Full Text: PDF(563.6KB)>>
Summary: This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process. | ||||||||||
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