A superconducting nanowire-based architecture for neuromorphic computing

In previous work [7], the application of two superconducting nanowires whose intrinsic nonlinear inductance L_nw was used to generate spiking behaviour is presented. We summarize the description here.

As illustrated in figure 1, the nanowire neuron consists of a main and control relaxation oscillator in a loop. A source I_bias biases both oscillators below their critical currents but in opposite directions. An input current pulse at I_in applied to the loop then results in the current in the main oscillator to exceed I_c, causing it to switch. Then, current is diverted counterclockwise in the loop which causes the control oscillator to switch while the main oscillator relaxes. The switching of the control oscillator diverts current clockwise and causes the main oscillator to switch again. Each time main oscillator switches, a voltage spike will be seen at node V_out. The main and control oscillator act analogously to the Na⁺ and K⁺ ion channels in the Hodgkin–Huxley neuron model [26].

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The synapse consists of an hTron and an integration loop formed by L_syn, R_syn,1, and R_syn,2. When a voltage spike appears at V_out, heat is dissipated across R₂ (orange arrows). R₂ acts as the gate of the hTron, and the heat from it lowers the critical current of the hTron channel, causing the hTron to switch. In the switched (normal, non-superconducting) state, the resistance of the channel is typically on the order of 10² Ω for NbN films. The typical resistance for R_syn,1 and R_syn,2 is on the order of 10 Ω. Thus, when the hTron channel switches, the majority of the current I_bias,h is diverted into the integration loop. A portion of the current through L_syn is then transmitted to the target neuron via R_out. This process is analogous to the integration behaviour of the Hodgkin–Huxley model [26].

The simulated operation of a simple neuron-synapse-neuron connection demonstrating excitatory and inhibitory behavior is shown in figure 2. The network illustrated consists of an input neuron (1) connected to two target neurons (2, 3). The spike output from neuron 1 is connected thermally to the synapses via the hTron and the synapses are connected electrically to neuron (2, 3). When I_in,1 makes neuron 1 fire, the spikes are integrated in the synapse as shown by I_syn in figure 2(b). This synaptic current leads to the excitation of neuron 2 for a brief period of time. Similarly, the same current I_syn but in the opposite direction leads to inhibition of the firing of neuron 3 for a brief period of time.

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In SNNs, information must be encoded in the timing of the spikes in the network. In figure 3, we demonstrate the time-domain response of the neuron circuit with respect to its current biasing conditions. We define the spike period as the time between the voltage spikes in a neuron. Figure 3(a) demonstrates a decrease in the spike period of the nanowire neuron as a function of increasing input current. This same behaviour is seen in overbiased relaxation oscillators, where biasing a nanowire above its critical current also results in frequency-tunable oscillations [27]. We map the effect of this current-controlled frequency-tunability in figure 3(b). From the color map a firing threshold for the nanowire neuron can be identified from the summation of the input and bias currents. Once this threshold is reached, either an increase in the bias current or an increase in the input current result in an increase in the firing rate. This behavior can be explained from the critical current dynamics of the nanowires in the neuron circuit.

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Similarly, the synapse circuit presented in figure 1 also demonstrates tunable characteristics. The integration loop of the synapse acts as a leaky integrator circuit. The time-domain response of this circuit can be set during its design, by choosing the ratio between the L_syn/R_syn time constant and the L_nw/R₂ time constant, where L_nw is the inductance of nw₂. The leakiness of the synapse is illustrated in figure 4(a) where the current in the synaptic inductor is plotted for different values of synaptic inductance. In addition, I_bias,h controls the amount of current injected into the integration loop, modifying the output of the synapse. Therefore, the strength of the synaptic connection can be updated externally by tuning I_bias,h . Figure 4(b) shows the output current of the synapse for different values of I_bias,h .

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3.1.1. Correspondence to leaky integrate-and-fire model

The leaky integrate-and-fire neural network is one of the most commonly studied network-level models in neuroscience. In a network of n neurons, each is associated with a time-varying potential value. In this model, a neuron's potential is governed by the following equation:

$$\begin{equation}\frac{\mathrm{d}{u}_{i}(t)}{\mathrm{d}t}=-\lambda \left({u}_{i}(t)-{u}_{0,i}\right)-\sum\limits _{j}\,\alpha {C}_{ij}{s}_{j}(t)+{I}_{i}(t)\end{equation} \tag{ 1 }$$

where u_i (t) represents the potential of the ith neuron at time t; u_0,i is the initial potential with no input; and I_i (t) is the external input to the neuron. The leaky integration dynamic is encapsulated in the leakiness parameter λ of the neuron, that is the rate at which the neuron potential decreases. The synaptic strength from a neuron i to a neuron j is represented by matrix coefficient C_ij and a transfer parameter α. The spiking events of neuron i occur according to the following spike rule s(t):

$$\begin{equation}\begin{aligned}\hfill & s(t)=1,\quad {u}_{i}(t) > \eta \hfill \\ \hfill & s(t)=0,\quad \text{otherwise}\;,\hfill \end{aligned}\end{equation} \tag{ 2 }$$

where η is the threshold potential. We relate the parameters of this model to our superconducting hardware as described below.

In our hardware, the current in the nanowire i_nw(t) of the neuron's main oscillator corresponds to the potential u_i(t) in the leaky integrate-and-fire model. In the nanowire-based implementation, the spike rule corresponds to the voltage in the nanowire, the spiking events of the nanowire neuron are described by the following spike rule:

$$\begin{equation}\begin{aligned}\hfill & {v}_{\mathrm{n}\mathrm{w}}(t)={i}_{\mathrm{n}\mathrm{w}}{R}_{\mathrm{h}\mathrm{s}},{i}_{\mathrm{n}\mathrm{w}}(t) > {I}_{\mathrm{c}}\hfill \\ \hfill & {v}_{\mathrm{n}\mathrm{w}}(t)=0,\quad \text{otherwise.}\hfill \end{aligned}\end{equation} \tag{ 3 }$$

This relatively natural correspondence is what makes the superconducting system particularly elegant for the implementation of SNNs.

Similarly, the initial potential u₀ directly corresponds to the initial value of i_nw. For instance, when the inductance and resistance values between the two branches of the neurons are the same, the bias current in the nanowire of the main oscillator will be I_bias/2.

Moreover, the integration behaviour of the model corresponds to the ability of the hTron synapses to integrate the voltage spikes generated by the upstream neurons. The switching of the hTron channel and its subsequent diversion of current into the integration loop of the synapse, can be approximated by a leaky integration circuit with dynamics described by:

$$\begin{equation}\frac{\mathrm{d}{i}_{\mathrm{i}\mathrm{n}\mathrm{t}}}{\mathrm{d}t}=\frac{1}{\tau }\left({v}_{\mathrm{i}\mathrm{n}}-{i}_{\mathrm{i}\mathrm{n}\mathrm{t}}\right).\end{equation} \tag{ 4 }$$

Continuing with the analogy, the leakiness parameter λ corresponds to the ratio of the time constant of the relaxation of the nanowire in the neuron to the time constant of the integration loop in the synapse ${\tau }_{\mathrm{n}\mathrm{w}}/{\tau }_{\mathrm{s}\mathrm{y}\mathrm{n}}=\left({L}_{\mathrm{n}\mathrm{w}}/{R}_{2}\right)/\left({L}_{\mathrm{s}\mathrm{y}\mathrm{n}}/{R}_{{\mathrm{s}\mathrm{y}\mathrm{n}}_{1}}\right)$. τ_syn can be set such that it is larger than τ_nw to allow the synapse to retain the spike information from the neurons.

The transfer parameter α in the model corresponds to the ratio between I_bias,h and the current entering the nanowire of the main oscillator. The value of α is dependent on the number of synapses connected to a neuron, the synaptic inductance, and the inductances L₁ and L₂ of the nanowire neuron. For a neuron with a large number of synapses connected to its input terminal, less current from each synapse enters the neuron.

The matrix coefficients C_ij correspond to I_bias,h between the ith and jth neurons as it represents the strength of the connection between two neurons via a synapse. In the hardware, C_ij can be externally tuned as discussed in the previous section and illustrated in figure 4. Coupled together, C_ij can be mapped to the current added to the nanowire of the main oscillator.

The I_i (t) terms in the model correspond to the external input current source I_in to the ith neuron as shown in figure 1.

3.1.2. Correspondence to a basic compositional model

From the above descriptions of the leaky-integrate-and-fire model and the basic compositional model for SNNs, we built a tool to directly relate the parameters of the models to the physical implementation of the nanowire neuron and synapse. This tool can help bridge the expertise gap between computer scientists and hardware engineers in designing neuronal circuits as it provides a platform for a common description of a problem.

3.2.1. Implementation of the translational tool

In the tool, the network consisting of the neurons and synapses is described as a graph. A vector V describing the bias conditions to the neurons (the vertices) and a matrix E describing the strength of the synapses between them (the edges) is specified. Then, the algorithmic description from the leaky integrate-and-fire model, or the compositional model is chosen. Depending on the choice of model, V is treated as I_i (t) or b(u) and E is treated as C_ij or w(u, v). Correspondingly, the parameters of the algorithmic model are tuned either at each individual node or across the whole graph. The tool translates the parameters of each algorithmic model to the low-level hardware description based on the correspondence between the parameters described in each the previous section.

The tool uses SciPy's numerical solver IVP [30] to simulate the underlying system based on a state variable description of the nanowire neuron circuit, as follows:

$$\begin{equation}\begin{aligned}\hfill \frac{\mathrm{d}{i}_{1}}{\mathrm{d}t}& =\left({i}_{2}{R}_{1}-{i}_{1}{R}_{\mathrm{h}\mathrm{s}}{n}_{1}\right)/{L}_{\mathrm{n}\mathrm{w}}\left({i}_{1}\right)\hfill \\ \hfill \frac{\mathrm{d}{i}_{2}}{\mathrm{d}t}& =-\frac{1}{{L}_{1}+{L}_{2}}\left({L}_{1}\frac{\mathrm{d}{i}_{\mathrm{i}\mathrm{n}}}{\mathrm{d}t}+{i}_{2}{R}_{1}-{i}_{4}{R}_{2}\right)-\frac{\mathrm{d}{i}_{1}}{\mathrm{d}t}\hfill \\ \hfill \frac{\mathrm{d}{i}_{3}}{\mathrm{d}t}& =\left({i}_{4}{R}_{2}-{i}_{3}{R}_{\mathrm{h}\mathrm{s}}{n}_{2}\right)/{L}_{\mathrm{n}\mathrm{w}}\left({i}_{3}\right)\hfill \\ \hfill \frac{\mathrm{d}{i}_{4}}{\mathrm{d}t}& =\frac{1}{{L}_{1}+{L}_{2}}\left({L}_{1}\frac{\mathrm{d}{i}_{\mathrm{i}\mathrm{n}}}{\mathrm{d}t}+{i}_{3}{R}_{1}-{i}_{4}{R}_{2}\right)-\frac{\mathrm{d}{i}_{3}}{\mathrm{d}t}\hfill \end{aligned}\end{equation} \tag{ 5 }$$

in this case, L_nw(i) is a nonlinear function accounting for the kinetic inductance of the nanowire following the expression from [22]. We define the current i_in as I_in + ∑_k i_syn,k where i_syn,k is the current flowing through R_out from each synapse to the neuron and I_in is as in figure 1. The remaining current variables are further defined in the appendix A.

Note that here we make a simplifying assumption about the dynamics of a superconducting nanowire. We specify a state variable n_i for each nanowire to capture whether the nanowire is in the superconducting (n_i = 0) or the normal (n_i = 1) state. The transition from the superconducting to the normal state is brought about when i_nw(t) > I_c. The transition form the normal state back to the superconducting state occurs when i_nw(t) < I_r.

Similarly, a state-variable description for the synapse is as follows:

$$\begin{equation}\begin{aligned}\hfill \frac{\mathrm{d}{i}_{1}}{\mathrm{d}t}& =\left({i}_{2}{R}_{\mathrm{s}\mathrm{y}\mathrm{n},1}-{i}_{1}{R}_{\mathrm{h}\mathrm{s}}h\right)/{L}_{\mathrm{n}\mathrm{w},h}\left({i}_{1}\right)\hfill \\ \hfill \frac{\mathrm{d}{i}_{2}}{\mathrm{d}t}& =-\frac{\mathrm{d}{i}_{1}}{\mathrm{d}t}-\frac{\mathrm{d}{i}_{3}}{\mathrm{d}t}\hfill \\ \hfill \frac{\mathrm{d}{i}_{3}}{\mathrm{d}t}& =\left({i}_{2}{R}_{\mathrm{s}\mathrm{y}\mathrm{n},1}-{i}_{4}{R}_{\mathrm{s}\mathrm{y}\mathrm{n},2}\right)/{L}_{\mathrm{s}\mathrm{y}\mathrm{n}}\hfill \\ \hfill \frac{\mathrm{d}{i}_{4}}{\mathrm{d}t}& =\frac{\mathrm{d}{i}_{3}}{\mathrm{d}t}-\frac{\mathrm{d}{i}_{5}}{\mathrm{d}t}\hfill \\ \hfill \frac{\mathrm{d}{i}_{5}}{\mathrm{d}t}& =\left({i}_{4}{R}_{\mathrm{s}\mathrm{y}\mathrm{n},2}-{i}_{5}{R}_{\mathrm{o}\mathrm{u}\mathrm{t}}\right)/{L}_{2}.\hfill \end{aligned}\end{equation} \tag{ 6 }$$

We use the same simplifying assumption about the dynamics of the channel of the hTron as we use for the nanowires in the neuron. Transitions to the normal state in the channel of the hTron are brought about after its current surpasses I_c,h and its return to the superconducting state occurs when its current is below I_r,h . To couple neuron and the synapse, we force the hTron channel to switch everytime the neuron fires, that is we set h = 1 whenever n₂ = 1. In an effort to facilitate broad use of this model, we reference the code implementing it here [31].

As an example, using the tool to relate a leaky integrate-and-fire model to the hardware, the following steps are taken to translate the algorithmic description to the hardware:

• (a)  
  The neurons and the synapses between them are configured as specified by the user in their graph description.
• (b)  
  By default, the internal parameters of a neuron $\left({L}_{\mathrm{n}\mathrm{w}},{L}_{1},{L}_{2},{R}_{1},{R}_{2}\right)$ are set to typical values $\left(10\enspace \mathrm{n}\mathrm{H},20\enspace \mathrm{n}\mathrm{H},20\enspace \mathrm{n}\mathrm{H},5\enspace {\Omega},5\enspace {\Omega}\right)$ as are the parameters of a synapse $\left({L}_{\mathrm{n}\mathrm{w},h},{R}_{\mathrm{s}\mathrm{y}\mathrm{n},1},{R}_{\mathrm{s}\mathrm{y}\mathrm{n},2},{R}_{\mathrm{o}\mathrm{u}\mathrm{t}}\right)$ are set to (100 nH, 10 Ω, 10 Ω, 5 Ω).
• (c)  
  u₀ and η are respectively mapped directly to I_bias in the neuron and I_c of the nanowires.
• (d)  
  L_syn is set such that the leakiness parameter $\lambda =\left({L}_{\mathrm{n}\mathrm{w}}/{R}_{2}\right)/\left({L}_{\mathrm{s}\mathrm{y}\mathrm{n}}/{R}_{\mathrm{s}\mathrm{y}\mathrm{n}}\right)$.
• (e)  
  For each synapse, I_bias,h is set such that the current in nw₂ increases by a factor of C_ij . This ratio is maintained across all synapses. Correspondingly, I_c,h is set to be higher than I_bias,h .
• (f)  
  External inputs to the neurons I_i (t) are proportionally mapped to the input currents I_i of each neuron.
• (g)  
  The network is simulated by solving the IVP's of underlying circuits.

In the following section apply the correspondence of our hardware to two algorithmic examples. We simulate Boolean gates and solve special linear systems with our superconducting-nanowire-based neuromorphic architecture. These choices stem from the ubiquitous nature of Boolean gates and algorithms to solve linear systems in classical computing.

In a recent paper by Chou et al [32], non-leaky integrate-and-fire neural networks were shown to efficiently solve linear systems. Here, we demonstrate the computational power of SNNs in simulation by implementing their theoretical models using our superconducting nanowire-based architecture. As a proof of concept, we start with solving a simple two-dimensional linear system. Then, we scale up the problem to a five-dimensional linear system with Laplacian structure.

The motivation for Laplacian linear systems is two-fold: (1) many practical applications and engineering problems rely on solving large Laplacian linear systems such as diffusion models, graph models and random walks; (2) some Laplacian linear systems have infinitely many solutions. Chou et al [32] predicted that a SNN will converge to the solution with the least vector magnitude. We use the approach taken by Chou et al [32] to solve Laplacian linear systems, namely a 2 × 2 and a 5 × 5 system.

To translate a linear system of the form Ax = b to a SNN, we map C_ij to be the elements of the matrix A^T A and I(t) to be the vector A^T b to ensure that the matrix C is positive semidefinite (PSD). The number of neurons in the SNN corresponds to the dimension of A.

For the first example, we attempt to solve the following Ax = b linear system which is already PSD:

$$\begin{equation}\left[\begin{matrix}\hfill 1\hfill & \hfill -0.5\hfill \\ \hfill -0.5\hfill & \hfill 1\hfill \end{matrix}\right]x=\left[\begin{matrix}\hfill 0.5\hfill \\ \hfill 3.5\hfill \end{matrix}\right]\end{equation} \tag{ 7 }$$

We illustrate the network for solving this system and use the tool to handle parameter mapping as in figure 5. The connectivity matrix C_ij from the leaky integrate-and-fire model corresponds to the matrix (−1) × A in the problem. We can then map the elements of matrix A from the problem to the weights of the synapses as shown in figure 5(a). Similarly, the row elements of vector b are mapped to the ramp rates of currents at I_in for each of the neurons relative to the timescale T of the neuron. To apply the leaky integrate-and-fire model, we set the timescale of integration λ = 0.02 to ensure that the current in the synapse decays much slower relative to the decay of current after a neuron spike. Using the tool, we chose α = 0.67 and u₀ = 0.95η.

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The evolution of the system is illustrated in figure 5(c). Initially, neither neuron is firing. As time progresses, the input current to each neuron increases at different rates. Since the external bias for neuron 2 is greater, its potential will increase faster and it will fire earlier. When neuron 2 fires, both of its outgoing synapses are activated. Neuron 2 excites neuron 1 but also inhibits itself. After some time, neuron 1 will fire as a result of the excitation from neuron 2. When neuron 1 fires, it will excite neuron 2 but inhibit itself. As can be seen in figure 5(b), two distinct firing rates emerge from the system. Specifically, we reference the approach of Chou et al [32] to define a firing rate as:

$$\begin{equation}N(t)/t,\end{equation} \tag{ 8 }$$

where N(t) is the cumulative number of spikes at time t. As can be seen in figure 5(b), we find that the firing rate of each neuron converges to the rows of the solution vector of the linear system x = [3 5]^T.

To illustrate the generality of the method, we extend the approach to solving a more complex linear system. We apply the same approach to solving a cycle graph represented by the following Ax = b linear system which is again already PSD:

$$\begin{equation}\left[\begin{matrix}\hfill 1\hfill & \hfill -0.5\hfill & \hfill 0\hfill & \hfill 0\hfill & \hfill -0.5\hfill \\ \hfill -0.5\hfill & \hfill 1\hfill & \hfill -0.5\hfill & \hfill 0\hfill & \hfill 0\hfill \\ \hfill 0\hfill & \hfill -0.5\hfill & \hfill 1\hfill & \hfill -0.5\hfill & \hfill 0\hfill \\ \hfill 0\hfill & \hfill 0\hfill & \hfill -0.5\hfill & \hfill 1\hfill & \hfill -0.5\hfill \\ \hfill -0.5\hfill & \hfill 0\hfill & \hfill 0\hfill & \hfill -0.5\hfill & \hfill 1\hfill \end{matrix}\right]x=\left[\begin{matrix}\hfill -2.5\hfill \\ \hfill 0\hfill \\ \hfill 0\hfill \\ \hfill 0\hfill \\ \hfill -2.5\hfill \end{matrix}\right]\end{equation} \tag{ 9 }$$

We can map again the elements of matrix A to the connectivity matrix C_ij and the elements of vector b to the input currents of the neurons. We use the tool described in the previous section to simulate the system and illustrate the results in figure 6.

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These results can be understood from an energy minimization perspective. When neuron 5 fires, it will excite neuron 4 after a long period of time. When neuron 4 begins firing continuously, neuron 3 will be excited. This same effect will propagate to neuron 2 after a period of time. Neuron 1 will not fire due to the fact that the input current to the neuron is negative. This is illustrated in figure 6(b) where the firing rates of the different neurons have different activation times. It must then be noted that this linear system Ax = b defined by the cycle graph has multiple solutions and the firing rate of our SNN approaches the solution with the least L1 norm as predicted in [32]: $x={\left[0\,1\,2\,3\,4\right]}^{\mathrm{T}}$.

To assess the evolution of the network and determine error in the firing rate, we defined the least square error as follows:

$$\begin{equation}\mathrm{e}\mathrm{r}\mathrm{r}={\Vert}Ax-b{\Vert}/{\Vert}b{\Vert}\end{equation} \tag{ 10 }$$

where the notation ||b|| signifies the magnitude of the vector. We take x to be the instantaneous firing rate vector. We plot the evolution of the least square error in figure 6(c).

We also implement several Boolean gate network examples found in Lynch and Musco's paper [3]. The networks were created using their algorithmic model and then translated into our neuromorphic hardware. Boolean gates are relevant algorithmic examples to convert into neuromorphic computing hardware given their high importance in classical computing and their use in neural networks. Thus, neuromorphic versions of a universal set of Boolean gates could enable computation with both classical and neuromorphic paradigms.

We demonstrate a three-input AND gate network in figure 7. In the following paragraph, we describe the operation of this network using the compositional framework from Lynch and Musco's paper [3]. We understand the operation of the network using the compositional model. The weight of the synapses are taken to be L. When all three of the input neurons fire, the potential of the neuron is −b + 3L and the probability of the output neuron firing is (1 + exp(b − 3L))⁻¹. When only two input neurons fire, the probability of the output neuron firing is (1 + exp(b − 2L))⁻¹. If we take $L=2\,\mathrm{ln}(\frac{1-\delta }{\delta })$ and $b=\frac{5}{2}L$ we can see that the probability of output neuron firing when all three input neurons fire is 1 − δ for δ being an arbitrary small parameter. In practice, the synapse and neuron biasing conditions determine δ, allowing δ to be set arbitrarily close to 0. In a physical implementation of the network, the probability of the output neuron firing can be attributed to current noise which causes fluctuations in the current of the nanowires. If a nanowire is biased very closely to I_c then there is a probability it may switch.

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In addition, we demonstrate a three-input OR gate in figure 8. The input currents and the synapse bias currents are similar to the AND gate. Through an analogous formulation as in the AND gate, we can set the biases in the network such that the output neuron fires with probability 1 − δ when one of the input neurons fires, it fires with probability δ if none of the input neurons fire. Again, δ can be made arbitrarily close to 0 in this model. We can understand this as a threshold problem allowing for the robust implementation of Boolean gates.

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The approach by Chou et al for solving linear systems implemented in this paper is numerically robust. The solution of the Ax = b system is not physically tied to an experimental observable, such as voltage or current. As in [32], the numerical accuracy is a function of the total evolution time of the system. Accuracy can thus be optimized by increasing the time as well as by decreasing the time scale of the components of the circuits. Superconducting nanowires offer rise times on the order of a few ps and relaxation times as short as 2–5 ns from previous measurements [27]. Thus, least-square errors below 10⁻³ might be achieved within tens of microseconds for large networks. The values of the resistors and inductors chosen to set the L/R time constants with the tool do not constraint the time scale of the SNN. Therefore, the solution can be obtained independently of the timing parameters set in the system. The implementation of this approach with superconducting hardware remains to be demonstrated experimentally. In neurons with high fan-in, that is with many incoming connections from synapses, the resistive network connecting a set of synapses to the input terminal of the neuron can result in significant power consumption. Higher current and resistances are needed to account for leakage current in such a network. Some previous approaches [25, 33] have suggested the use of fan-in trees to mitigate this problem which could be beneficial in our architecture. However, using either resistive networks or tree structure would still pose problems with either power or area scaling. An improved architecture for fan-in is needed to break this scaling concern.

The advantage of our architecture is the decoupling of the neuron output to the synapse input via the hTron. Since no electrical connection is needed between the output node of a neuron to a synapse, there is no need for impedance matching. Hence, large fan-out can be achieved by patterning R₂ to allow for heat dissipation at multiple locations where the hTron channels of multiple synapses could be located. However, this of course comes at a cost of higher power needed. An estimation of the power consumption of an implementation of the nanowire neuron can be found in previous work [7].

Due to non-idealities in the fabrication process for superconducting electronics, there can be difficulty in achieving small variance in the resistances, inductances, and critical currents of circuit components. This can lead to a spread in the distribution of the spike rise and relaxation times. However, variance across neurons is masked by the definition of the firing rate. After the network evolves for an appreciable time, the time between the spikes need not matter more than the total number of spikes. The firing rate is thus a robust quantity. Even with non-idealities in the fabrication process, the architecture proposed in this work would not be significantly different from biological neurons and synapses, which intrinsically have variability. Here, we make the assumption that the design of the hTron can be optimized such that the synapses are still activated despite variations in the strength of the voltage spike at the neuron.

While some simple checks are implemented to check parameter ranges that are practically realizable by fabrication, additional experimental verification may still be needed. For instance, the range of synaptic weights in the synapses that can be designed via the inductance of L_syn is limited by the kinetic inductance of the material used. We have chosen NbN with kinetic inductance 33 pH/sq for our tool owing to previous reports of implementations and measurements of nanowire neurons and synapses [7, 25]. To alleviate this problem, higher-kinetic-inductance materials such as WSi with kinetic inductance of 260 pH/sq [34] can be chosen instead. Achieving lower resistances is limited by the presence contact resistance and the inherent variability in fabrication processes. Similarly, the range of synaptic weights is also limited by the design of the hTron. The upper bound for the value of I_bias,h stems from I_c,h . Superconducting nanowires can be designed to have critical currents above 1 mA. However, challenges could arise with the size of components on chip. Larger critical currents typically are obtained from an increase in cross-sectional area of the superconducting trace. As a result, there is a large area cost for synaptic inductors with large kinetic inductances and high critical currents. This constraint may limit the values of C_ij that could be realized.

Another consideration in the design of the circuit network is the readout of the firing rate. For a fully integrated system as in [4], we envision a multi-layered system with readout and control circuitry connected by vias. For the firing rate readout circuit, superconducting counter circuits could be implemented based on nTron devices [35]. Similarly, a hybrid superconductor-transistor approach could allow for readout via classical digital logic [36]. In cases where the spike strength or the weights of the synapses are not known, the linearity of an Ax = b system could be exploited. Instead of using the individual firing rates of the neurons as the components of the solution vector x, the ratio of the firing rates of the neurons could be used instead. Superconducting single flux quantum (SFQ) logic architectures would then be available to realize more complex readout circuits [37] while still offering the advantages of superconducting electronics.

We have taken a simpler approach to modelling superconducting elements to accommodate the possibility of increased scaling. The tool ignores the microscopic electrodynamics of the system and the rigorous electrothermal physics that describes device operation. Instead, the state-variable description of the switching of the nanowires in the neuron and the hTron channel in the synapses is a simplification of the phenomenological models of [22, 25] which is convenient for algorithm designers and avoids non-linearities in the model [23]. For larger nanowires, there may be non-trivial dynamics that would deviate from the lumped element model and discrepancies that could arise from the temperature dependence of the physical parameters.

In the first example presented in the previous section, the tool enabled the translation of algorithmic parameters from the leaky integrate-and-fire model $\left(\lambda ,\alpha ,{C}_{ij},{I}_{i}\right)$ into specifications for the hardware $\left({R}_{1,2},{L}_{1,2},{R}_{\mathrm{s}\mathrm{y}\mathrm{n},1,2},{L}_{\mathrm{s}\mathrm{y}\mathrm{n}},{R}_{\mathrm{o}\mathrm{u}\mathrm{t}},\text{etc}\right)$ with ease. While the approach presented in the previous section of choosing the parameters is not necessarily unique, it is possible for experts outside of superconducting electronics to understand and apply. Hence, there is no expertise in superconducting electronics required to explore further applications. Our superconducting hardware and its associated tool is versatile because it can be associated with many computational models—two are shown in this paper. Superconducting nanowires have also been applied in image recognition, Winner-Takes-All algorithms, stochastic behaviour [29]; and more conventional electronics [38]. By the same token, the tool is not dependent on circuit modelling software such as LTSPICE and uses the more common language of python rather than a higher-level professional language like Verilog A. As a result, the functionality of the tool presented in this work can be similarly extended to other superconducting systems based on Josephson junctions [8, 11, 17], and quantum phase-slip junctions [13, 14] albeit with increased complexity for the component models. Optimizing circuit layouts for power or area given a set of algorithmic constraints would also be an area of extension for the tool. These ideas constitute a useful continuation of this work.