Mathematical model and optimization of a thin-film thermoelectric generator

The thriving of the Internet of Things is set to increase the demand for low-power wireless sensing devices. Thin-film thermoelectric generators are ideal as a sustainable power source for Internet of Things devices as they allow for low maintenance and energy autonomy. This work presents a model to estimate the performance of a thin-film thermoelectric generator. Verified by finite-element method simulation, the results from the model show that increasing the interconnect electrical conductivity and reducing the device pitch increases the power density. The power density can also be increased by increasing the fill factor and reducing the thermal conductivity of the insulating materials. A new corrugated thin-film thermoelectric generator design is proposed in this work that allows for higher fill factors than conventional square designs where a limit on the minimum feature size is imposed, as is the case with photolithography.


Introduction
With increasing interest in renewable energy and energy efficiency, direct thermal to electrical energy conversion via the thermoelectric Seebeck effect has attracted significant interest [1][2][3]. Such devices are constructed by connecting together both n-and p-type thermoelectric material electrically in series and thermally in parallel. Once connected to a load, power will be generated by these devices, depending heavily on the material properties (Seebeck coefficient, thermal conductivity and electrical conductivity) of the thermoelectric materials but also on the device design.
The thriving of the Internet of Things (IoT) has increased the demand for low-power sustainable power sources. Thermoelectric generators (TEGs) offer high reliability, long lifetimes and low maintenance [4][5][6][7][8][9][10]. For thin-film TEGs in particular the advantages are reduction in the use of rare and costly elements by reducing the volume of thermoelectric material [11] and also their possible integration for on-chip cooling or energy harvesting [12]. The reason these devices are well suited for IoT devices is that a heat source could be available at all times, unlike solar energy that is only useful during the day. A lot of research has been going into increasing the figure of merit of thermoelectric materials [13][14][15], but material optimization does not necessarily lead to high-performance devices. These devices must be well designed to minimize the effects of both thermal and electric parasitic resistances to maximize performance. However, device design is often a difficult task as there are many parameters that must be optimized, and these optimizations depend on the application [16,17]. The device performance can be defined either as the power output (or density) for a particular temperature difference or by the conversion efficiency of the device. The importance of each depends on the application: for a system with fixed temperature the power output will be more important and in a system with fixed heat flux the efficiency is a more useful parameter. Original content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence.
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One of the parameters that can have a significant effect on performance is the fill factor (FF). The FF is defined as the ratio between the area of the thermoelectric material and the area of the device. In a fixed heat flux system, such as in wearable technologies [29], it can be shown that there is an optimum FF for a maximum power density, especially where the thermal resistance of the heat source is quite high. In the case of a fixed temperature difference, such as harvesting from temperature-controlled reservoirs/radiators, the power density will increase with increasing FF [6]. However, where the minimum feature size is limited by fabrication or lithography methods, it may be challenging to achieve a large FF.
In this work, a new thermoelectric generator design, a corrugated thin-film thermoelectric generator (CTF-TEG), is evaluated. This architecture uses thermoelectric elements that are long and narrow (typically 1 mm×10 μm) as opposed to the conventional checker-board design in which the elements have equal length and width. It will be shown that this design has a similar performance to the conventional thermoelectric device design. However, the advantage of the design used here is that larger FFs are possible, which can improve power output and efficiency. Using mathematical modelling and finite-element method (FEM) simulations, design parameters such as the FF, pitch and choice of interconnecting material will be optimized for the highest power output and efficiency of a thin-film device operating under a fixed temperature difference.

Methods
A diagram of the thermoelectric generator used in this paper is shown in figure 1. The n-and p-type thermoelectric legs are made of bismuth telluride (the properties of which are taken from the COMSOL material library [30]) and a perfect inverse match is achieved by negating the Seebeck coefficient to reduce the complexity of the calculations. This still gives valid results, as the expected change when using a material such as antimony telluride would be relatively minor. TiN has been chosen for the interconnecting metal due to its high electrical conductivity, high resistance against corrosion and its use as a barrier material. The exact material properties used are shown in table 1.
The devices are 1 mm wide and 1 mm long; the height depends on optimization of the legs, but is usually between 5 and 20 μm. Unlike conventional devices, the thermoelectric leg extends for the full 1 mm, which leads to the FF being related to the pitch and leg width by a linear relation rather than a squared relation. This gives a larger possible range of FFs compared with conventional square devices. These benefits are particularly significant when a minimum limit for dimensions is used, as would be the case when fabricating these devices. Throughout this work, there is either air or silicon dioxide between the thermoelements. Air (or another  Table 1. Material properties used for FEM simulation and mathematical modelling. Properties shown are at 300 K. All properties, unless otherwise noted, are taken from [30].

Material
Seebeck coefficient, material with extremely low thermal conductivity) will give the best device performance. However, the fabrication of suspended interconnects may not always be possible and so an insulating/supporting material of silicon dioxide is used in between the thermoelements. The design is similar to the design proposed in [31], which investigated a design using longer thermoelements but still having multiple rows of these longer elements; their investigation focused on fabrication by folding the substrate. The investigation here is not limited to any particular fabrication method as long as the parameters investigated are able to be tuned to the optimum values.
In this paper optimization of some of the parameters including pitch s, FF ( w s area area TE device = / /, where w is the width of the thermoelements), and interconnect conductivity σ IC will be attempted using mathematical modelling and FEM simulations. A full breakdown of the parameters and ranges of these parameters is shown in Table 2.

Modelling
A simple model (see figure 2) for the maximum power output from a thermoelectric device including parasitic resistances is developed from a single thermocouple of thermoelectric material with metal and thermal contacts on the top and bottom. Extended from a model in [33], this model assumes a constant temperature difference across the device, and that the heat conduction is all in one dimension. This gives the power output as a function of both the thermal and electrical resistances of the active material, insulating material and the contacts:  The power output shown in (1) is a function of the number of thermocouples, N, the Seebeck coefficient (assuming identical n and p material), α, the temperature difference across the device, ΔT, the interconnect and thermoelectric electrical resistances, R IC and R TE , and the thermal resistances of the thermal contacts, electrical contacts, insulating material and thermoelectric legs, R C q , R e q , R i q and R TE q (all resistances are defined in the supplementary material, which is available online at stacks.iop.org/JPENERGY/2/014001/mmedia). This model (figure 2) then leads to the relationships between the power and leg length, area and conductivities by explicitly writing the resistances in full: show a more complete model for the power (P) per unit area (A) when the FF is defined using (5). Equations (3) and (4) show the models for the electrical and thermal power efficiencies (E elec and E thermal ), respectively. Here the influence of the heights of the thermoelements, the electrical and thermal contacts (h, h e , h t ), the thermal conductivity of the electrical and thermal contacts, the filling material and the thermoelectric materials ( , , , t e i TE k k k k ), the FF, the conductivity of the interconnects and resistivity of the thermoelectric material (σ IC , ρ TE ) are shown. The term a (in equation (3)) is a fitting parameter for this model. This is used to correct for the non-uniform current density through the interconnecting material and thermoelements. This current crowding causes the resistance to deviate from the standard formula for a resistor ( l A r , where l and A are length and cross-sectional area). Simulations will then be used to compare the resistance of the interconnects with the calculated value of the resistance to find the function or value represented by a. It can be seen that the value of a is roughly constant at higher interconnect conductivities, smaller interconnect heights (less than 3 μm) and higher FFs, as shown in figure S2. As will be shown later in the paper, these are the conditions for the higher power densities, so throughout the rest of the paper a will be treated as having a constant value of 0.34.

Simulation
Simulations were carried out using COMSOL Multiphysics, a FEM simulation method. The device model used is the same as in figure 1. The models were set up so a fixed temperature difference of 20 K is held across the device giving a varying heat flux dependent on device parameters. The power output was extracted from the voltage across and current through a load resistor that was optimized to give a maximum power output using the optimization method of moving asymptotes [34], a gradient-based form of optimization. The conversion efficiency was found by integrating the heat flux over the device area to give the total input thermal power. The full 1 mm×1 mm device was simulated so to include any edge effects in thermal gradients that would be present in a fabricated device. COMSOL simulations using the thermoelectric effect module will include both the Thomson effect and Ohmic heating, which are neglected in the mathematical model. In both the mathematical model and the simulations, the electrical and thermal contact resistances are neglected. Therefore the mathematical model will be used herein as an estimation of the performance, and the simulations will be used to verify this model by comparing the results.

Leg height optimization
Leg height optimization of these devices at a fixed temperature difference gives a similar trend to [33], as shown in figure 3. For a set of device and operating parameters, an optimum leg height for power output can be identified. This trend is caused by a balance between E elec and E thermal . As the leg height increases the thermal resistance of the thermoelement increases, causing a larger temperature difference across the thermoelement and therefore an increased power density. However, at the same time, as the leg height increases this will increase the resistance of the thermoelements, so the power density reduces. This then leads to there being an optimum point for the maximum power output. As the pitch increases, the maximum possible power density decreases, but the optimum leg height also increases. This is due to the change in relative values for both E elec and E thermal . For the rest of this paper a leg height of 4.5 μm and a pitch of 10 μm will be used unless otherwise mentioned.

Interconnect conductivity
The interconnect resistance reduces the overall power density and efficiency. This parasitic resistance is much more prevalent in thin-film devices as the thickness of the interconnects tends to be of the order of hundreds of nanometres. So then the resistance of these interconnects tends to be of a similar order to the resistance of the thermoelements. The impact of σ IC on the power density depends mostly on the ratio between the interconnect resistance and leg resistance. Fixing R TE and changing R IC by varying the electrical conductivity of the material leads to the relationship in figure 4. As conductivity increases and R IC decreases the power density increases, but this increase is not linear and the effects of the change in conductivity begin to significantly decrease after σ=1×10 7 S m −1 (roughly within 5% of the asymptotic value). This is due to the internal resistance then being dominated by the thermoelectric legs (i.e. R TE ?R IC ).
The increase in FF shown in figure 4 increases the power density but does not affect the relationship with interconnect conductivity, agreeing well with the mathematical model presented in equations (2)-(4). The  . Power density of both a conventional square generator and the CTF-TEG design presented in this paper, and the dependence on interconnect conductivity and FF. Device parameters: s=10 μm, h=4.5 μm, h e =1 μm, h t =0.5 μm. Reference materials from [32] (A), [35] (B) and [36] (C). The points show the simulation results and lines are the results from the mathematical model. differences between the simulated and modelled data can be explained by the absence of the Thomson effect and Ohmic heating (shown in the supplementary material). As interconnect conductivity is changed, both the resistance of the interconnects and the current through the device will change, and therefore the temperature difference across the thermoelements will change. Figure 4 also shows some popular metallic materials as a reference for the reader. Note, however, that values for TiN B , W, Al and Cu are for bulk electrical conductivity and will be reduced when deposited as thin films (similar to TiN A ) modelled by descriptions such as the Mayadas and Shatzkes resistivity model for polycrystalline films [37]. This model takes into account grain boundaries that are created by deposition of thin films, using the average mean free path and distance between grains.
Using a similar method to mathematically model the conventional square design of a thermoelectric generator leads to the same equation as equation (2). The only difference is that the FF is defined as in equation (6). So from the modelling we can conclude that for the same FF, the power density will be almost the same, except for w having different value for the same FF: The difference between the two designs is shown in figure 4, which shows the modelled and simulated power density of the two designs at different FFs and interconnect conductivities. The results from the simulation show that generally the design presented in this paper gives a similar power density to the conventional square design. The real significance is that because of the definitions of the FFs, for a fixed minimum dimension, the CTF-TEG design will always allow for a higher FF, leading to a higher power density. This difference in FF is much larger when the pitch is close to the minimum dimension limit.

Pitch
According to equation (3), the output power is roughly inversely proportional to the pitch squared; this is because as the pitch decreases, R IC also decreases, increasing E elec . This prediction from the mathematical model is shown in figure 5 using thin-film TiN (σ=1.25×10 6 S m −1 ) as the baseline interconnect material. To reduce the effects of pitch in fabricated devices, the interconnect material can be exchanged for one with a higher electrical conductivity, or alternatively h e could be increased to reduce the interconnect resistance. However, it is impractical to achieve such high interconnect conductivity and high h e , in particular in thin-film TEGs.
For devices with interconnect material that has a finite electrical conductivity, reducing pitch improves power performance. This is because the effect of the parasitic interconnect resistance is less significant at smaller pitches. For thin-film TiN of 1 μm, a pitch less than 10 μm significantly improves performance. Another advantage, particularly for IoT applications, is that a smaller pitch, for a fixed device area, increases the number of thermoelements, and therefore the voltage output.

Fill factor
A theoretical prediction of how FF and thermal conductivity of the insulating material (κ i ) affects the maximum power density and percentage of Carnot efficiency (η/η c ) can be found using equations (2)- (5). The input thermal power is calculated by using the thermal resistances in figure 2. The predictions in figure 6(a) show that for smaller pitches (10 μm), power density increases with FF but does not vary strongly with κ i . This can be explained by the reduction in leg resistance due to the increase in cross-sectional area, changing the ratio between R IC and R TE . In addition some changes in interconnect resistance are made by changing the effective conducting length. With larger pitches, figure 6(b) (100 μm), the power density increases with FF, but more significantly at lower FF with decreasing κ i . This is because at smaller FF the decrease in κ i increases the temperature across the thermoelements more significantly.
For smaller pitches (10 μm) the thermal efficiency increases with FF at higher values of κ i , but transitions to a regime where decreasing FF increases efficiency when κ i is lower than κ TE =1.6 W m -1 K -1 , as shown in figure 6(c). The change in the trends of efficiency with different κ i can be explained by the change to thermal resistance in the filling material. With a lower κ i the efficiency increases with lower FF because the thermal resistance of the overall device is higher and so the thermal power input reduces for a fixed temperature difference. With higher κ i the efficiency increases with FF; this is because the thermal resistance of the overall device is not changed much as it is similar to the thermal conductivity of the thermoelectric material. So the increase in power density with increasing FF increases the efficiency. For larger pitches (100 μm) (figure 6(d)) the thermal efficiency has a similar trend, where it increases with high values of κ i and decreases when this is lower than κ TE . The differences between figures 6(c) and (d) for low FF and κ i can be explained by the very low thermal resistance, leading to a much smaller thermal power input and therefore much greater increase in efficiency. Notice also that the power density and thermal efficiency decrease with increasing pitch, as the parasitic interconnect resistance becomes larger and therefore so do the losses.
Simulations using polycrystalline SiO 2 (κ=1.2 W m -1 K -1 ) and air (κ=0.026 W m -1 K -1 ) [30] as filling materials show these trends in figure 7. These simulation results are used to validate the accuracy of the results of mathematical modelling shown in figure 6. There is some error between the mathematical model and the simulations which is due to the simulation including both the Thomson effect and Ohmic heating; also these simulations can more accurately calculate the conduction path through the device, where in the model a correction factor is used. However, the trend of the mathematical model is very similar to the simulated results with a maximum discrepancy between the simulated and calculated power density of ≈15%. This suggests the model is a useful tool for quickly evaluating chosen design parameters for devices. This model could be improved by including boundary thermal resistance [25], electrical contact resistance [38,39], the Thomson effect [40] and Ohmic heating [41]. Another aspect that has been neglected here is the thermal exchange between the device and the heat source; to model this an exact application would have to be decided on and so this has been simplified for any application that could provide a fixed temperature difference at the device level. For this to be included a more complex thermal resistance network would have to used, such as in [41][42][43].

Conclusion
In this work a CTF-TEG has been modelled and optimized for increased power density and efficiency. We found that for a fixed temperature difference, decreasing the ratio between interconnect resistance and the resistance of the thermoelements decreases the losses. Reducing the pitch of the device thermocouples increases the power density by reducing the interconnect resistance and increasing voltage output. Increasing the FF will increase power density for the devices modelled, but depending on the fill material efficiency will either decrease (if the thermal conductivity of the filling materials is less than that of the thermoelements) or increase (if it is larger). As this design allows for a larger FF than the conventional design, especially at smaller pitches, a significant increase in power density can be achieved with this design.
The model provides an easy method for evaluating the performance of a thin-film TEG. It has been shown that the model follows the trends for power density with a discrepancy of ≈15%. This model could be improved by incorporating both the Thomson effect and Ohmic heating.