Low-power-consumption organic field-effect transistors

At present, the electrical performance of organic field-effect transistors (OFETs) has reached the level of commercial amorphous silicon. OFETs show considerable application potential in artificial intelligence, deep learning algorithms, and artificial skin sensors. The devices which can operate with high performance and low power consumption are needed for these applications. The recent energy-related improvement to realize low-power consumption OFETs were reviewed, including minimizing operating voltage, reducing subthreshold swing, and decreasing contact resistance. In this review, we demonstrate breakthroughs in materials and methods to decrease power consumption, providing a promising avenue toward low-power consumption organic electronics.


High-κ dielectrics
High-κ materials, such as Al 2 O 3 (κ~10), HfO 2 (κ ~20), and TiO 2 (κ~41), have been extensively applied to fabricate low-voltage OFETs. Klauk et al demonstrated the OFETs with Al 2 O 3 /self-assembled monolayer (SAM) as the dielectrics on flexible, transparent polyethylene naphthalate [5]. The Al 2 O 3 was fabricated by exposing the thermally evaporated Al to oxygen and SAM was grown atop it to avoid high leakage current. A capacitance of 0.7 μF cm −2 and leakage current of 5×10 −8 A cm −2 were measured for the dielectrics at an applied voltage of 2 V. As a result, the operating voltages of the p-and n-type OFETs were 1.5 V and 3 V, respectively. The static power dissipation of the complementary was less than 1 nW per logic gate, which indicated the successful production of low-power organic circuits with Al 2 O 3 as the dielectrics. More recently, Tetzner et al demonstrated a roomtemperature solution process to fabricate OFETs based on a semiconductor of FS111 [49]. The dielectric (HfO 2 ) was prepared by a sol-gel technique, followed by using photonic curing instead of annealing at 600°C to suppress the leakage current. The electronic measurements revealed a high dielectric constant of 26. The OFETs exhibited field-effect mobilities of 1 cm 2 V -1 s -1 , low subthreshold swing (110 mV decade −1 ), and low operation voltages (< 2 V). Additionally, an electrochemical reaction that processes fully at room temperature can be used for high quality dielectric formation. Metals used as anodes in aqueous electrolytes can form densely packed oxide thin films through anodization. More importantly, the thickness of the oxide was readily controlled by adjusting the anodization voltage. Jinno et al demonstrated the low-voltage OFETs based on an anodized TiO x /SAM dielectric [50]. The dielectric was fabricated via anodization to form a 40 nm thick oxide layer, followed by the formation of a phosphonic acid layer through self-assembly. The TiO x with high-κ nature boosted the unit area capacitance of dielectrics to 3 μF cm −2 and reduced the leakage current ( figure 1(a)). Consequently, the thermal evaporated OFETs turned on at the gate voltage of −1 V gate bias ( figure 1(b)). Apart from oxide dielectrics, applying high-κ polymers is also an efficient way to reduce the operating voltage of OFETs [31,58]. Poly(vinyl alcohol) (PVA) with dielectric permittivity of approximately 7 appeared as a candidate in OFET fabrication. However, PVA has the drawback of instability with moisture because it contains hydroxyl groups. Thus, one common way to improve PVA stability is to crosslink with ammonium dichromate (AD) [59]. The best performance of poly(3-hexylthiphene)-based OFETs was observed with mobility of 0.12 cm 2 V −1 s −1 and operation voltage of −5 V while the ratio of AD/PVA was 25%/75% [51]. Furthermore, incorporating high-κ nanoparticles into polymer can also be utilized to enhance the capacitance of the dielectrics [60][61][62][63][64]. The polymeric-nanoparticle composites not only include the merits of inorganic highκ materials, but also retain the advantages of organic counterparts, such as flexibility and easy processability [62,[65][66][67][68][69]. In 2017, Dastan et al prepared PVA and TiO 2 nanoparticles as the hybrid dielectrics by spin-coating, showing a low leakage current of 2×10 −12 A [70]. Moreover, high-κ ferroelectric polymers, such as polyvinylidenefluoride-trifluoroethylene P(VDF-TrFE), having a promising high dielectric permittivity, are potential candidates as the dielectrics in OFETs. However, the OFETs with these polymers as the dielectrics have the drawback of large hysteresis due to the ferroelectric effect [71]. Baeg et al studied the low-hysteresis OFETs with P(VDF-TrFE) and polymethyl methacrylate (PMMA) blend as the dielectrics [52]. The ferroelectric effect caused by the formation of ferroelectric β-phase crystals can be suppressed by adding PMMA. As a result, low hysteresis and low operation voltage (< 2 V) were realized in the blend dielectrics with P(VDF-TrFE):PMMA proportion of 7:3.

Self-assembled monolayers and multilayers
Other than the above mentioned utilizing high-κ dielectrics in the OFETs, a high capacitance can be realized by applying thin dielectrics. However, this would inevitably result in a markedly improved leakage current due to the defects and tunneling effects at the dielectrics. It turns out that the current leakages can be suppressed by using a highly ordered self-assembled monolayers (SAMs), showing excellent insulating behavior with leakage currents on the order of approximately 10 −8 A cm −2 [72][73][74]. Halik et al found that (18-phenoxyoctadecyl) tricholorosilane can be densely packed on a heavily doped silicon wafer due to the π-π interactions between the phenoxy end groups of adjacent molecules [53]. With a thickness of 2.5 nm, these dielectrics provided a gate capacitance of 0.9 μF cm −2 to afford the OFETs with a field-effect mobility of 1 cm 2 V −1 s −1 , I on /I off ≈10 6 , and operation voltages of 2 V.
In addition to the self-assembled monolayers, self-assembled multilayers have been extensively used as dielectrics in OFETs. Marks et al reported low-voltage OFETs with a three-dimensional-crosslinked dielectric deposited by a solution-phase method [54]. The robust dielectrics comprised as follows: hydrocarbon chains, stibazolium layers, and octachlorotrisiloxane layers. Different combinations with the three kinds of SAMs were tested, and the dielectric (hydrocarbon chains+octachlorotrisiloxane layers+stibazolium layers+octachlorotrisiloxane layers) showed the optimal performance in terms of low leakage (10 −9 A cm −2 ), high capacitance (2.5 μF cm −2 ), and high dielectric constant (16). The OFETs with 2.5 nm thick dielectrics can be operated at low threshold voltages (< 1 V).

Electrolyte dielectrics
Besides high-κ materials and SAMs, a large capacitance can be realized by using electrolytes as the dielectrics due to the formed electric double layers (EDLs) as showed in figure 2(a). By applying a gate voltage, the ions in electrolytes will migrate in the dielectrics and eventually accumulate at the gate-dielectric and dielectric- semiconductor interfaces on the side of the dielectrics. The charges will then be induced and accumulated at the gate-dielectric and dielectric-semiconductor interfaces on the side of the gate electrodes and semiconductors, respectively, thus the formation of EDLs at each interface [75]. EDLs can be regarded as a nanometer-thick capacitor because the distance between ion and charge layers is approximately 1.0 nm. Therefore, the capacitance value above 1 μF cm −2 is commonly attainable with electrolytes. In the following section, we briefly categorize three kinds of electrolyte, including ionic liquid, ion gel, and polyelectrolytes.
Ionic liquid electrolytes have a set of excellent performance, such as high ionic conductivity, negligible volatility, non-flammability, and thermal stability. Panzer et al utilized a solution-processable PEO-LiClO 4 dielectrics to realize a high capacitance of 5 μF cm −2 [55]. As a result, the operating voltage of the pentacenebased OFETs was only 2 V (figure 2(b)). In addition to ionic liquid electrolytes, ionic gel electrolytes have also been chosen as dielectrics to realize a low operating voltage. Lee et al reported 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMI] [TFSI]) based on poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) as the dielectrics [56]. The ion gel films can be easily cut and transferred due to their high elasticity. The films can be directly laminated on the top of the semiconductors without the damage. The prepared ion gel dielectrics exhibited a high capacitance of 10 μF cm −2 (figure 2(c)) and the ion gel-gated OFETs can be operated at a low voltage of 2 V and a high on/off ratio of approximately 10 6 . Besides, an interesting class of electrolytes called polyelectrolytes have been applied in OFETs. Herlogsson et al recently reported a novel solid-state polyanionic proton-conducting electrolyte based on a random copolymer of vinyl phosphonic acid and acrylic acid (PVPA-AA) [57]. OFETs based on a P(PVA-AA) gate dielectric and P3HT semiconductor were fabricated, operating at an applied voltage of −1 V and demonstrating the short response time of 300 μs.

Steep subthreshold slope for reducing power consumption
Reducing the operation voltages by enlarging the capacitance of dielectrics facilitates extraordinary improvements in achieving low-power-consumption OFETs. The subthreshold slope (SS), which determines the gate voltage amount necessary to increase the drain-source current by an order of magnitude in the subthreshold region, must be steep to further reduce the operation voltages [76][77][78]. The SS is expressed as follows:  [55]. Rights managed by AIP Publishing. (c) Capacitance-frequency characteristics for a 10 μm thick free-standing ion gel based on P(VDF-HFP) random copolymer (+) and an ion gel based on poly(styrene-b-methyl methacrylate-b-styrene), (SMS), triblock copolymer (•). Reproduced with permission [56].
where v th is the thermal voltage, D t is the trap density, and C is the capacitance of gate dielectric. The theoretical minimum value of SS at room temperature (T=300 K) for an ideal OFET is approximately 59.6 mV dec −1 . According to the equation, an effective way to realize a steep SS is to enlarge the capacitance of the dielectrics. We have summarized the related work on achieving a high capacitance in section 2. Therefore, the details regarding increasing the capacitance of the dielectrics will not be described herein. Another effective way is to reduce the D t , which comprises the defects in the organic semiconductor bulk and at the semiconductordielectric interface [79]. A steep SS can be achieved via the following approaches: (i) reducing the structural defects of organic semiconductors and (ii) improving the surface quality of dielectrics. In addition, steep SS combined with Schottky barrier OFETs (SB-OFETs) can make a breakthrough in the low-power-consumption OFETs. Recently reported low SS of OFETs are summarized in table 2.  [80]. They estimated that the trap density of semiconductor bulk (D bulk ) was 1×10 13 cm −3 eV −1 , and equivalently trap density of dielectric interfaces (D it ) was 3×10 9 cm −2 eV −1 . This research demonstrated that highly pure organic single crystals were profoundly required to satisfy the demands for high-performance, low-power-consumption OFETs.

Improving the surface quality of dielectrics
Apart from improving the quality of organic semiconductors, modifying the dielectric surface can effectively reduce the trap density of the interfaces. The methods for improving the surface quality of dielectrics include using SAM [81,82,86], modifying techniques to deposit dielectrics [83], and utilizing new organic materials as the dielectrics [26,87]. In the following section, we will focus on these methods reported in the literatures.
The application of densely packed SAM is remarkable for modifying the semiconductor-dielectric interface. For example, -OH groups on SiO 2 substrate, which work as the interfacial charge traps and hinder the charge transport, are abundant. Maeda et al inserted an n-doped LaB 6 layer into the pentacene-SiO 2 interface [81]. Such an interfacial modification method can passivate the interfacial traps and enhance the interface quality. Therefore, a steep SS of 75 mV dec −1 was achieved.
Additionally, conventional deposition methods of ultrathin high-κ oxide dielectrics (HfO 2 , ZrO 2 , BaSrTiO 3 , and AlO x ), such as thermal evaporation, have difficulties in forming a high surface quality dielectric. Optimizing the deposition techniques of oxide dielectrics is necessary due to the significant impact of the semiconductordielectric interface on SS. Yang et al applied a template stripping method to fabricate a single-crystalline OFET based on the anodized AlO x dielectric with a nearly defect-free semiconductor-dielectric interface (figure 3(c)) [83]. Si wafer with atomic flat surface was used as a template in this work. A 100 nm Al was thermally evaporated onto the wafer, and the UV-curable adhesive (optical adhesive, OA) was directly put on the Al surface and pressed using a glass slide. Then, the OA glass was mechanically cleaved from the Si wafer, which induced an Al film with low surface roughness. Therefore, the high-quality AlO x by anodization and the low D it of 1.81×10 11 cm -2 eV -1 was realized. Compared with the conventional thermally evaporated Al thin film with surface roughness larger than 1 nm, the template-striping method can achieve an ultra-smooth surface (roughness can decrease to 0.53 nm). This ultra-flat dielectric combined with a single-crystal 2,6diphenylanthracene semiconductor via physical vapor transport growth was used to fabricate a low-voltage OFET device. As shown in figure 3(d), the ultra-steep SS is 66 mV dec −1 which is ascribed to the high-quality semiconductor-dielectric interface. Furthermore, polymers have considerable potential for reducing the surface trap states of dielectrics. Several polymers with optimized surface and large capacitance have appealing prospects in achieving steep SS. Xu et al used a bilayer structure of atomic layer-deposited alumina and cyanoethylated pullulan (CEP) layer as gate dielectric [26]. The alumina layer suppressed the leakage current, while the CEP layer not only provided a highquality surface but also demonstrated a high capacitance, inducing a steep SS of 66 mV dec −1 . One advantage of polymer dielectrics is that can be formed by the solution process, which can provide a high-quality interface because the surface tension of the solution is beneficial for maintaining an ultra-flat surface when the solution is dried [28,85,88]. Zhao et al used high-κ poly(vinylidenefluoridetrifluoroethylene-chlorofloroethylene) (P (VDF-TrFE-CFE)) copolymer and low-κ poly(vinyl cinnamate) (PVC) as the bottom and top dielectrics, respectively, via a fully solution process to improve the surface quality [84]. By adjusting the thickness of the twolayer dielectric, they found that a considerably steep SS of 64 mV dec −1 was achieved with a thick gate dielectric layer of 364 nm (the thickness of P(VDF-TrFE-CFE) and PVC is 250 and 114 nm, respectively). This method provides a desirable guideline in achieving a steep SS.

Schottky barrier OFET with a steep subthreshold slope
The Schottky barrier OFET with steep SS makes a significant breakthrough in low-power consumption. Jiang et al found that PVC can be used as the dielectric to provide a low trap density interface between the semiconductor and dielectric [87]. The dielectric was also utilized to fabricate a subthreshold Schottky barrier OFET (SB-OFET) through an inkjet-printed circuit technology [79]. The printed dielectric was free of dangling bonds and a smooth semiconductor-dielectric interface was formed. Hence, an ultra-steep SS of 60.2 mV dec −1 , which is the steepest reported SS for OFETs so far, was achieved (figures 4(a)-(c)). Moreover, this excellent dielectric was associated with a good Schottky barrier in the subthreshold regime. The ultra-steep SS for SB-OTETs is important for high tranconductance and transconductance efficiency. Furthermore, the SB-OTFT operation is channel-length independent with a large output resistance (figure 4(d)), which is provided by the Schottky barrier at the source-semiconductor contact. These characteristics are profitable for printed electronics with variations of typical inject-printed feature size. Thus, the SB-OTFT has a high and constant value for high intrinsic gain in the subthreshold regime, which is much larger than that of inorganic SB-TFT and Si-MOSFET. Through the above improvements, the low-voltage, low-power circuits with high gain, high input impedance, and simple and low-cost fabrication OFETs were achieved.

Improving contact for decreasing power consumption
In addition to high gate voltages and subthreshold swings. Huge contact resistance is also a limiting factor in the realization of extremely energy-efficient OFETs. Joule heat will be generated at the electrode-semiconductor area in the OFETs due to high contact resistance (R c ), which is detrimental to the device stability and increases the power consumption. R c generally comprises the injection resistance (R inj ) at the metal-semiconductor interface and the access resistance (R acc ) between the contacting interface and the transport channel ( figure 5(a)) [91][92][93][94].

Improving charge injection
The R inj is caused by the charge-injection barrier between the metal work function and the highest occupied or lowest unoccupied molecular orbits of semiconductors [95]. The currents decrease with the increase of barrier height and barrier width. Therefore, the three major approaches to reduce R inj are as follows: using matched materials as source-drain electrodes, reducing the barrier height by inserting an injection layer between the semiconductor and source-drain electrodes, and decreasing the barrier width by doping the semiconductors [84,85,88].
Graphene is suitable as an electrode due to its high mechanical strength and flexibility. Lee et al reported high-performance bottom-contact pentacene-based OFETs with graphene source or drain electrodes by transferring and patterning CVD-grown monolayer graphene films in a room-temperature process [90]. The contact resistance with graphene electrodes was less than two orders of magnitude than that with Au electrodes ( figure 5(c)). Consequently, the mobility of the pentacene-based OFETs with graphene as the source-drain electrodes was up to 0.6 cm 2 V −1 s −1 , which was 30 times higher than the devices with gold as electrodes ( figure 5(d)). Additionally, inserting a charge injection layer at the metal electrode-semiconductor interface is another common approach to decrease injection resistance. Various materials, such as metal oxide, inorganic salts, and organic compounds, have been used as insertion layers. Kano et al reported high-performance OFETs by inserting a thermally evaporated MoO x layer between Au electrode and C 8 -BTBT semiconductor [89]. The thickness of MoO x layer was examined in the range of 2-30 nm, and then 15 nm was determined as the most appropriate thickness. Figure 5(b) shows that resistance of the devices with the Au/MoO x contact was much lower than that without the MoO x interlayer. The devices with the Au/MoO x contact exhibited large mobility of 2.3 cm 2 V −1 s −1 at low operating voltage, whereas the device without the interlayer exhibited mobility of

Reducing access resistance
With the exception of the injection resistance, another important part of the contact resistance is R acc , which is caused by charge-transport process in the semiconductor from the electrode-semiconductor interface to the active channel. Therefore, the factors that can affect the access resistance basically are: (1) device structures; (2) the quality of the dielectrics, which influence amount of mobility carriers; (3) the thickness of the semiconductors [89,[96][97][98][99].
Depending on the position of the gate and source-drain electrodes, four kinds of OFET structures, namely, bottom-gate bottom-contact (BGBC), bottom-gate top-contact (BGTC), top-gate bottom-contact (TGBC), and top-gate top-contact (TGTC), are related to contact resistance. Peter et al reduced the access resistance by using the TGBC structure ( figure 6(a)) [91]. The TGBC OFETs with C 8 -BTBT as semiconductor exhibited a lower contact resistance of 1.8 kΩ cm than that of BGTC OFETs (200 kΩ cm). As a result, the TGBC OFETs exhibited high average mobility of 5.7 cm 2 V −1 s −1 and on/off ratio of ≈10 9 . Besides, Liu et al found that the quality of dielectrics was important for charge transport because the defects can reduce the amount of mobile charge carries [101]. They used different polymer dielectrics to fabricate C 8 -BTBT-based OFETs. The devices showed that the contact resistance value differed significantly from 10 to 66 kΩ cm relying on dielectrics. Apart from polymer dielectrics, SAM nano-dielectrics can also be adopted for minimizing the contact resistance. The surface energy of SAM can affect the morphology of the semiconductors that in turn affects the transport of carriers. For example, the orientation of the molecules was upright on the SAM-modified Au instead of being flat on bare Au [102]. In addition to device structure and the quality of the dielectrics, many studies demonstrated the reduction of access resistance with the decrease of semiconductor thickness [103][104][105][106][107]. Therefore, twodimensional (2D) organic semiconductors with a few nanometers exhibit excellent contact behaviors, which can effectively eliminate R acc . Wang et al deposited large area 2D molecular crystal via the floating-coffee-ringdriven assembly ( figure 6(a)) [100]. Based on the 2D bilayer crystalline film, the BGTC OFETs were fabricated and exhibited the average and the maximum carrier mobility of up to 5.2 cm 2 V −1 s −1 and 13.0 cm 2 V −1 s −1 , respectively. The estimated contact resistance in the OFET device was only 400 Ω cm.

Other low-power consumption devices
Apart from the switching function, the OFETs can be also applied in emerging energy-related devices, such as photodetectors and non-volatile memories (NVM). Herein, we briefly introduce several new attempts and innovative research on low-power-consumption organic phototransistors and organic-based NVMs.
For the application in the next-generation wearable electronics, the organic photodetectors, which are mainly used to achieve the light detection capability by converting incident light into output electrical signals, have emerged as promising candidates due to their tunable optoelectronic properties, good light sensing performance, biocompatibility, and flexibility [108]. Low-power consumption is required while ensuring the high performance of the devices to promote the application of organic photodetectors in wearable devices. Depending on the requirements of next generation electronics, several ways to achieve low-power consumption have been employed in phototransistors. For instance, Namgung et al utilized ionic liquid as the top dielectric, which can achieve a high capacitance, to fabricate a low-power-consumption multimodal photodetector platform with multilayer transition metal dichalcogenides as the semiconductor. The multimodal photodetector platform combined a lateral phototransistor structure and a vertical large-area Schottky photodiode structure (figure 7(a)) [109]. Then, the organic photodetector can be dynamically selected the following modes: photogating (PG) mode, which can achieve the high optical gain characteristic; and photovoltaic (PV) mode, which can realize the fast response characteristic by controlling the gate and drain voltages. In the PV mode, when a V g =+0.25 V is applied to the ionic liquid gate, a large photocurrent can be observed over both electrodes. The device also showed a high responsivity of 1270 A W −1 with a small V d of 0.5 V. In the PG mode, large negative and positive photocurrents can be measured at V g =−1 V and V g =+1 V, respectively. Therefore, the device both worked at low operating voltage on PG and PV modes.
Increasing the capacitance using high-κ dielectrics is also an effective approach to realizing low-power consumption photodetectors. Jiang et al utilized the high-κ (2-phenylethyl) trichlorosilane and SAM-modified titanium-silicon oxide/hybrid (hTSO) as gate dielectric to fabricate phototransistors with the 5,5′didithienothiophenyl-3,3′-bis(tetradecylthio)-2,2′-bithiophene as the semiconductor ( figure 7(b)) [110]. The high-κ nature of hTSO and the modification of SAM boost the unit capacitance of SAM/hTSO dielectric to 180 nF cm −2 . The organic phototransistor exhibited a high photosensitivity of 3800 and a good carrier mobility of 0.25 cm 2 V −1 s −1 under a low operating voltage of −3 V.
Decreasing the trap density of dielectric interface can also reduce low-power consumption. Xie et al reported a hybrid phototransistor based on perovskite/organic semiconductor hybrid heterojunctions with a layer of [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) coating as a passivation layer. This layer can accelerate the separation of electron-hole pairs and passivate the perovskite to reduce trap states and grain boundaries of the dielectric interface [111]. In the staggered heterojunction, CH 3 NH 3 PbI 3−x Cl x perovskite was used as the light harvesting layer of the photodetector, and the carrier conducting channel of the photodetector utilized poly-(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) ( figure 7(c)). The device can operate with a low voltage of 0.5 V under 598 nm illumination with approximately 44% enhancement in responsivity (2.46×10 9 AW −1 ). PCBM also provided an extra built-in electric field to accelerate the drift of photocarriers and to prolong the lifetime of holes. Consequently, the device can have a response speed of approximately five times faster than that without PCBM coating. In addition to the organic phototransistors, researches on NVMs with low-power consumption have also been made significant progress, which we will briefly discuss as follows.
NVMs, which can be divided into three-and two-terminal devices, show a growing demand for low-power consumption with the development of the artificial intelligence. Three terminal devices, such as OFETs with ferroelectric as the dielectrics (Fe-OFETs), which can function as NVMs have attracted considerable attention for many researchers. The power consumption of Fe-OFET NVMs can be decreased by reducing their operating voltage and promoting data switching. For example, Xu et al utilized a P(VDF-TrFE-CTFE) film with low coercive field to develop a Fe-OFET NVM with low operating voltage. Construction of the compound gate dielectric layer was an ultrathin P(VDF-TrFE-CTFE) film sandwiched in between two layers ultrathin high-κ AlO x [112,114]. The sandwich-structured dielectric layer made a contribution to reduce the operating voltage, depress the gate leakage and improve the mobility. Therefore, the device exhibited a low operating voltage of 4 V and the on-off ratio was over 10 2 at the low P/E voltages of ±4 V. In addition, Pei et al reported ultra-low-powerconsumption memory, namely, C 8 -BTBT-based Fe-OFET NVMs with a high-κ AlO x and ultra-thin P(VDF-TrFE) hybrid dielectric, to reduce the operating voltage and promote the data switching [112]. The device exhibited low voltage, fast operation, and satisfactory performance of low-power consumption due to the ultrathin ferroelectric and the high-quality 2D molecular crystals with excellent charge transport characteristics. The device only needed pJ-level energy consumption ( figure 7(d)). Some properties of NVMs, which can be used for applications out of memory space [114], for example, the two-terminal memristors, are associated with braininspired neuromorphic computing to simulate the functions of biological synapses, thereby functioning as NVMs [115]. Many researchers have explored low-power-consumption flexible two-terminal memristors based on organic materials. For example, Chen et al reported a low-power organic flexible memristor whose architecture was Al/graphene/parylene/W (G-memristor) based on flexible parylene substrates and the insertion of graphene as a barrier layer, which was the main factor of the device to achieve the low-power consumption (figure 7(e)) [113]. Researchers utilized the intrinsic nanopores on graphene with considerable impermeability to limit the diffusion of metal atoms across the architecture and imparted the formation of the fine conductive filaments during the set process to reduce Al and parylene. In addition, the formation and dissolution of the filaments were closely linked to the resistive switching behavior of the devices. Compared with the memristor without the graphene barrier layer, the average reset current of the G-memristor decreased from 2.97 to 0.63 mA and the power consumption reduced from 2.15 to 0.149 mW. The G-memristor also demonstrated a low reset current and a programming power consumption by≈47 and ≈14 times, respectively.

Conclusion
Energy-effective OFETs have progressed rapidly in the recent years. We outlined some of most promising strategies for realizing low-power consumption, including reducing the operation voltage, achieving a steep SS, and decreasing the contact resistance. The high-κ materials, SAMs, and electrolytes show unique advantages in realizing low operation voltage. The OFETs based on low-defect organic semiconductors and high-quality semiconductor-dielectric interfaces exhibit excellent subthreshold properties. The two main approaches in reducing the contact resistance are as follows: (1) tuning the charge-injection barrier between the metal work function and the highest occupied or lowest unoccupied molecular orbits of semiconductors; (2) decreasing the thickness of the semiconductor.
Despite recent successes in energy-efficient OFETs, more research is necessary to overcome current limitations before organic electronic devices can be seamlessly integrated into our daily life. The physical understanding of transport and structure-property relationships further need to be improved, which in turn supports the development of low-power consumption OFETs. Additionally, as most intrinsic organic semiconductors are based on dynamic non-covalent cross-linked bonds, their mechanical properties are sensitive to temperature. Encapsulation can help increase stability of the low-power consumption OFETs to desired levels. Furthermore, although the power dissipation of a single OFET has been achieved a low level, the technology for fabricating energy-efficient OFET arrays still remains a challenge. Therefore, the development of the fabrication process such as patterning technology will be necessary.