Effects of annealing temperature of NbLaO gate dielectric on electrical properties of ZnO thin-film transistor

A bottom-gate zinc-oxide thin-film transistor (ZnO TFT) with high-k NbLaO as gate dielectric was fabricated on indium tin oxide-coated glass substrate by radio frequency sputtering. The NbLaO gate dielectric was annealed in N2 at different temperatures (200 °C, 300 °C, and 400 °C) for 30 min to investigate the effects of the annealing temperature on the electrical properties of the device. It is demonstrated that the ZnO TFT annealed at 300 °C exhibits the relatively good electrical performance with mobility of 20.5 cm2 V−1 s−1, off-state current of 3.4 pA, subthreshold slope of 0.18 V/decade, on/off current ratio of 6.25 × 107 and small hysteresis, which are due to reduction of deep traps in the high-k film or at gate-dielectric/semiconductor interface as supported by using a low-frequency noise analysis.


Introduction
Zinc oxide (ZnO) thin film transistors (TFTs) have been extensively studied due to the desirable properties of ZnO, including large band gap, low processing temperature, and high transparency in the visible range [1][2][3][4]. ZnO TFTs have been reported using many techniques such as magnetron sputtering [5,6], atomic layer deposition [7,8], pulsed laser deposition [9,10], and solution processing [11,12]. High-performance TFTs with high carrier mobility and low operating voltage are required to achieve low power consumption in applications like next generation transparent and flexible electronics [13,14]. In TFT devices, the gate dielectric plays an important role in controlling device performance as well as the semiconductor active layer [15,16]. It is known that conventional gate dielectrics such as silicon oxide (SiO 2 ) and aluminum oxide (Al 2 O 3 ) cannot meet these requirements because of their low dielectric constant, despite some advantages such as good quality interface with the semiconductor and low leakage current due to the large band gap of Al 2 O 3 [16,17]. To further improve the performance of ZnO TFT, various high-k materials have been adopted as the gate dielectric to reduce the operating voltage of the devices and increase carrier mobility. Adamopoulos et al [11] reported that ZnO TFTs with HfO 2 gate dielectric fabricated by spray pyrolysis technique exhibits a low operating voltage of 6 V and electron mobility of 40 cm 2 V −1 s −1 . Song et al [18] used Ta 2 O 5 gate dielectric, and mobility over 50 cm 2 V −1 s −1 and low operating voltage of 4 V were achieved in ZnO TFTs fabricated by radio-frequency magnetron sputtering. Su et al [19] fabricated ZnO TFTs with HfLaO gate dielectric, which resulted in a low operating voltage <3 V and a carrier mobility of 3.5 cm 2 V −1 s −1 . Subramanian et al [20] explored solution-processed ZrO 2 gate dielectric and demonstrated a mobility of 20 cm 2 V −1 s −1 and a low operating voltage <3 V in ZnO TFTs. However, there are several potential disadvantages associated with using high-k gate dielectric in TFTs. For example, defects in high-k dielectrics could lead to defect-assisted current transport such as the Poole-Frenkel effect, which increases the leakage current of the devices. Original content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence.
Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. Nb 2 O 5 , with a high k value (>40), was used as the dielectric layer in metal-insulator-metal capacitor to achieve a high capacitance density of 1.76 fF μm −2 with acceptable breakdown voltage [21], demonstrating its great potential to reduce the operating voltage of TFT. However, Nb 2 O 5 film has high polarizability, small bandgap (3.4 eV) and high defect concentration (10 19 -10 21 cm −3 ) [22], which induces strong Coulomb scattering on charge carriers and high leakage current. Fortunately, it was reported that La incorporation in Nb 2 O 5 gate dielectric could decrease its surface roughness and passivate the defect states at/near the dielectric/ InGaZnO interface [23]. On the other hand, Park et al [24] reported that the performance of ZnO TFTs with SiO 2 gate insulators was improved by rapid thermal annealing. Kim et al [25] reported that the characteristics of ZnO TFT with low-temperature oxide gate insulator were improved by low-temperature annealing. Therefore, the annealing temperature can greatly influence the electrical performance of the ZnO TFTs, but the related reports, especially about the effects of annealing temperature of NbLaO gate insulator on the electrical performance of ZnO TFTs, are still very limited. So, in this work, ZnO TFTs with low-temperature-annealed NbLaO gate dielectric are fabricated on indium tin oxide (ITO)-coated glass substrate by RF magnetron sputtering, and the influence of the annealing temperature on the electrical properties of ZnO-TFTs is investigated. Figure 1 shows the cross-sectional view of the ZnO TFT with NbLaO gate dielectric. ITO-coated glass substrates (ITO acting as the gate electrode) was used to make ZnO TFTs with a bottom-gate top-contact configuration. Initially, ITO coated glass was ultrasonically cleaned in acetone and methanol and then in de-ionized water for 15 min each. After having been dried by N 2 gas, the cleaned substrate was transferred immediately to a sputtering system, and then a NbLaO film acting as the gate dielectric was deposited on the ITO films (six samples) by cosputtering of Nb metal target and La 2 O 3 ceramic target in an Ar/O 2 (24/6 sccm) mixed ambient. During this process, the direct current/RF power for the Nb/La 2 O 3 targets were set as 0.02 A/ 45 W respectively. After that, all the samples were divided into three groups which were annealed at different temperatures (200°C, 300°C, and 400°C) in a N 2 ambient for 30 min. Subsequently, a 65 nm ZnO film acting as the active layer was deposited on the gate insulator by RF sputtering of a ZnO ceramic target (99.99% in purity). The ZnO film was prepared at a sputtering power of 50 W in an Ar/O 2 (24/1 sccm) mixed ambient. Al source/drain (S/D) electrodes were deposited by thermal evaporation through a shadow mask. Finally, the devices were annealed at 200°C for 30 min in N 2 to reduce the contact resistance of the source/drain electrodes. Except the annealing processes, all the other processes were carried out at room temperature. In addition, Al/NbLaO/ITO (MIM) capacitors were also prepared to monitor the gate oxide capacitance per unit area (C ox ) of the TFTs annealed at different temperatures. The channel width (W) and channel length (L) of the device were 350 μm and 100 μm respectively.

Experimental details
The physical thicknesses of the NbLaO and ZnO films were measured by spectroscopic reflectometer (Ocean Optics, NanoCalc-2000). The electrical characteristics of the TFTs and the 1 MHz capacitance-voltage (C-V ) characteristics of the capacitors were measured using a HP 4156 C semiconductor parameter analyzer and a HP 4284 A precision LCR meter, respectively. For the output characteristic (I D -V DS ) of the TFTs, the drain-tosource voltage (V DS ) was increased from 0 to 10 V with a voltage step of 0.2 V, while the gate-to-source voltage (V GS ) was increased from 1 to 5 V with a voltage step of 1 V. For the transfer characteristics (I D -V GS ) of the TFTs, V GS was increased from −5 to 12 V with a voltage step of 0.2 V, while V DS was fixed at 6 V. All the electrical characterizations and C-V measurements were conducted at room temperature under a light-tight, electricallyshielded condition.   with increasing V DS , and then remains unchanged. This unusual saturation behavior can be explained as follows. When the device is in on-state and V DS is smaller than the pinch-off voltage, the channel is in a strong accumulation condition, the donor-like interface traps at the NbLaO/ZnO interface are filled with electrons from the channel because the trap level is below the Fermi level at the surface of ZnO, and so the drain current increases linearly with the increasing V DS due to increasing channel field. But when V DS increases up to the pinch-off voltage, the channel region near the drain is in depletion condition, the donor-like interface traps above the Fermi level is positively charged and so able to capture electrons injected from the source, and thus resulting in a reduction of the drain current. However, when V DS continues to increase to a certain value, the donor-like interface traps above the Fermi level are all basically filled with electrons and do not continue to increase with increasing drain voltage due to the Fermi level pinning effect, and so the drain current remains unchanged for further increase in V DS . In addition, it can be also noted that the sample annealed at 300°C exhibits a smallest gate-leakage current according to the negative drain current at zero V DS under the same V GS . The above analysis indicates that the annealing at an appropriate temperature (e.g. 300°C) can reduce deep traps in the gate dielectric or at/near the NbLaO/ZnO interface. This may be because the densification of the NbLaO film annealed at 300°C is improved to reduce oxide charge, and unsaturated bonds in the NbLaO gate dielectric.

Results and discussion
where C i is the capacitance per unit area of the gate insulator. The subthreshold swing (SS), defined as the gatevoltage change that makes the drain current increase by a factor of 10. From the I D -V GS curve, SS can be calculated Based the SS value, the trap density (N it ) at/near the gate dielectric/ZnO interface can be calculated from where k is the Boltzmann's constant, T the temperature in Kelvin, and q the electron charge. Therefore, the electrical parameters of the devices can be readily extracted from the transfer curves and summarized in table 1.
The sample with the annealing temperature of 200°C shows higher saturation carrier mobility (39.7 cm 2 V −1 s −1 ) than those of the samples annealed at 300°C and 400°C, which are 20.5 and 10.2 cm 2 V −1 s −1 respectively. One possible reason is that large amount of negative oxide charge in the NbLaO gate dielectric with low annealing temperature (as supported by larger V th ) can form a strong electric field to cause repel the electrons in the channel away from the NbLaO surface, thus resulting in weaker surfaceroughness scattering for the electrons. Another possible explanation is that for no annealing or low annealing temperature, the traps are uniformly distributed in the NbLaO gate dielectric and so have a small scattering effect on the carriers in the channel. However, for relatively high annealing temperature, the traps are more concentrated at the NbLaO/ZnO interface, thus causing a decrease in carrier mobility due to more severe Coulomb scattering on the channel carriers [26]. On the other hand, V th decreases weakly from 2.7 to 2.4 V with increasing annealing temperature from 200°C to 400°C, which is possibly due to two factors: one is the increase of C i due to stronger densification of the NbLaO film during the annealing as listed in table 1; the other is that the negative oxide charges in the gate dielectric that can be reduced by annealing at higher temperature. In addition, the ZnO TFT annealed at 300°C exhibits a smaller subthreshold slope (∼0.18 V/decade) and a higher on/off current ratio (∼6.25×10 7 ) than the other two samples. The high on/off current ratio is mainly originated from a low off-state current of 3.4 pA, which is an order of magnitude less than that of the sample annealed at 200°C, and is two times lower than that of the sample annealed at 400°C. The trap density at/near the gate-dielectric/ ZnO interface can be estimated by equation (3) to be 1.6×10 12 , 1.2×10 12 and 3.6×10 12 cm −2 for the annealing temperature of 200°C, 300°C and 400°C, respectively, indicating that the relatively good electrical performance of the ZnO-TFT with the annealing temperature of 300°C is mainly attributed to the low trap density at/near the gate-dielectric/ZnO interface. In addition, the devices for the three annealing temperatures exhibit a low voltage operation (<8 V), which is close to the results reported using Al 2 O 3 and Ta 2 O 5 gate dielectrics [11,27], but is higher than that of HfLaO and ZrO 2 gate dielectrics [19,20], implying that the electrical performances of the device need to be further optimized for the requirement of low power application in flexible and wearable electronics. Figure 4 exhibits the hysteresis behavior of transfer characteristics under forward and reverse V GS sweeps, and the threshold-voltage shifts (ΔV th =V th·reverse −V th·forward ) of the samples with different NbLaO annealing temperatures are listed in table 1. It can be seen from figure 4 that there is an anticlockwise hysteresis phenomenon for the three samples, implying that there are donor-like deep traps at/near the NbLaO/ZnO interface of the three samples. During the forward V GS sweep, the donor-like deep traps start to capture holes (i.e. minority carriers for ZnO channel) in the subthreshold region, thus generating a built-in electric field to enhance the external electric field and so accumulate more electrons in the channel during the reverse sweep. As a result, V th is shifted in the negative direction to produce an anticlockwise hysteresis. However, it is notable that ΔV th of the sample annealed at 300°C (−0.48 V) is much smaller than those of the other two samples (−2.95 and −2.72 V) and close to or less than that of the ZnO TFTs with Al 2 O 3 or Ta 2 O 5 as gate dielectrics [27,28]. The large ΔV th of the sample annealed at 200°C should be due to the stronger moisture absorption of the looser NbLaO film annealed at lower temperature [22]. The densification of the NbLaO film is improved with increasing annealing temperature to reduce the deep traps, oxide charge, and unsaturated bonds in the NbLaO gate dielectric. Therefore, the hysteresis phenomenon is effectively suppressed, together with smallest SS. However, for the annealing temperature of 400°C, the hysteresis phenomenon becomes signification again. It indicates that, compared with the sample annealed at 300°C, there are more donor-like deep traps near and at the NbLaO/ZnO interface which are likely originated from more indium diffused into the NbLaO gate dielectric from the ITO during annealing at a higher temperature, thus leading to the increases of I off , SS and ΔV th .
For further investigation on the interface properties of the TFTs, low frequency noise (LFN) measurements are performed. Figure 5 shows the normalized noise spectral density (S ID /I D 2 ) for the drain current of the samples, measured at the same gate overdrive voltage (V GS −V th ) of 3.0 V and V DS of 3.0 V. All the spectra show a monotonic decrease as frequency increases from 3.5 Hz to 100 kHz, and the LFN follows the 1/ƒ γ behavior for all three devices. However, the frequency exponent γ values are about 1.5, much larger than 1. Moreover, the normalized noise of the sample annealed at 300°C is about two orders of magnitude lower than that those of the other two samples. It is well known that the exponent of 1/ƒ γ behavior in the noise spectral density is closely related to location of the Fermi level, trap distribution, and available energy states within the bandgap of the semiconductor. Christensson et al explained that the power spectral density shows exact 1/ƒ behavior only for dominant oxide traps with uniform distributions over space and energy because only traps around the Fermi level are involved in the noise generation process and traps with different lifetimes are equally distributed [29]. However, if the distribution of traps is not uniform, the spectral density will deviate from the ideal 1/ƒ behavior. Based on this, the results here can be explained as following. When the ZnO TFTs operate in the saturation mode, the channel region near the drain is in depletion due to the high drain bias, and so the Fermi level near the drain region is located near mid-gap. Since the traps near the Fermi level are the only active traps for noise generation, only deep traps participate in the fluctuation of carrier number. Since trapping and detrapping by deep traps require longer time than that by shallow traps, carriers trapping and detrapping correlated with where T is absolute temperature, λ the tunneling parameter conventionally assumed to be 0.1 nm, N t the trap density, and = S S g , V m ID 2 with g m the transconductance. Furthermore, N t can be calculated from figures 3 and 5 to be 6.9×10 22 cm −3 eV −1 , 1.2×10 21 cm −3 eV −1 , and 8.8×10 22 cm −3 eV −1 at a frequency of 100 Hz for the samples annealed at 200°C, 300°C and 400°C, respectively. Therefore, this further supports that the relatively good electrical properties of the sample annealed at 300°C are mainly attributed to the reduction of deep traps in the high-k gate dielectric and at the gate-dielectric/semiconductor interface.

Conclusions
The electrical characteristics of ZnO-TFTs with NbLaO gate dielectric annealed at different temperatures (200°C, 300°C and 400°C) are investigated. The sample annealed at 300°C exhibits the relatively better electrical properties. The mobility, on/off ratio, subthreshold slope, off-state current and interface-state density are 20.5 cm 2 V −1 s −1 , 6.25×10 7 , 180 mV dec −1 , 3.4 pA and 1.2×10 12 cm −2 , respectively, and there is a slight hysteresis phenomenon in the transfer characteristics. The optimized performance is mainly attributed to reduced deep traps in the high-k gate dielectric or at gate-dielectric/semiconductor interface. The optimized device is suitable for low power applications such as flexible and wearable electronics.