Electrical characterization of 2D materials-based field-effect transistors

Two-dimensional (2D) materials hold great promise for future nanoelectronics as conventional semiconductor technologies face serious limitations in performance and power dissipation for future technology nodes. The atomic thinness of 2D materials enables highly scaled field-effect transistors (FETs) with reduced short-channel effects while maintaining high carrier mobility, essential for high-performance, low-voltage device operations. The richness of their electronic band structure opens up the possibility of using these materials in novel electronic and optoelectronic devices. These applications are strongly dependent on the electrical properties of 2D materials-based FETs. Thus, accurate characterization of important properties such as conductivity, carrier density, mobility, contact resistance, interface trap density, etc is vital for progress in the field. However, electrical characterization methods for 2D devices, particularly FET-related measurement techniques, must be revisited since conventional characterization methods for bulk semiconductor materials often fail in the limit of ultrathin 2D materials. In this paper, we review the common electrical characterization techniques for 2D FETs and the related issues arising from adapting the techniques for use on 2D materials.


Introduction
Two-dimensional (2D) van der Waals materials or layered materials are characterized by materials with an anisotropic electronic and chemical structure of strong covalent bonds along the in-plane direction and weak van der Waals bonds along the out-ofplane direction. Among such materials, graphene has been studied most extensively, due to its high mobility, widely tunable carrier concentration, and the occurrence of phenomena such as the quantum Hall effect in atomically thin samples prepared by a simple Scotch tape exfoliation method [1][2][3]. Subsequently, the development of large-scale chemical vapor deposition (CVD) graphene synthesis has enabled the fabrication of wafer-scale electronic and photonic devices [4,5]. Meanwhile, theoretical studies on carrier transport in graphene have inspired experimental research in the fields of condensed matter physics, semiconductor nanoelectronics, photonics, and energy storage [6][7][8].
In addition to graphene, other 2D materials have been investigated with great intensity for future electronic and optoelectronic applications [9][10][11][12][13][14], as these materials offer a range of bandgaps with high carrier mobility and efficient electrostatic control. These properties, combined with mechanical flexibility [15][16][17][18] and tunability of electronic properties, make 2D materials especially promising as a channel material in high-performance 2D fieldeffect transistors (FETs), which could be operated in emerging future mobile and IoT environment [19][20][21][22][23]. In light of this, accurate characterization of 2D FETs and extraction of important device parameters, such as resistivity, carrier density, mobility, contact resistance, charge trap densities, dielectric permittivity, and anisotropy in carrier transport, are essential to explore 2D materials and to correlate them with the performance of 2D FETs [24][25][26][27].
A mainstay of 2D materials-based semiconductor device research focuses on developing FETs with high ON/OFF ratios, high conductivity, high carrier mobility, and low power consumption [24,25,[28][29][30]. It is critically important to understand the electrical properties of such devices, since the use of conventional electrical characterization methods can produce unreliable results when applied to ultra-thin 2D layered materials. For example, room-temperature electrical conductivity in a bulk semiconductor is directly related to charge carrier density. However, conventional implanted substitutional doping cannot be performed on 2D materials due to their atomic thinness. Instead, different methods, such as charge transfer doping, are predominantly used to generate electron and hole carriers in 2D materials [31][32][33], and in few-layer materials, the charge density falls off rapidly away from the surface, rather than being uniform as in conventional semiconductor materials.
Furthermore, the pristine surface of 2D materials forms weak van der Waals bonds with adjacent materials and presents challenges to the creation of low-resistance contacts, by introducing a tunnel barrier for charge carrier transport, whereas the formation of stronger bonds requires disruption of the 2D crystal structure, which introduces defect states. Therefore, it is important to accurately characterize the properties of metal contacts, e.g., contact resistance and metal-semiconductor Schottky barrier [34]. Interfaces between 2D semiconductors and metals are subject to Fermi level pinning due to the tunnel barrier at the interface, defect-induced interface states, and orbital overlap between adjacent heterogeneous materials, requiring precise characterization of the Schottky barrier and Fermi level pinning, which could severely increase the contact resistance at the interfaces [35].
In this review, conductivity, carrier density, mobility, Schottky barrier height (SBH), contact resistance (R C ) and trapped charges are discussed as key parameters for the electrical characterization of 2D devices, constituting the main sections below. Figure 1 illustrates the representative parameters that can be extracted by various electrical characterization methods, including current-voltage (I-V), Hall effect, capacitance-voltage (C-V), and 4-point probe (4PP) measurements, as well as the transmission line method (TLM). Moreover, we also address the correlation between these macroscopic device parameters and the nanoscale properties of 2D materials, visualized using scanning probe microscopy (SPM) techniques.

2D devices 2.1. 2D FETs
The basic structure of a FET comprises of a metallic gate, a semiconductor channel between the source and drain electrodes, and an insulating gate oxide (the barrier between the channel and gate). The current flow in the semiconductor channel (drain current, I D ) is established by the source-drain voltage (V DS ) and is modulated by the applied gate voltage (V GS ) by changing the conductivity of the channel region. Figure 2(a) shows schematic and circuit diagrams of a typical back-gated 2D FET with metallic source and drain contacts and hexagonal boron nitride (hBN) encapsulation [36]. Unlike conventional bulk semiconductor FETs, the presence of metallic electrodes at the source-drain junctions results in Schottky contacts due to a lack of efficient doping techniques. Moreover, back-gated 2D FETs currently in the research stage consist of thick gateoxides (e.g.~300 nm) that require large gate voltages (e.g. >10 V) to switch the device from the OFF to ON states. Besides, back gating affects both the channel and contact regions in a convoluted manner that complicates the gating characteristics of 2D FETs. In this section, we discuss the output and transfer characteristics of back-gated 2D FETs and provide insights into the extraction of fundamental device parameters.

Current-voltage characterization
I-V measurement is the fundamental electrical characterization technique for understanding the working principle of FETs. Also, I-V measurements allow for qualitative and quantitative understanding of intrinsic semiconductor properties such as mobility and carrier density, along with external properties such as interface states and contact resistance. Here, we discuss typical I-V measurement of a 2D FET; the performance of the FET is characterized primarily by measuring the output (I D as a function of V DS ) and transfer (I D as a function of V GS ) characteristics.

Output characteristics
To measure the output characteristics of a FET, the drain current is measured as a function of V DS at different V GS . The output characteristics with a small V DS (figure 2(b)) allow the extraction of important FET parameters as the device acts as a linear resistor in this region. Assuming channel-dominated behavior, the I D for an n-type 2D FET in the linear regime can be expressed as where L, W, µ n , C ox , and V TH are the channel length, channel width, channel electron mobility, oxide capacitance, and the threshold voltage, respectively. We discuss the use of equation (1) to extract the channel mobility and carrier density in the following sections.
In the presence of R C , only a portion of V DS drops across the channel; thus, equation (1) needs to be further modified to address this issue. The effect of R C can be included straightforwardly by replacing V DS with Here, 2R C refers to the contact resistance for the source and drain junction at small V DS . However, the presence of a global back gate (V BG ) in 2D FETs results in simultaneous gating of the contact region, making R C , a function of V GS and V DS . Thus, the linearity of the output characteristics can be used as a simple yet important check to determine the effect of contact resistance on FET performance. Note that, due to the simultaneous gating of the contact and channel regions, contacts can show different behavior (Ohmic or Schottky) at different gate voltages. However, the linear behavior does not provide any information regarding the mechanism behind the Ohmic nature of contacts as doped (gated) Schottky contacts can resemble Ohmic characteristics due to enhancement of the tunneling component at the source junction [37]. Thus, proper extraction of µ n , V TH , and R C is essential to understanding current flow in 2D FETs. The extraction of these parameters is discussed in the following sections.
For use of 2D FET in analog, digital, and high power applications, observations of current saturation over a large V DS window is crucial [39,40]. The current saturation region is characterized by a constant I D independent of V DS , as shown in figure 2(c); I D initially increases linearly with V DS (linear regime) and then saturates at higher V DS . Although several reports have demonstrated current saturation in various transition metal dichalcogenide (TMDC) (e.g. MoS 2 , WSe 2 , WS 2 ) FETs [28,[41][42][43][44], obtaining saturation in 2D devices at desirable values of V DS still remains elusive due to large contact resistance, low channel mobility, and high-field scattering. The application of high electric field without those effects was realized by employing ionic gated transistors [45,46], although it is difficult to use the ionic transistors for practical purposes. Lack of bandgap, weak electrostatic control, and interfacial phonon scattering in graphene are responsible for the poor current saturation seen in graphene FETs (shown in figure 2(d)), which limits their usability in radio frequency applications [38,47,48].

Transfer characteristics
The other way to assess the electrical performance of a FET is by utilizing the transfer characteristics that can be obtained by measuring I D as a function of V GS at constant V DS , as illustrated in figure 2(e). These characteristics are used to extract the parameters, such as transconductance (g m = dID dVGS ), threshold voltage (V TH -the gate voltage at which the FET turns on), and subthreshold swing (SS-the value indicating the sharpness of switching behavior of the 2D FET), as shown in figure 2(f). For an n-channel FET (n-FET), the transfer characteristics display ON-state current (I ON ) for V GS = V DD > V TH (V DD is the maximum voltage supplied to the device) and OFF-state current (I OFF ) for V GS < V TH , and vice versa for a p-FET. Various methods are employed to extract the V TH from the transfer characteristics, such as linear region extrapolation, transconductance linear extrapolation (V GS versus g m ), second-derivative of transconductance, and Ghibaudo's method (intercept of V GS versus I D /g 0.5 m ) [49]. The right y-axis in figure 2(f) displays the g m curve as a function of V GS .
Scaling down the power supply voltage is critical for energy-efficient electronics, and one of the most effective ways to control the power density is to lower the supply voltage. To reduce power consumption, it is necessary to overcome the abruptness (thermionic limit of 60 mV/decade) that originates from the thermal carrier injection mechanism, i.e., thermionic emission (TE). The abruptness of a FET is measured by SS, which is defined as the inverse of the slope of log(I D ) versus V GS curve. The SS determines the gate efficiency of tuning the energy barrier at the source terminal. A small SS over a wide range of current is required to achieve, since it indicates a large I ON /I OFF ratio for small supply voltages.
In the subthreshold regime or OFF state (V GS < V TH ), the subthreshold current is limited by thermal injection of carriers at the source junction and can be expressed as: where q is the elementary charge, k B is Boltzmann's constant, and T is temperature. The SS can be obtained from (3), as follows: where kBT q is the thermal voltage, C CH is the channel capacitance and C ox is the oxide capacitance. For an ideal 2D FET, C CH ≪ C ox in the subthreshold region and thus SS is~60 mV/decade at room temperature. However, most 2D FETs are fabricated on thick SiO 2 substratewith large interface trap density, yielding large SS values (> a few hundred mV/decade). Although unrealistic in practical applications, large C ox can be realized by using ionic gated transistors that results in SS values very close to 60 mV dec −1 despite using 2D Schottky devices [46,50] and also mobility values close to the limitation by phonon scattering [51], making the ionic transistors efficient to quantitatively characterize the electronic properties of 2D materials. The interfacial traps between 2D channels and SiO 2 also induce unwanted hysteresis in the transfer characteristics [52,53]. This can be improved by stacking or encapsulating of the 2D materials with an insulating 2D material such as hBN [54][55][56][57][58]. Moreover, a sub-thermionic transistor mechanism such as quantum mechanical band-toband tunneling can exhibit a steep turn-on with low SS values far below the thermionic limit [59,60].

Conductivity in 2D materials and devices
In an isotropic three-dimensional (3D) material, the electrical resistivity (ρ) and conductivity (σ) are defined as ρ = 1 , where R, A, and L are the total resistance, cross-sectional area (= W × t, where W is the width and t is the thickness of the material), and distance between the measuring points, respectively. Conductivity measurements in bulk semiconductors can be made without fabricating any electrical contacts using standard multipoint resistance measurements; however, the very nature of 2D materials necessitates the formation of electrical contacts in 2D devices to determine resistivity or conductivity [61]. Several studies on thick 2D materials-based devices have demonstrated superlinear behavior (σ ∝ t −k ) of electrical conductivity as  [38]. (e) Transfer characteristics of the WSe2 device showing good subthreshold swing and low drain-induced barrier lowering [36]. (f) Transfer curve (left) and transconductance (gm) (right) characteristics of an ideal n-type FET with respect to VGS. For a better FET switch-on characteristic, the slope in the subthreshold region (VGS < V TH ) should be sharp. The transistor is switched on when VGS is equal to the maximum voltage supplied to the device, VDD. a function of sample thickness [62,63]. The superlinear behavior in such structures is attributed to the non-uniform current distribution in thick 2D materials that results from gate-dependent carrier density profile and interlayer resistance [37]. This is further accentuated at the limit of 2D materials (~10 layers in the study cited here) where conductivity is observed to exhibit non-monotonic thickness dependence due to the interplay between mobility and carrier density [64]. Besides, conductivity in 2D materials also shows a large degree of inter-sample variation due to unintentional doping from substrate , ambient surroundings, and sample preparation methods [65][66][67][68]. Therefore, the conductivity/resistivity of fewlayer 2D devices is determined in terms of channel resistance (R CH ) or sheet resistance (R SH ), which is a more straightforward way to evaluate current flow in 2D materials. Typically, R CH and R SH can be determined by fabricating 2D FETs and measuring the output/transfer characteristics at varying V GS using either a 2-point probe (2PP) or 4PP technique, as discussed in the following sections.

2-point probe measurements
Standard 2PP measurements refer to measurements in which the current and voltage are assessed and applied by the same terminals. Over time, 2PP measurement has become a standard method of obtaining the output and transfer characteristics of a 2D FET. Figure 3(a) displays the individual components of the total resistances (R Total ) in a ReS 2 -based 2D FET; the corresponding 2PP output characteristics at different V GS are illustrated in figure 3(b) [69]. Assuming R CH > R C along with linear I D vs. V DS characteristics, R CH , R SH , and σ can be determined by using the following relationship: where t CH refers to the thickness of the 2D semiconducting channel. The presence of back gate results in gate voltage-dependent R CH values indicating the gating behavior of channel conductivity. Similar results can also be obtained from the transfer characteristics, which provide gate-dependent R CH at constant V DS . However, in many cases, the contact resistance in back-gated 2D FETs is either comparable to or higher than the channel resistance, resulting in significant errors in the R CH value extracted using 2PP measurements [72]. This issue can be resolved by using 4PP method, which can deconvolute the effect of R C on the extracted R CH and R SH values [73,74]. , (c) Comparison between 2PP and 4PP measurements, respectively, of ID as a function of the VDS for a few-layered ReS2-FET device [69]. (d) Schematic of a monolayer MoS2 device with 4PP contact configuration. (e) 2PP and 4PP conductance, which shows different V TH readings due to differences in channel and contact gating. (f) Higher mobility in 4PP measurements illustrating the impact of contact resistance [70]. (g) Schematic of a multilayer MoS2 device with van der Pauw contact configuration [71]. (h), (i) Different van der Pauw configurations for measuring the sheet resistance of the same MoS2 device at different gate voltages.

4-point probe measurements
As discussed above, 2D devices suffer from large contact resistances, which make it difficult to explore channel-dominated behavior and result in wrong inferences. Here, 4PP measurements are used to measure R CH independent of R C . Figure 3(c) shows the output characteristics of a ReS 2 device obtained using 4PP measurements, which reveal a higher device current at the same V DS when compared to 2PP measurements. The inset in figure 3(c) illustrates the schematic and equivalent circuit of the 4PP structure used for the measurement. Accurate conductivity measurements using the 4PP method are typically enabled by the Hall bar and van der Pauw geometry, as addressed below, which can be extended further to determine carrier density and mobility from magneto-transport measurements.

4PP measurements with hall bar geometry
Generally, 4PP measurements in 2D materials-based devices are done on devices in which the contacts and channel region are patterned in a Hall bar geometry, as shown in figure 3(d) [70]. In this structure, the voltage probes (other than the source and drain contacts) minimally affect the current flow in the channel material and thus act like perfect voltmeters. The source and drain (S/D) probes are used to source/measure I D , and V 1 and V 2 between S/D are used to sense the voltage difference (V 12 = |V 2 − V 1 |); in turn, these measurements are used to evaluate the intrinsic transport properties of 2D materials by deconvoluting the effects of R C . Compared to the 2PP measurements, the 4PP measurements result in smaller R CH as only a portion of applied V DS drops across the channel region. Here, R CH can be extracted from the 4PP I-V characteristics by using the following relation: where L 12 is the distance between voltage probes in the middle of the device. Consequently, R C -corrected R SH and σ values can be calculated from equations (5) and (6). Finally, the 4PP characteristics can also be used to calculate R C by subtracting the extracted R CH value from R Total . Thus, 4PP measurements provide an easy and efficient means of extracting both R CH and R C . The 2PP and 4PP measurements of the transfer characteristics of a 1L-MoS 2 device are shown in figure 3(e). These measurements provide different values of V TH (using the linear extrapolation method), which implies different gating properties of the channel and the contact regions due to differences in the band movements in the channel and contact regions [75]. Figure 3(f) shows higher 4PPthan 2PP-mobility due to the presence of substantial contact resistance. The results show that 4PP measurements are necessary to accurately calculate the intrinsic conductivity, unveiling true channel mobility, carrier density, and contact resistance as discussed in later sections.

4PP measurements with van der Pauw geometry
Because exfoliated 2D materials come in irregular shapes, 4PP measurements with Hall bar geometry generally require reshaping of the channel material; this involves fabrication steps that could alter their intrinsic properties as 2D materials are highly sensitive to surface treatments. In this respect, the van der Pauw method is advantageous for measuring the sheet resistance of graphene and 2D materials as it does not require channel patterning in regular shapes [76].
In van der Pauw measurements, four contacts are placed at the edges (periphery) of a flake as shown in figures 3(g)-(i); a constant current flows between adjacent pair of contacts (1-2 or 2-4), and the voltage drops are measured between another adjacent pair of contacts (3-4 or 1-3). Although van der Pauw measurements for bulk semiconductors do not require channel reshaping, typical Van der Pauw measurements for 2D materials often utilize regularshaped flakes (or flakes patterned in regular shapes, e.g. square, rectangular, or circular shapes) due to the convenience in analyzing experimental results. For a square channel geometry, two sets of measurements are performed to include vertical and horizontal conduction in the flake , resulting in the following sets of resistances: Then, an average resistance is calculated for sets A and B, which can be expressed as: Finally, sheet resistance and conductivity are calculated using the following relation: Similar expressions can be obtained for other channel shapes [77]. Since contact resistance is usually large in TMDC 2D FETs, accurate extraction of R CH and R C using van der Pauw measurements becomes highly difficult even after reshaping the flakes in regular forms. Thus, the 4PP measurements using Hall bar geometry are more prevalent in the 2D community.

Challenges of 4PP measurements
Although 4PP measurements are a powerful tool for the electrical characterization of 2D materials-based devices (electrical conductivity in this section), certain experimental considerations need to be satisfied to ensure accurate measurements and data extraction.
(i) Accurate 4PP measurements require the channel region to be patterned (reshaped) in a way that avoids the impact of voltage probes on the current flow in the channel region, e.g. Hall bar or van der Pauw (square, circle, cloverleaf, etc) structures [78]. This requirement is especially critical for few-layer 2D devices, where the presence of voltage probes directly on the channel (as in the case of TLM) can severely affect the current flow in the underlying channel. Similarly, in 4PP measurements with a non-Hall bar patterned channel, the intrusion of voltage probes into the channel region affects the local electric field and current flow in the channel region and thus can result in erroneous extraction of R CH , R SH , and R C [79]. (ii) Another consideration in measuring a 2D FET using differential measurements (such as lock-in amplifier-based measurements) is understanding the role of the common-mode rejection ratio (CMRR) [80]. In 4PP measurements, the drain voltage is often biased at high drain bias (V DS > 1 V) compared to the source, which is often held at ground voltage. In the presence of large R C , this leaves the middle voltage probes measuring a small differential voltage on top of a large background common voltage of VDS 2 . Thus, the rejection of this common voltage is crucial for accurate 4PP measurements. This limits the utility of the 4PP measurements in 2D devices biased at low gate voltages. For example, a typical CMRR of 100 dB with V DS = 1 V results in ±5 µV of common mode voltage. This limits the voltage range for the middle probes to, at minimum, ±100 µV to achieve >95% accuracy. (iii) A logical yet often ignored consideration in 4PP measurements is the extremely small magnitude of the voltage drops across the voltage probes due to the presence of large R C at the source and drain junctions, especially when the device is in the OFF state. In the OFF state, both source and drain regions are completely depleted and thus the contact resistance is substantially high. Almost all of the source-drain bias is dropped across the source and drain regions, so the voltage probes have to measure extremely small voltages. These voltages are difficult to measure with most standard source measuring units. As a result, contact and channel resistance measurements in the OFF state are often erroneous. (iv) Since Ohmic contacts are essential for calculating accurate sheet resistance using van der Pauw measurements, a reciprocity check needs to be conducted to ensure proper van der Pauw measurements in the case of 2D Schottky contact devices. The RA RB ratio is often calculated to determine the reliability of van der Pauw measurements [81,82].

Doping in 2D materials and devices
Electrical conductivity is further related to extracting charge carrier density using the relation σ = 1/qnµ, where q is the elementary charge, µ is the carrier mobility, and n is the carrier density. Carrier density in a semiconductor can be tuned with substitutional doping; however, substitutional doping is very difficult in 2D materials due to their nanometer-scale thickness. Despite this limitation, there have been a few reports on substitutional doping in 2D materials. For example, group-V elements such as niobium and group-VII elements such as rhenium can be substitutionally incorporated during growth into the crystal lattice of group-VI TMDCs, yielding p-type and n-type semiconductors, respectively [83,84]. However, the doping density is significantly limited by the solid solubility, thickness, and binding energy of the 2D materials [85]. For example, although a high substitutional Nb dopant concentration up to 10 14 cm −2 (10% Nb concentration) has been achieved in monolayer CVD grown WS 2 , the estimated active dopant density according to the electrical properties was onlỹ 6 × 10 12 cm −2 (approximately 0.06 charges induced per dopant), as evidenced by non-degenerate behavior of transfer curves [86]. Furthermore, charge transfer doping of 2D materials, which is based on their interaction with adlayers, atoms, or molecules, has also been widely studied as an alternative [31-33, 41, 44, 87-96].
Generally, in conventional semiconductors, the doping concentration at room temperature is assumed to be the same as the free carrier concentration, because free carriers such as electrons or holes are generated from fully ionized dopant atoms, which are embedded in the semiconductors by an ion implantation process followed by an activation process using high-temperature annealing. Therefore, doping concentration in bulk semiconductors can be estimated by various methods, e.g. secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, and I−V (C−V) characterization. By contrast, doping density in 2D materials is either induced by electrostatic gating or charge transfer, which directly modulates the free carrier density in the material and therefore is primarily determined by electrical characterization.

Doping density from current-voltage characterization
The carrier density of a semiconductor can be modulated by electrostatic gating in a FET configuration. In this configuration, the two metal electrodes (source and drain, S/D) are used to monitor its conductivity, while the third electrode (gate, G) induces free carriers in the channel material across a gate dielectric material. Here, the carrier density above V TH can be estimated by where C ox is the oxide gate capacitance per area (for example, 11.5 nF cm −2 with 300 nm SiO 2 [84]). Note that equation (10) assumes that the device is channel-dominated for V GS > V TH ; however, it is not operated in a quantum-capacitance dominated regime. For a channel-dominated WSe 2 device with low R C , good linearity in the transfer curve for a WSe 2 FET is observed for V GS > V TH and thus the carrier density extracted from the equation at high V GS (1.6-4.3 × 10 12 cm −2 ) is in good agreement with that measured using the Hall effect (1-6 × 10 12 cm −2 ) [36]. For 2D materials, the doping density is nearly equal to the free carrier density, since it is mainly induced by the application of gate biases without external doping. When the doping is generated by external processing instead of gate biasing, the induced doping density can be determined by the shift in charge-neutral points (CNPs) or threshold voltages in the transfer curve according to ∆n = C ox (∆V CNP or TH ) /q [97,98].

Hall effect measurements
Hall effect measurements are widely carried out to extract the intrinsic material properties of a semiconductor such as carrier density, type, and mobility. Figure 4(a) illustrates how an electron moves in a conductive channel under applied longitudinal electric and perpendicular magnetic fields. The underlying principle of the Hall effect is based on the Lorentz force [99]. An electron flows (in the opposite direction to the current) along the channel in the presence of an electric field E x with drift velocity υ. When a perpendicular magnetic field B z is applied, the electron experiences Lorentz force, resulting in a voltage difference (Hall voltage, V H ) transverse to the flow of the electron. The sign of V H depends on carrier type (electron or hole), and the value of V H varies depending on the carrier density, current, and magnetic field. Two typical device structures are used for Hall effect measurements: (1) van der Pauw structure (see figures 3(g)-(i)), and (2) Hall bar structure. Figure 4(b) shows a typical bridge-type Hall bar structure device, which is widely used for Hall measurement of 2D materials. ASTM International provided a guideline for the device geometry of a sixcontact device: It requires that 1.0 ≤ L 2p ≤ 1.5 cm, although it is very difficult to achieve a centimeter-sized device with good uniformity when working with 2D materials.
Hall effect measurements are usually conducted with a sinusoidal AC or DC drain current, I D , flowing through the channel of the device (figure 4(b)), and V H is measured while B-field is swept at a fixed V GS , as shown in figure 4(c). It should be noted that the use of AC measurement with lock-in amplifiers often has a significant advantage over the DC measurement, since V H is usually in the range of 1-10 µV with a current of 100 nA and a B-field of 1 T, which cannot be observed with conventional DC source measuring units. To make the DC measurements possible, a higher current is required at the same B-field, which in turn results in many unfavorable effects due to threshold voltage shift, Joule heating-induced breakdown, and phase transition [101][102][103]. Furthermore, the sheet carrier density is calculated from the following equation: This is a simplified equation by taking the Hall scattering factor (r, generally between 1 and 2) as unity; it should be multiplied by r to the equation  [30]. It should be noted that n 2D can also be determined from the van der Pauw structure by measuring differential voltages along diagonal direction (e.g. V 14 and V 23 in figures 3(h) and (i)) under the presence of a magnetic field. Without the Hall scattering factor, the extracted n 2D for undoped 2D semiconductors typically ranges from 0.5-6 × 10 12 cm -2 with back gate voltages applied across 300 nm SiO 2 at room temperature [36,104]. The advantage of this method is that any geometric non-uniformity in the devices can be eliminated by extracting the inverse of the slope of a linear curve. As shown in figure 4(c), nonzero V H at zero B-field due to the non-symmetric geometry, carrier inhomogeneity, and contact resistance can be observed in typical measurements, which can vary depending on the applied V GS . The R SH and Hall mobility (µ H ) values extracted from the Hall effect measurements are described in section 5.1 below.
Apart from Hall effect measurements, the carrier density in 2D materials can also be determined by observing the Shubnikov-de Hass (SdH) effect where the oscillatory behavior of ρ xx is observed in the presence of magnetic fields, as shown in figure 4(d). For 2D devices with moderate electron/hole mobilities, SdH oscillations are usually observed at ultra-low temperatures (a few kelvins) and in the presence of a large magnetic field [2,3]. Over the years, techniques such as van der Waals-based assembly [105], full device encapsulation, and clean contact fabrication have enabled the observation of SdH oscillations at moderate magnetic fields (<5 T) from graphene [106,107] and other 2D semiconductorbased devices [108,109]. In this regard, the SdH effect has become an important measurement tool to determine important material parameters: (i) Quantum mobility (µ q ) from the relation, µ q ≈ 1 Bq where B q is the magnetic field referring to the onset of SdH oscillation [57]; and (ii) carrier (electron) density from the slope of 1/B versus index of SdH minima by the relation n = 2q , where B m is the magnetic field at minimum ρ xx and h is Planck's constant. Thus, the Hall effect measurement along with SdH oscillation is a very powerful and effective technique to characterize carrier density in 2D materials.

Mobility
Two forms of mobility are typically extracted in 2D devices-Hall effect mobility and MOSFET mobility. Both extraction techniques have their pros and cons. µ H extraction has an advantage in that it independently measures both resistivity and carrier concentration. Its key disadvantage is that it requires a specialized Hall bar structure (or other suitable geometries with small contacts at the edges of the structure) and the Hall scattering factor (r), is often unknown and simply assumed to be one. MOSFET mobility, on the other hand, comes in many flavors-effective mobility, field-effect mobility, and saturation mobilitydepending on how it is extracted. Its main advantage is that MOSFET mobility is extracted in a region of operation that more closely resembles true device operation; however, much care must be taken to ensure that the model used for mobility extraction correctly models the device current and the carrier density of the channel.

Hall effect mobility
The standard procedure to measure the µ H is to pattern the semiconductor into a Hall bar structure with contacts placed on the fingers, as shown in figure 4(b). In the typical approach for measuring the µ H in 2D devices, a constant current is flowed between the source and drain contacts, while a magnetic field is applied normal to the plane of the semiconductor. Hall effect mobility measurements benefit from the independent extraction of the carrier concentration in the channel. In quasi-equilibrium, zero current flows along the width of the device. Therefore, the total force along the width must be zero, satisfied when the Lorentz force is zero, which gives E y = υ x B z , where x is along the length, y is along the width, and z is perpendicular to the 2D semiconductor channel. The general expression for current flow is given by I D = qWυ x n 2D . By defining the Hall voltage as V H ≡ E y W, we find that V H = IDBz qn2D , (see equation (11) for n 2D ). From the measurement of V xx shown in figure 4(b), the R SH of the channel can be determined by Using R SH = 1 qµnn2D , we find the Hall effect mobility to be where the value of n 2D is given by equation (11) and µ n = µ H is assumed (which is only valid for a Hall scattering factor of 1). This assumption is further discussed in the following section. As discussed in the previous section, the quantum mobility can also be obtained from the onset of SdH oscillations by Hall effect measurements (e.g. the onset of SdH oscillation occurs at B = 1 T, µ q = 10 000 cm 2 V·s −1 ) [57].

Challenges of Hall effect measurement
In principle, the measurement of µ H is straightforward, but in practice, several difficulties arise, complicating the measurement on 2D materials. The first challenge is that the Hall effect measurement requires a specialized structure, ideally following the guidelines of ASTM Standard F76 [100]. The structure should be designed such that the contacts lie as close to the edge of the sample as possible. The flakes can be etched into the desired geometry, but doing so has a negative consequence that the lithography and etch process may adversely decrease the mobility from its value in a pristine state. This is especially concerning for the mobility measurement of ultra-thin samples, where surface contamination can greatly affect the material's mobility. Another practical challenge for measuring Hall mobility in 2D materials is that V H can be quite small, making measurement difficult. V H is proportional to current per unit width, which is often less than 1 µA µm −1 for ultra-thin samples. V H can have an offset (i.e. V H ̸ = 0 for ⃗ B = 0 as shown in figure 4(c)) due to asymmetry in a Hall bar geometry so the difference in Hall voltage at different B-fields must be used instead of a single B-field measurement. A specialized probe station is typically required to obtain a large B-field, often involving the use of a cryostat with a cryogenic superconducting magnet. The AC Hall effect measurements, where a coil is used to generate the AC magnetic field, which is advantageous over DC measurement as it enables fast and low field measurements <0.1 T, can also be used [110].
Although it is not often done for 2D materials, the sample (mostly graphene) can also be measured while placed atop a permanent magnet that is flipped between measurements to give a positive and negative B-field [111,112]. Unfortunately, many back-gated devices that are pervasive across the 2Dmaterials community show significant hysteresis [52,113] (or even worse, device degradation) from measurement to measurement, which makes the differential extraction between the positive and negative B-field measurements prone to hysteretic error. A solution to overcoming this problem is to perform repeated measurements, switching back and forth between +B z and -B z , to verify that the data is stable.
Another, often overlooked, error in the measurement of µ H arises from the assumption of energyindependent scattering in the semiconductor, which is generally only valid at very high magnetic fields (≫1 T) or for neutral impurity scattering. Energydependent scattering is captured in the Hall scattering factor, r = ⟨τ 2 ⟩ ⟨τ ⟩ 2 (1 < r < 2), where τ is the mean time between carrier collisions and ⟨τ ⟩ is the average over energy. The Hall scattering factor can be determined at a specific B-field by r = RH(Bz) RH(Bz = ∞) . Including this factor, the carrier concentration becomes and the conductivity mobility equals Therefore, the µ H can over-predict the conductivity mobility by up to a factor of 2. All in all, Hall effect measurement is a powerful technique to measure carrier mobility in 2D materials; however, the technique is not without challenges and complications.

MOSFET mobility
In contrast to µ H , MOSFET mobilities can be extracted from the measured transistor characteristics. MOSFET mobilities come in two flavors: effective mobility and field-effect mobility. Figure 5 illustrates the MoS 2 MOSFET characteristics employed to extract the effective and field-effect mobilities [114].

Effective and field-effect mobilities
Effective mobility is extracted from the drain conductance of a MOSFET biased in the linear regime. A general expression for the drain current of a MOSFET with a negligible diffusive current at small V DS can be written as where Q n = C ox (V GS − V TH ) is the sheet charge density of the channel, µ eff is the effective mobility, and kT is the thermal energy. Ideally, Q n is determined through independent capacitance or Hall effect measurements of the MOSFET structure; however, given the small size of many exfoliated samples, the capacitance of 2D MOSFETs is not typically measured as the signal is much too small and complex to reliably detect using conventional techniques. For an ideal device, effective mobility is then given by where g d is the drain conductance given by g d ≡

∂ID ∂VDS constant VGS
, as shown in figure 5(a). If the output characteristics do not exhibit a linear dependence on V DS around the bias point for which the mobility is extracted, the extracted mobility is suspect since the device characteristics do not follow equation (16) from which µ eff is derived. Similarly, if the transfer characteristics do not exhibit a linear dependence on V GS around the bias point for which the mobility is extracted, the use of the equation to determine Q n is highly suspect since the device behavior does not fit the charge model. Field-effect mobility is derived from the transconductance g m = ∂ID ∂VGS constant VDS of a MOSFET biased in the linear regime as shown in figure 5(b), which is given by For conventional MOSFETs, extracted µ FE is often less than the µ eff due to effective-field dependence of the mobility. When considering this dependence, the transconductance becomes Since µ eff decreases with increasing effective field, ∂µ eff ∂VGS is negative and the measured transconductance is less than what would ideally be expected. The dependence of the µ eff on V GS is often expressed in terms of the effective vertical field, where µ o , α, and γ are constants, and ε eff is the effective (vertical) field in the semiconductor channel. However, the change in µ eff with V GS is proportional to the change in ε eff with V GS , which is small for backgated 2D devices with thick oxides. Furthermore, for ultra-thin few-layer 2D MOSFETs, the majority of the channel charge is already present near the channel surface [37], which further suggests that the gatedependence of µ eff will be less than that of conventional devices.

Errors due to contact resistance
Large contact resistance is a common problem in 2D devices that limits the accurate extraction of MOS-FET mobilities. In conventional MOSFETs, R C is often determined from TLM structures, and the extracted mobilities can be corrected for degradation due to R C . In principle, the same TLM can be applied to 2D MOSFETs; however, often large device-to-device variations make it difficult to achieve reliable and trustworthy results when applied to 2D materials. Moreover, the mobility extraction from the contactlimited devices can be problematic since V TH is not the onset voltage where the channel is depleted which gives inaccurate charge density Q n . One way to circumvent the problem of R C is to fabricate four-probe structures similar to those used for Hall effect measurements as shown in figure 4(b). In such a structure, the voltage drop between the middle contacts is measured (V xx ), while V DS is applied between the source and drain contacts. This four-probe drain conductance is defined as g The measured potential is changed by varying the applied V DS . In this way, the effect of the contacts is removed from the extraction procedure. The measured potential across the channel may be quite small and perturbation of potential distribution due to the device geometry (e.g. size of voltage sensing probes [115]) may affect the ability to accurately determine the modified drain conductance. The dual-gate structure makes it more complicated due to the contact turn-on effect tending to overestimate mobility unless thorough characterization to minimize measurement artifacts and systematic simulation are considered [116]. Nevertheless, due to the often large and variable R C in 2D MOSFETs, four-probe measurement presents the best technique to accurately determine channel mobility for both Hall effect and MOSFET mobility measurements.

Contact resistance (R C ) and Schottky barriers 6.1. Contact resistance in 2D devices
Lack of simple, efficient, and controllable doping techniques for 2D materials results in large R C at the metal-semiconductor junction. R C depends on the nature of the barrier, i.e., its width and height, since barrier sensitively affects carrier transport across it. For the conventional semiconductors, e.g. Si and GaAs, R C is known to approach near the quantum mechanical limit [117]. Also, there was an early-stage experimental report on R C in graphene devices by varying contact lengths, in which R C much larger than quantum limit was consistently obtained from various device configurations including 2PP and 4PP measurements [118]. However, 2D semiconducting materials with a sizable bandgap in the range of 0.5~2 eV, e.g., TMDCs, show very high R C >10 times that of the conventional semiconductor materials [117,119]. The large R C at the metal-semiconductor interface is attributable to the formation of Schottky barriers due to mid-gap Fermi level pinning arising from intrinsic material defects and processing conditions [36,120]. These Schottky barriers not only limit the ON current of the 2D FETs, but also determine their polarity [121,122]. Moreover, weak Van der Waals bonding between high work function metals such as gold (Au) and palladium (Pd) and 2D materials results in additional tunnel resistance and therefore higher R C . In addition, typical back-gated 2D devices allow simultaneous gating of contact and channel regions, which convolutes the underlying physics. Since R C in 2D devices is often much larger than R CH , the output and transfer characteristics of such FET devices represent contact properties rather than channel properties, as discussed in the conductivity section [61,[123][124][125][126][127]. This limits the performance of scaled 2D FETs and affects extraction of important device parameters such as fieldeffect mobility and V TH , as discussed in the previous sections. Thus, accurate estimation of R C is critical for understanding, improving, and benchmarking 2D devices.
In this section, we discuss the widely employed TLM technique used to estimate contact resistance in 2D FETs. We discuss the advantages and disadvantages of the method and highlight important considerations that should be taken into account when applying it to 2D materials. We also discuss the temperature-dependent Arrhenius method for extracting SBHs in 2D devices.

Transmission line method
The TLM/transfer length method is conventionally used to determine R C for metal contacts on bulk semiconductors, such as Si and Ge [78,128]. In this method, multiple devices are fabricated with TLM geometry (shown in figure 6(a)), where the channel length/spacing (denoted by L1, L2, etc) is varied between different contacts, while the contact length is kept constant. As shown in the inset of figure 6(a), R Total between any two contacts can be expressed as a linear combination of R C and the length-dependent R CH of the semiconductor in between the contacts, i.e.
which, using equation (5), can be further rewritten as Equation (22) is the fundamental relationship that is used to extract R C in TLM. Note that the term R C W is sometimes used to refer to R C in literature, where it represents width-normalized R C . Several 2-probe resistance measurements are made between an adjacent pair of contacts with different channel lengths and R Total is plotted as a function of channel length. Figure 6(b) shows a typical plot of R Total versus L from which R C can be extracted by finding the y-intercept using a linear fit. Other relevant parameters are also highlighted in the plot. Furthermore, low sourcedrain voltages (< 1 V) are recommended for accurate TLM to avoid Joule heating [103] and impact ionization [129] in channel 2D materials. Figure 6(c) shows a schematic of a typical TLM structure with a 2D material as the channel material and conventional back-gated geometry. Unlike bulk semiconductors, 2D materials generally do not conduct well without gating due to large R C . Thus, equation (22) needs to be modified to show the effect of global back gating, in which case both the channel and contact regions are modified simultaneously, i.e. Figure 6(d) illustrates the use of TLM to extract contact resistance for Au contacts on a bilayer MoS 2 where the channel length was varied from 200 to 1000 nm [130]. The measured total resistance (R Total W) was plotted as a function of channel length; the corresponding y-intercept provides the contact resistance (R C W). As discussed earlier, the contact resistance shows clear gate voltage dependence (highlighted by carrier density in the channel using equation (10)), as contact resistance decreases with an increase in gate voltage.

Transfer length and contact resistivity extraction
TLM also provides a simple way to study the scaling properties of contacts, which is crucial to determine the fundamental limits to scaling of 2D materialsbased FETs. As the channel length is scaled to enable better electrostatics and achieve higher device density, a large portion of total resistance corresponds to the contact resistance resulting in contact-dominated behavior of scaled devices. Using a distributed resistive network model for the contact region (figure 7(a)), analytical expressions for contact resistance can be obtained in terms of specific contact resistivity (ρ c ), sheet resistance under contact (R SK ), and transfer length (L T ):  Here, L C is the physical contact length and L T represents the current crowding at the metalsemiconductor junction and is defined as the effective length over which a majority of charge transfer/current transport occurs beginning at the edge of the junction (x = 0). Further insight can be gained by considering two limiting cases: Experimentally, these parameters are extracted from TLM by assuming that R SK = R SH and L C ≫ L T which allows us to extract L T by finding the xintercept of the curve of R Total versus L. Once L T is determined, ρ c can be determined by either equations (26) or (27) . Figures 7(b) and (c) show the extracted ρ c and L T values, respectively, for the device presented in figure 6(d).

Challenges with TLM
Over time, the TLM has become the most commonly employed method of determining R C and R SH in 2D materials-based devices due to the ease of device fab-rication and straightforward nature of the analysis. Moreover, the method is generally material agnostic; it does not require any prior knowledge of effective mass, dielectric constant, bandgap, etc.. Furthermore, the TLM has an advantage over 4PP as current transport is not disrupted by the presence of inner electrodes, which are used as voltage probes in typical 4probe measurements, as discussed in the previous sections [115,131,132]. However, a few potential pitfalls must be considered when applying TLM to 2D FET analysis: (i) Reliable TLM requires linear dependence of channel resistance on channel length and low spatial variation of contact resistance. Fabrication issues such as irregular device geometry due to non-patterned 2D flakes, inhomogeneous non-laminar current flow due to polymer contamination, lithography-induced damage, and unknown contributions from sample edges, can cause deviation from linear scaling of channel resistance and therefore result in erroneous contact resistance measurements [120]. (ii) TLM is also problematic when contact resistance is substantially higher than channel resistance, since a small amount of inter-device variation in contact resistance can cause large errors in the linear fit. Moreover, for Schottky contacts with non-linear I-V characteristics, R C becomes bias-dependent, which needs to be carefully considered when examining scaling behavior. The impact of non-linearity in the plot of R Total versus L is severe when the extracted transfer lengths are small. TLM is most successful at high back gate voltages, where the channel resistance is substantially larger than the contact resistance and it is clear that total resistance scales linearly with channel length [130]. (iii) Extracting transfer length and specific contact resistivity requires that R SK = R SH holds true, which is hard to justify for few-layer devices. Unlike conventional semiconductors, in which lateral transport occurs far (~10-100 nm) from the metal-semiconductor interface, transport in 2D materials occurs right at the interface and the material properties are substantially changed by the metal contacts (e.g. contact doping, fabrication-induced damage, and change in bandgap). Recent studies have shown significant differences in R SK and R SH , which calls for use of complementary methods for accurate extraction of L T , ρ C and R SK such as contact-end and cross-Kelvin bridge methods [133]. Future work on modeling and analysis of metal contacts on 2D materials needs to take this into consideration, helping to come up with accurate methods of extracting L T , ρ C and R SK .

Schottky barrier heights and Fermi level pinning
As discussed above, the large contact resistance in 2D devices can be attributed to the presence of Schottky junctions at the metal-2D semiconductor interfaces. Schottky junctions are characterized by SBHs, the relative values of which determine the current transport at the metal-semiconductor interface affecting the polarity, magnitude, and switching characteristics of the injected charge carriers. Figure 8(a) shows the SBH and conceptual band diagram of a metal-2D semiconductor interface. For an ideal metal-2D semiconductor junction, the SBH for n-type (ϕ Bn ) or ptype (ϕ Bp ) semiconductors is given by: For p -type: where ϕ m is the work function of a metal, χ is the electron affinity and E g is the 2D semiconductor bandgap. For such ideal systems, the SBH for electrons increases linearly with the metal work function, thus satisfying the Schottky-Mott rule as shown in figure 8(b). However, non-ideal states such as interface and gap states at the metal-semiconductor interface can cause severe deviation from the Schottky-Mott rule, making it difficult to control electron/hole SBH by varying the metal work function. Quantitatively, we can interpret this deviation by introducing a pinning factor (S) and charge neutrality level (CNL, ϕ CNL ) [134,135]: Here, S is defined as the slope S = ∂ϕBn ∂ϕm and can be calculated from the linear fit of ϕ Bn versus ϕ m plot. S = 1 represents an ideal metal-semiconductor interface whereas S = 0 represents almost no variation in SBH with a change in the metal work function, indicating a completely pinned interface at the charge neutrality level. The CNL for n-type can be estimated by the relation For S < 1, the semiconductor Fermi level is fixed near the CNL, which results in similar SBHs for different metal contacts, that is, 'Fermi level pinning' , as shown in figure 8(c). Fermi level pinning is often attributed to metal-induced gap states (MIGS) and defect-induced gap states (DIGS); however, the exact physical mechanism still remains an open question.

SBH extraction in 2D devices
Accurate extraction of SBH for any metal-2D semiconductor junction is essential for understanding the underlying physics of 2D devices and deducing the pinning factor and CNL. Generally, for bulk semiconductors, SBH is determined by fabricating Schottky diodes with different metal contacts; however, the large contact resistance at the metal-2D semiconductor interface makes it almost impossible to construct a proper Schottky diode . For this reason, the standard back-gated FET structure is more commonly used to extract SBH. The most prevalent method of determining SBH is the Arrhenius technique, which depends upon analyzing the temperature-dependent transfer or output characteristics of a back-gated 2D FET [34,61]. As shown in figure 9(a), current transport at the reverse-biased source junction of a 2D FET consists of two distinct components: (i) TE, where charge injection occurs over the barrier, and (ii, iii) tunneling transport, where the charge injection occurs through the barrier [136,137]. Tunneling transport can be further divided into thermionic field emission (TFE) and field emission (FE), where TFE denotes tunneling at an energy level higher than the source Fermi level and vice-versa. The relative contribution of these three components can be tuned by changing the applied gate bias. In the OFF state, the conduction band edge is higher than the actual SBH and is completely dominated by TE. In this regime, the current can be expressed as where ϕ B, eff (V GS ) is the gate voltage-dependent effective barrier height, is the modified Richardson constant, T is temperature and m * is the effective mass. In TE regime the current is strongly influenced by temperature and gate voltage due to its exponential dependence on these parameters. At a certain gate voltage, termed flat-band voltage (V FB ), the conduction band is perfectly aligned with the SBH at the source end, i.e. ϕ B, eff = ϕ Bn . For V GS > V FB , the tunneling current starts to dominate the overall current transport resulting in weaker temperature dependence. Thus, the actual barrier height can be extracted by identifying the effective barrier corresponding to the flat band voltage by analyzing the temperature-dependent transfer characteristics as shown in figure 9(b).
To extract the SBH, the temperature-dependent transfer characteristics are modeled with the thermionic current equation and replotted in an Arrhenius manner, shown in figure 9(c). From here, the effective barrier for current flow can be extracted by linearly fitting the Arrhenius curves, and can be expressed as Finally, as shown in figure 9(d), ϕ B,eff is plotted as a function of applied gate bias, and the actual SBH (ϕ Bn ) can be determined by identifying the gate voltage at which the curve of ϕ B,eff versus V GS deviates from its initial linear slope [34,61]. This gate voltage corresponds to the flat band voltage and the corresponding ϕ B,eff is recognized as ϕ Bn .

Challenges with the Arrhenius method of SBH extraction
Even though the Arrhenius method is widely used to extract SBH in 2D materials, its applicability is often questioned, because it requires several assumptions that are not generally satisfied in 2D devices. Here, we discuss the assumptions and their impact on the extracted SBH.  needs to show a clear transition from a thermionically dominated regime to a tunneling regime. However, this transition is often poorly defined in 2D devices due to the presence of non-idealities such as traps, non-homogenous doping due to surface contaminants, and van der Waals gap [138][139][140]. Moreover, for doped contacts, devices with thick (>2 nm) tunnel barriers, and few-layer (>5) devices, the assumption of pure thermionic current is difficult to verify due to the high tunneling current arising from the channel region underneath the contact [121,137,[141][142][143][144]. (ii) Weaker thermionic current at lower temperatures: More often than not, the Arrhenius method for SBH extraction in 2D materials involves temperatures below 100 K. At such temperatures, the thermionic component is substantially smaller than the usual leakage floor for any considerable SBH (ϕ Bn > 100 meV). For example, a contactdominated 2D FET with an SBH of 0.3 eV should result in a maximum thermionic current of 6 nA at flat band condition at 300 K, which is reduced to less than 1 fA for T < 77 K. Thus, it is extremely difficult to measure any thermionic current at low temperatures below 100 K. This means that the currents observed at such temperatures usually come from TFE or FE components that show weak temperature dependence [35,145] and therefore leading to erroneous SBH extraction.  is often used to mechanically exfoliate the 2D crystals and to transfer them to desirable substrate. But the polymer residues from PDMS stamp degrade the properties of transferred 2D materials via the formation of interfacial bubbles and wrinkles, which results in contaminants trapped at the interface between the substrate and the 2D material. To avoid and minimize the formation of residues at the interface during the stacking of such materials, alternative polymers, such as poly(propylene) carbonate, can be used [146]. Afterfabricating clean 2D MOS capacitors, the electrical measurements are conducted using a semiconductor parameter analyzer and an LCR meter. Care should be taken to ensure that the instruments are used with the lowest possible external impedance to minimize the parasitic capacitances. Although 2D materials have attracted a great deal of interest for advanced electronic applications due to their tunable bandgaps and high surface-to-volume ratios [147][148][149], the device performance is strongly affected by various 2D materials-related processing issues, such as the adsorption of H 2 O molecules from the environment, structural defects (vacancies, grain boundaries, dislocations, etc.), and the interface charge traps due to the interactions with dielectric materials (e.g. SiO 2 , Al 2 O 3 , HfO 2 ), which results in hysteresis in C-V (I-V) characteristics and degradation of electron and hole mobilities [150][151][152][153][154]. Zhu et al studied the interfacial properties of a HfO 2 /monolayer MoS 2 using C-V measurements and observed a double-hump feature in the C-V curve characterized to different gate voltages and frequencies, revealing traps in CVDgrown MoS 2 [155].
When working with 2D materials, due to their inert surfaces and the absence of dangling bonds, it is difficult to form a uniform and high-quality dielectric film, but this goal can be realized with proper surface functionalization [156,157]. Pretreatment of the 2D material surface (e.g. MoS 2 ) with oxygen plasma (O 2 ) or ultraviolet/ozone (UV/O 3 ) has been considered to enhance reactivity before high-k deposition to decrease the density of interface traps [158][159][160][161]. Previously, the quartz substrates were used for the fabrication of MIS capacitors to eliminate the parasitic capacitances between the metal pads and the substrates [162]; the C-V measurements of intermediate (WSe 2 , 1.2 eV) and narrow bandgap (black phosphorus,~0.3 eV) materials showed high-frequency (unipolar) and low-frequency (ambipolar) behavior, respectively.

Trapped charges in 2D materials
High-quality interfaces are crucial for highperformance 2D devices due to the large surfaceto-volume ratio of 2D materials [163][164][165][166]. Charges trapped in the interface, either positive or negative, originate from structurally induced defects at the gate-dielectric and dielectric-semiconductor interfaces that are capable of trapping and de-trapping charge carriers. The trapped charges in 2D device structures have been quantitatively analyzed using the capacitance and AC conductance measurements [155,163,167]. The density of interface traps can be determined by D it = ∂N it /∂E (cm −2 eV −1 ), where D it is the interface trap density, N it is the number of interface traps per unit area, and E is the energy. Figure 11(a) illustrates various origins of interface states in a high-k/MoS 2 /oxide structure [168].
Researchers have employed different methods for interface analysis and extracted different types of trapped charges, such as interface trapped charges and dielectric border trapped charges (or oxide charges) [158,161,[168][169][170]. For example, the band diagrams of the interface and border traps in HfO 2 /MoS 2 are shown in figure 11(b). The interface traps in MoS 2 bandgap dominate the C-V response in the depletion region, whereas the border traps in HfO 2 dominate in the accumulation region. The interface traps were investigated and the D it was extracted using frequency-dependent C-V measurements. The typical mid-gap D it at the SiO 2 gate dielectrics/Si interface is~10 10 cm −2 eV −1 , while the D it of the high-k dielectric/Si interface ranges from 10 11 to 10 12 cm −2 eV −1 [171]. One study examined the density distribution and dynamics of trap states in CVD-grown MoS 2 using capacitance measurements; the traps were shown to colonize the mid-gap (Type M trap) and band edge (Type B trap) regions (figure 11(c)) [155].
The influence of high interface state density D it on high-k/2D device characteristics has inspired extensive research on passivation of the high-k/2D interface to reduce D it [158][159][160][161]. D it most likely originates from the oxygen atoms that fill the sulfur vacancies during UV/O 3 functionalization treatment [160]. D it can be calculated with the conventional high-low frequency and multi-frequency methods using the following equations where C it is the capacitance of interface traps when all the traps react with AC signal at low frequency, and C LF and C HF are the capacitances measured at low and high frequencies, respectively [158,172]. Liu et al evaluated D it (10 13 cm −2 eV −1 ) in BP and WSe 2 -based MIS capacitors with Al 2 O 3 as a dielectric using the parallel conductance (G p ), which is extracted from capacitance and conductance measurements [162], given as where ω is the measurement frequency, C m is the capacitance of the device, and G m is the conductance. D it is calculated using [155,162,170], A significant decrease in D it was reported in a 2D hBN capacitor [162]. A low-temperature high-k deposition method led to the formation of traps associated with the dielectric known as border traps or nearinterfacial oxide traps [173]. These defects responded to a change in V GS in the gate dielectric at some distance from the interface, and therefore induce hysteresis in C-V measurements and are responsible for the frequency dispersion in the accumulation region.
There have also been studies that determined the density of border traps, as distinct from interface traps, using multi-frequency C-V characteristics of HfO 2 /MoS 2 and HfO 2 -Al 2 O 3 /MoS 2 top-gate stacks (figure 11(d)) [159,160].

Dielectric constants of 2D materials
The dielectric constant (ε) of a material is a fundamental electrostatic property that can be used to determine the capacitance, charge screening, and energy storage capacity of electronic devices. ε also plays a significant role in defining the active interactions that take place between charged particles in the material and contains information about the collective oscillations of electron gas, plasmons, excitons, and quasiparticle band structures [174,175]. The unique structure of 2D layered materials leads to anisotropic physical properties between the in-plane and out-of-plane directions, e.g. inhomogeneous dielectric strength and Coulomb interaction strength characterized by ε; this is unlike conventional isotropic materials such as silicon. The theoretical dielectric property of 2D materials such as graphene and MoS 2 is anisotropic owing to the different nature of bonds in the in-pane and out-of-plane directions (ε || and ε ⊥ ) [176][177][178]. Chen et al experimentally extracted the ε of MoS 2 from C-V measurements based on vertical MIS capacitor structures by using the following relation: where C min is the minimum capacitance measured at is the geometric capacitance, C BN is the geometric capacitance of hBN, and C in is the interlayer capacitance originating from the interlayer spacing between hBN and MoS 2 ( figure 12(a)) [179]. The ε as a function of the frequency (dielectric dispersion) of an hBN-based metal-insulatormetal (MIM) capacitor was demonstrated using time-domain reflectometry, where the ε of hBN decreases with an increase in frequency (figures 12(b) and (c)) [180]. The confined nature of atomically thin 2D crystals associated with the anisotropic dielectric screening has created long-term debates whether the dielectric constant truly represents the dielectric features of such low-dimensional systems. The ε values accounted for by both theoretical and experimental approaches vary by more than an order of magnitude [181]. Therefore, future developments that allow reliable and precise measurements of ε are needed.

Correlating device parameters to nanoscale material properties
Until this section, we have described the extraction of electrical parameters in the macroscopic transport of 2D devices, mainly focusing on FET structures. The device properties and performance are largely affected by both intrinsic (vacancies, anti-sites, substitutions, and grain boundaries in polycrystalline samples) and extrinsic (strains due to surface roughness The extracted ε of hBN as a function of applied frequency. ε remains stable at low frequencies (region I), whereas ε appears smaller at higher frequencies (region II) since the charges are allowed less time to orient themselves in the direction of the alternating field. The inset shows the dispersion characteristics of hBN flakes with different thicknesses [180]. and ripples, electron-hole puddles caused by charge impurities in a SiO 2 substrate, chemical adsorbates, polymer residues, etc) disorder [105]. For example, the grain boundary in a graphene device can affect the sheet resistance depending on the grain size according to the equation R SH = R G SH + ρGB lG , where R G SH is the average sheet resistance of the graphene grains, ρ GB is the average grain boundary resistivity, and l G is the average grain diameter [182]. The charge inhomogeneity induced by the SiO 2 substrate gives rise to carrier density fluctuation of up to~4.5 × 10 11 #/cm 2 at the sub-10 nanometer-scale length, as shown in figure 13(a) [183,184]. Mechanical and surface morphology (e.g. a crested substrate)-induced strain can engineer the local bandgap and mobility of 2D materials [185,186]. The influences of the disorder are very difficult to characterize solely by macroscopic transport unless nanoscale characterization techniques are utilized. In this section, we introduce various SPM techniques as supporting methods that enable local characterization of 2D materials correlated with the electrical parameters discussed in the previous sections. Detailed reviews on SPMs of nanomaterials and nanoelectronics are also provided in [187,188].
Kelvin probe force microscopy (KPFM) is a widely used SPM technique for nanomaterials and nanoelectronics. KPFM measures contact potential differences (V CPD ) to provide a quantitative measure of the work function difference between a sample and a probe tip. Figure 13(b) shows a schematic illustration of a KPFM measurement setup for graphene in which AC (V AC ) voltage generates oscillating electrical forces and DC (V DC ) voltage is applied to nullify the oscillating electric forces when V DC = V CPD [189,190]. The ∆V CPD (contact potential difference between electrode and sample) is used to obtain the work function of graphene, which is correlated with the Fermi energy (E F ) of graphene, a relative energy level with respect to the charge neutral point (CNP), as shown in figure 13(c). For graphene, the carrier density can be calculated using the following equa- where ℏ is the reduced Planck constant, and v F is the Fermi velocity of graphene [191,192]. A space charge region in a 2D semiconductor, which can be capacitively coupled with the air gap between the tip and sample, should be carefully considered for the measurements. Scanning capacitance microscopy, which measures local differential capacitance, allows for mapping of the carrier (doping) density and polarity profile, as well as the measurement of trapped charges and quantum capacitance [187,193,194].
Scanning tunneling microscopy (STM) has become a core technique for exploring the emergent physics of newly discovered materials. Since the discovery of 2D materials, this technique has been widely employed to locally map the atomic structure and electronic properties of various 2D materials [198][199][200]. Due to the wide application of STM, it has become an ideal tool to reveal the intrinsic atomic defects in 2D materials due to the low energy of the tunneling electron, which should leave the intrinsic defect structure to remain unaffected. , where m is the electron mass, ∆ϕ is the work function difference, ℏ is the reduced Planck constant and V b is the offset bias voltage. The STM imaging technique has been applied on various 2D materials, including graphene, black phosphorus and TMDCs, to reveal the electronic nature of intrinsic defects such as point defects, surface defects, dopant impurities, dislocation, and grain boundaries in bulk as well as in atomically thin monolayers [201][202][203][204][205][206]. An example of Figure 13. (a) Charge density map obtained from an STM dI/dV spectrum revealing charge fluctuation in graphene induced by a SiO2 substrate [183]. (b) Schematic illustration of KPFM measurement setup and (c) the extracted EF of graphene depending on the applied gate voltages [189]. (d) Schematic model of the working principle of the STM system. (e) Atomically resolved STM image of intrinsic tungsten (W) vacancies in multilayer WSe2. Inset shows an enlarged image. (f) Logarithmic dI/dV spectra for K/Wvac (red) and intrinsic Wvac (black) in multilayer WSe2 [195]. (g, h) Device schematic and resistance distribution in the CAFM measurement of the local conductivity of graphene on SiC due to differences in SiC topography [196]. (i) SBH measurement of metal-MoS2 contacts using the CAFM technique. The technique allows nanoscale mapping of SBH [197].
an STM image of WSe 2 is given in figure 13(e) and the corresponding dV/dI spectra showing the bandgap and defect-induced mid-gap states are depicted in figure 13(f).
Another important surface and electrical characterization methodology used in the field of 2D materials is conductive atomic force microscopy (CAFM). The lateral resolution of CAFM sits right between that of STM and conventional electrical probes. CAFM uses an ultrasharp conductive tip to apply electrical stress on the sample of interest. Typical CAFM systems can provide a lateral resolution of~10 nm, which is adequate for characterizing small channel (sub-100 nm) 2D devices. In the field of 2D materials, CAFM is generally used to map the lateral inhomogeneity in current transport that arises from several intrinsic and extrinsic factors, such as charge puddles, polymer residues, grain boundaries, and trap states. Giannazzo et al used CAFM to determine the substrate-dependent conductivity of epitaxial graphene on a SiC substrate [196]. The device structure is shown in figure 13(g); epitaxial graphene was grown on a 4H-SiC substrate using sublimation and then scanned with a Pt-coated Si tip. The local current in this device differs on the (1 12 n) facets compared to the (0 0 0 1) basal plane terraces, which indicates that the local conductivity of graphene can vary significantly depending on the facets of SiC, as shown in figure 13(h). Another novel application of CAFM is to investigate current transport at nanoscale metal-TMDC interfaces, as shown in figure 13(i) [197]. The CAFM tip makes small area contacts with TMDCs such as MoS 2 , the surface of which can be then scanned on the surface to produce a map of the nanoscale contact resistance and SBHs. Given the difficulty in fabricating high-quality contacts in 2D materials, CAFM offers a simpler means of characterizing current transport at the metal-2D material interface and has the additional advantage of producing area scans [207].

Outlook and conclusion
Electrical characterization methods for atomically thin 2D electronic devices must be revisited since the techniques used for conventional 3D-based semiconductors do not properly model 2D devices. Also, challenges remain concerning the characterization of the electrical properties of anisotropic 2D layered materials, which show different carrier transport behavior between the in-plane and out-of-plane directions due to the tunnel barrier formed only along the out-of-plane direction. Electrical characterization techniques unique to surface-dominant 2D semiconductors with layered materials need to be developed, which are separate from the techniques used for conventional semiconductors. For example, electrical response-based surface characterization techniques such as SPMs can detect localized charge distribution, doping density, defects, SBHs, mid-gap states, and bandgap, as discussed in the last section. These methods can also be advantageous in analyzing charge traps, which give rise to Fermi level pinning and leaky device performance. However, most SPMs do not provide straightforward information about the correlation between localized effects such as charge puddles and macroscopic electrical quantities such as mobilities and contact resistances; thus, collaborative efforts involving material and device engineers are needed.
One of the challenges in ensuring the reliability of electrical contacts to 2D semiconductors is the Schottky barrier with the metal contact, which is unlike the conventional contacts on highly doped bulk semiconductors. We find that the TLM used to measure contact resistance for Ohmic contact devices brings about large errors for some 2D devices showing Schottky current transport behavior. It is worth mentioning that C-V measurements have been significantly limited in characterizing 2D devices compared to the conventional Si devices, despite the fact that these can provide valuable information on the device properties such as interfaces, semiconductor junctions, dielectric characteristics, as well as charge traps. Although it is difficult to conduct C-V measurements for 2D devices fabricated with mechanically exfoliated smallsized 2D materials, it is clear that these methods will accelerate the development of future 2D devices, particularly when large-scale 2D materials are more widely available. Last but not least, the reliability of the electrical characterization of 2D devices needs to be ensured, particularly given the presence of nonuniform interfaces and surfaces that are affected by device process-generated residues and air ambience.