Scratching lithography for wafer-scale MoS2 monolayers

Monolayer MoS2 is an emerging two-dimensional (2D) semiconductor with promise on novel electronics and optoelectronics. Standard micro-fabrication techniques such as lithography and etching are usually involved to pattern such materials for devices but usually face great challenges on yielding clean structures without edge, surface and interface contaminations induced during the fabrication process. Here a direct writing patterning approach for wafer-scale MoS2 monolayers is reported. By controllable scratching by a tip, wafer-scale monolayer MoS2 films on various substrates are patterned in an ultra-clean manner. MoS2 field effect transistors fabricated from this scratching lithography show excellent performances, evidenced from a room-temperature on–off ratio exceeding 1010 and a high field-effect mobility of 50.7 cm2 V−1 s−1, due to the cleanness of as-fabricated devices. Such scratching approach can be also applied to other 2D materials, thus providing an alternate patterning strategy to 2D-materials based devices.


Introduction
Monolayer 2H-phase MoS 2 , a representative in the two-dimensional (2D) transition metal dichalcogenides (TMDs) family, has recently attracted extensive attentions due to its outstanding physical and chemical properties [1][2][3][4][5][6]. Such a 2D semiconductor could offer opportunities in many application fields including electronics, optics, optoelectronics and catalysis [7][8][9][10][11][12][13][14][15][16]. Usually in MoS 2 -based devices processing, standard micro-fabrications, including lithography and reactive ion etching (RIE), are involved. In these fabrication processes, photoresists or electron beam lithography (EBL) resists on the surfaces of these 2D materials are very hard to be removed and harsh reactive ion etching could also cause edge passivations [17,18]. It is well known that 2D materials are very surface-and interface-sensitive, thus such resists residues or passivations are the main source of quality degradation, acting as additional scattering centers for charge transport [19]. Therefore, a clean microfabrication process is needed in order to explore the intrinsic properties of such monolayers and improve their device performance in many application environments.
Beyond standard micro-fabrications mentioned above, some alternate fabrication approaches, such as the oxidation nanolithography [20][21][22], peeling-off patterning by gold films [23], laser or argon plasma thinning and patterning [24][25][26], and micro-molding in capillaries [27], etc, have also been developed for MoS 2 . However, due to the chemical reaction process or direct contact of other materials to MoS 2 inevitably involved in these fabrication processes, achieving clean MoS 2 patterns remains a great challenge. Direct nanolithography of 2D materials by atomic force microcopy (AFM) tips or nanoprobes have also been reported previously [28][29][30][31][32][33], however, the methods are not suitable for wafer-scale patterning.
Aiming to a simple, clean and scalable patterning of MoS 2 monolayers on certain substrates, we here developed a direct writing approach named scratching lithography (SL). In this approach, a metal tip is used to engrave patterns directly by scratching MoS 2 off within the designed path while keeping the other regions intact. By controlling the tip-scanning path, we are able to achieve various MoS 2 patterns with micro-scale precision. We also show that improved electrical performance can be achieved for SL-patterned MoS 2 field effect transistors (FETs), benefiting from the clean and high-quality as-produced structures.

Results and discussions
In this work, wafer-scale highly-oriented monolayer MoS 2 films epitaxially grown on sapphire were used as raw materials for direct patterning [34]. Please see Methods section for detailed materials growth and also figure S1 (available online at https://stacks.iop.org/2DM/7/045028/mmedia) for a typical sample. Figure 1(a) shows our experimental setup installed inside a glovebox. Note that bended tips instead of straight ones were used in order to achieve larger and smoother contact between tip and sample for better reliability and less damages to the underneath substrates. Samples were mounted on a motorized positioning stage, while a metal (tungsten at the present case) tip was mounted on another motorized positioning stage and away from the sample surface. Different from the silicon tips for AFM, tungsten has high hardness, so the tips show a remarkable endurance without crack or deformation. Controlled by stepping motors, both stages can move along X-, Y-and Z-direction with 1 µm precision and 50 mm s −1 maximal speed. Sample stages can also rotate and tilt freely with 0.01 • precision. In addition, the experimental setup is simple, cost-effective and is suitable to pattern air-degradation sensitive 2D materials such as black phosphorus, magnetic materials and superconducting thin films.
The schematic process of SL is shown in figure 1(b). First, we adjust the stage levelling then slowly lowered the tip until it approaches the sample surface for a direct contact. Before scratching, we tune the tip-to-sample force by the engage distance and the force is estimated to be at the range of 5-10 mN normally. Then, we move either the tip or the sample to start scratching along any predesigned paths. Because of the weak binding force between MoS 2 and substrates, it is easy to fully tear and scratch MoS 2 off within the scanning paths. It is worth noting that the stability and levelness of positioning stages are two major factors for clean, straight and sharp scratched patterns; while the tip's moving speed has no obvious influence on it. The minimum line width of the scratched ribbons or grooves depends on both the precision of stepping motors and the tip-to-sample contact area (about 10 µm 2 at the present case). After scratching, various patterns of monolayer MoS 2 at a wafer-scale can be achieved. Please also see the supplementary video 1 & 2 for a better illustration. Figure 1(c) shows a 2 inch MoS 2 /sapphire sample after series of line scratching. After scratching, most of the MoS 2 residues accumulated at the end of paths on the samples (refer to upper image of figure 1(d)), while the residues were hardly observed on the tip. Therefore it is no need to clean the tip during the scratching process unless a block of residues stick on it by accident. After every runs of experiments, we sonicated the tip in alcohol for cleaning. These residues on the samples can be completely removed by post gentle sonication in alcohol (refer to lower image of figure 1(d)), as confirmed from the barely unchanged Raman and photoluminescence (PL) spectra on the MoS 2 sample areas and no signals on the scratched areas (figures 1(e) & (f)). Moreover, the sonication makes no obvious difference on the quality of monolayer MoS 2 . Please see figure S2 for more detailed information. Combining the scratching and sonication process, we thus are able to obtain various clean MoS 2 patterns, such as ribbons, squares, chessboards and numbers as shown in figure 1(g). Note that monolayer MoS 2 has strong fluorescence intensity due to its direct bandgap [3]. The high-contrast fluorescence microscopy image shown in figure 1(h) confirms again the cleanness and preserved optical quality of as-fabricated structures. The scratched patterns possess clean surfaces and sharp edges as shown in AFM image (figure 1(i)). A minimum line width of 1 micron, which is comparable to the accuracy of a standard ultraviolet (UV)-lithography, can be achieved reliably (refer to figure S3 for more details). Figure 1(j) shows the distribution of channel width for SL patterned 1 µm ribbons and over 35% ribbons are measured with the width between 0.95 µm and 1.05 µm. Actually, the precision could be much higher if improving the precision of stepping motors or including a feedback for tip-engaging to reduce the contact area between the tip and sample.
Based on these scratched monolayer MoS 2 microstructures, we thus fabricated field effect transistors to demonstrate the potential of such clean structures. In order to avoid a secondary contamination, we developed a lithography-free device fabrication process as shown in figure 2(a). In this process, monolayer MoS 2 films were firstly transferred from sapphire substrates onto SiO 2 /Si substrates via a water-assisted transfer method [34]. SL was then followed to separate and define the MoS 2 channels. Gold electrodes with a thickness of 40 nm were pre-deposited on poly propylene carbonate (PPC) by an electron beam evaporation system with the aid of a shadow mask. Finally, the electrodes were aligned and dry-transferred from PPC to the MoS 2 channels on SiO 2 /Si substrates. Please see more detailed description of fabrication process in supporting information (figures S4-S6). Note that the whole process is lithography-free without any photoresist. Here we choose the transferred electrodes, because direct evaporation of metal films on MoS 2 could cause structure damages, due to the bombardment from high energy metal atoms and clusters, thus degrade the contact quality [35]. This lithography-free device fabrication process might be also applicable to other fragile and contaminationsensitive materials like biologic or organic materials.
Next, we measured the electrical performance of these as-fabricated devices in a high vacuum fourprobe station system. Figures 2(b)-(c) show the transfer and output characteristics of a typical FET with both the channel length L and width W of 27 µm. From the output characteristics, it shows that the source-drain current I ds changes linearly with the bias voltage V ds when varying the gate voltage V gs from − 30 V to 60 V, suggesting nearly ohmic contacts. In the transfer characteristics of the same transistor, a typical n-type behavior and high on-off ratio exceeding 10 10 can be clearly seen. According to the equation where µ is the field-effect mobility and C i is the capacitance of the dielectric layer per unit area [8], we obtained µ = 50.7 cm 2 V −1 s −1 at the room temperature. Note that the SL patterned device shows excellent electrical performances, for example higher current onoff ratio and field-effect mobility than previous works [9,34,36].
We also fabricated two types of control samples for a better comparison. In type-I devices, monolayer MoS 2 was patterned by UV-lithography and RIE; in the following, electrodes were deposited by electron beam evaporation. In type-II devices, monolayer MoS 2 was patterned by UV-lithography and RIE; and electrodes were transferred instead of direct deposition. The transfer and output characteristic curves of  figure S7(a)-S7(d), respectively. The output curves of control samples show ohmic contacts but lower source-drain current compared with the SL-patterned transistor. Lower on-off ratios of ∼10 7 (at a bias of 1 V) can be seen for both control devices. Figure 2(d) shows transfer characteristic curves at V ds = 1 V of three different types of devices with same L and W. Note that we shifted the threshold voltage of all curves to 0 V for better comparisons. We can see clearly that the SL-patterned transistor shows higher on-state current and lower off-state current, leading to a higher onoff ratio and field-effect mobility. The two types of control samples show similar electrical properties and the field-effect mobility of them are much lower, i.e. 13.05 cm 2 V −1 s −1 and 17.40 cm 2 V −1 s −1 for type I and type II, respectively. Larger hysteresis can also be seen in figure S8 in control devices, due to the presence of surface or edge contaminations, which act as charge-trapping centers [37].
We attribute the excellent electrical performance of SL-patterned FETs to the clean surfaces and interfaces of our devices. To verify this point of view, we characterized SL-and UV-patterned MoS 2 strips by AFM. From the AFM images shown in figure 3(a), we can see that the SL-patterned samples are much cleaner at surfaces; while a plenty of residues/contaminations and structure deformations can be seen in the UV-patterned samples, even after a long period of thermal annealing or rinsing in acetone. In spite of the channel, the excellent electrical performance of SL-patterned FETs may also be benefited from the ultra-clean contact region and transferred electrodes. Contact resistance (R c ) and Schottky barrier height (SBH) were measured on many devices. In R c measurements, we fabricated MoS 2 FETs with transmission line structure (inset of figure 3(b)) and estimated R c according to the transfer length method (TLM) [38]. Figure 3(b) gives the comparison of R c between the SL-patterned and UVpatterned FETs (type I), and the resulted R c is 63.2 kΩ · µm and 688.8 kΩ · µm, respectively. SBH of these two contacts were extracted from the Arrhenius plots show in figure S9 [39,40]. Figure 3(c) shows the resulted SBH = 28.8/50.7 meV for the SL-/UV-patterned MoS 2 FETs. Near one order of magnitude lowered R c and almost halved Schottky barrier height in such clean devices contribute to their high performances compared with those of the traditional UV-patterned devices in no doubt. Figure 3(d) shows a 5 × 5 array of SL-patterned FETs. Corresponding spatial distribution of fieldeffect mobility of this array is shown in figure 3(e), SL is also applicable to other 2D materials or even thick films. Similarly, SL shows promise in the fabrication of 2D material based p-n junctions or superlattices. In figure S11, we also tested MoS 2 or nano-graphene films on SiO 2 /Si, sapphire and flexible polyethylene terephthalate (PET) substrates. All fabricated structures are of preserved quality with ultra-clean surfaces and sharp edges, suggesting the versatility of this approach.

Conclusion
In this work, we developed a simple, clean and scalable approach to pattern monolayer MoS 2 . This SL approach offers a minimum line width of ∼1µm. Clean MoS 2 FETs were fabricated by this approach and show improved electrical properties than those of lithography and etching defined devices, revealing the advances of this new approach. This approach is also applicable to other 2D materials on various substrates, thus paving a way towards facile fabrication of large-scale high-performance 2D-materials based electronic or optoelectronic devices.

Wafer-scale MoS 2 growth
The growth was carried out in a three-temperaturezone chemical vapor deposition (CVD) system with the schematic shown in figure S1(a). S (Alfa Aesar, 99.5%, 5 g) and MoO 3 (Alfa Aesar, 99.999%, 10 mg) powders were loaded in two inner quartz tubes at zone I and zone II, respectively, as reaction sources. Pre-annealed 2 inch sapphire wafers (C-plane off M-axis, thickness: 430 µm) were used as substrates and placed at high-temperature zone III. During the growth process, temperatures at zone-I, zone-II and zone-II were 130 • C, 530 • C and 900 • C, respectively; and Ar (200 sccm) and Ar/O 2 (75 sccm/3.5 sccm) were flowed through the inner tubes for the S-source and MoO 3 -source, respectively, as carrying gases. Here, O 2 can prevent the sulfurization of MoO 3 thus guarantee a continuous evaporation and reduce the nucleation density as well. The pressure of the growth chamber was kept at ∼ 1 Torr, and the whole growth process lasted for 45 min.

Characterizations of samples
AFM imaging of SL-patterned samples and UVpatterned samples were performed by Veeco Multimode III system under the tapping mode. Raman and PL spectra were performed by Horiba Jobin Yvon LabRAM HR-Evolution Raman system with a 532 nm laser excitation under a power of 500 µW and the integral time were 5 s and 10 s, respectively. Fluorescence microscopy images were collected by Olympus confocal fv3000 microscope with an exposure time of 100 ms.

Device fabrications and measurements
Control samples were fabricated by the standard micro-fabrication process. The transferred monolayer MoS 2 samples were first patterned into ribbons by UV lithography (Suss MicroTec Gmbh MA6) and RIE (Oxford Instruments Plasma 80 plus). Gold electrodes were patterned by a second UV lithography process and deposited by electron beam evaporation with thickness of 40 nm. Electrical measurements on all the devices were carried out in a high-vacuum (1 × 10 −6 mbar) four-probe-station system by an Agilent 4156 C semiconductor parameter analyzer.

Preparation of other film materials
Monolayer MoS 2 films on SiO 2 /Si substrates were grown by CVD with a deposition temperature of 750 • C. Bilayer MoS 2 films SiO 2 /Si were transferred layer-by-layer from sapphire substrates. Au films on sapphire were deposited by electron beam evaporation. Nano-graphene on SiO 2 /Si was grown by plasma-enhanced CVD (CH 4 as source) with a deposition temperature of 560 • C. Al 2 O 3 films on Si substrates were fabricated by standard atomic layer deposition. PMMA films on SiO 2 /Si were fabricated by spin-coating with a rotate speed of 4000 r min −1 and followed by a heating process at 180 • C. Sn films on SiO 2 /Si were prepared by squeegee method at 260 • C. Exfoliated graphene, BN and MoS 2 films were cleaved from bulk materials by Scotch tape and transferred onto SiO 2 /Si substrates.