The role of charge trapping in MoS2/SiO2 and MoS2/hBN field-effect transistors

The commonly observed hysteresis in the transfer characteristics of MoS2 transistors is typically associated with charge traps in the gate insulator. Since in Si technologies such traps can lead to severe reliability issues, we perform a combined study of both the hysteresis as well as the arguably most important reliability issue, the bias-temperature instability. We use single-layer MoS2 FETs with SiO2 and hBN insulators and demonstrate that both phenomena are indeed due to traps in the gate insulator with time constants distributed over wide timescales, where the faster ones lead to hysteresis and the slower ones to bias-temperature instabilities. Our data show that the use of hBN as a gate insulator considerably reduces the number of accessible slow traps and thus improves the reliability. However, the reliability of hBN insulators deteriorates with increasing temperature due to the thermally activated nature of charge trapping.


Configuration and basic characteristics of our MoS 2 /SiO 2 and MoS 2 /hBN FETs
In Figure S1 we show the schematic layout of our MoS 2 FETs with SiO 2 and hBN insulators. In our MoS 2 /SiO 2 devices ( Figure S1(left)) a MoS 2 channel is placed on top of a 90 nm thick SiO 2 layer. In the second set of transistors, MoS 2 is sandwiched between two 90 nm thick hBN layers ( Figure S1(right)). In order to allow for a more detailed analysis of hBN vs. SiO 2 , we added an additional Ti/Au gate between the hBN and the SiO 2 layer. Thus, we can operate these devices either with an hBN gate insulator by contacting the Ti/Au plate or with an hBN/SiO 2 stack through the highly doped Si substrate.
For the primary check of the performance of our devices we measured their gate transfer (I d -V g ) and output (I d -V d ) characteristics. The results obtained for MoS 2 /SiO 2 and MoS 2 /hBN FETs are shown in Figure S2. Similarly to Refs. [1,2], the gate transfer characteristics of our transistors exhibit the behaviour typical for n-FETs with some hysteresis. The latter is associated with charging/discharging of fast traps. Consistent with literature results [2], for the devices with hBN the hysteresis is significantly smaller than for their counterparts with SiO 2 . At the same time, the output characteristics of both types of our devices show a quasi-linear behaviour, which is a consequence of the narrow drain voltage intervals [1,2]. The estimated field-effect mobility can reach 1 cm 2 /Vs for MoS 2 /SiO 2 FETs and 3 cm 2 /Vs for MoS 2 /hBN devices (cf. Ref. [3]). These Figure S1. Schematic layout of our two single-layer MoS 2 FETs with SiO 2 (left) and hBN (right). The insulator thickness is around 90 nm for both SiO 2 and hBN. The MoS 2 /hBN device has two gate contacts: one through the highly doped Si substrate and the other through a Ti/Au pad in between the SiO 2 and hBN layers. This allows us to use either the hBN or the hBN/SiO 2 stack as a gate insulator. The drain and source contacts are made of Ti/Au. Figure S2. The gate transfer (I d -V g ) and output (I d -V d ) characteristics of our MoS 2 FETs with SiO 2 (a) and pure hBN (b). The transfer characteristics show some hysteresis due to charging/discharging of fast traps, while for MoS 2 /hBN devices the hysteresis is considerably smaller. The output characteristics show a quasi-linear current increase within the narrow V d range used.
rather low values are most likely because of the considerable Schottky barrier between MoS 2 and Ti/Au, which leads to a large contact resistance. At the same time, the on/off ratio measured with high current resolution can exceed 10 5 .

Impact of interface traps on the performance of MoS 2 /SiO 2 FETs
As shown in Figure S3, for very high sweep frequencies our MoS 2 /SiO 2 devices exhibit some instability below V th . Based on the results of our TCAD simulations we ascribe this behaviour to the impact of interface traps. Furthermore, the transfer characteristics measured using extremely fast sweeps can be matched reasonably well with the TCAD results by assuming a very large density of interface traps N it = 5×10 14 cm −2 . Otherwise, Figure S3. The I d -V g characteristic measured for our MoS 2 /SiO 2 device using fast sweep rates does not contain any hysteresis associated with oxide traps. However, there is a strong instability below V th . This phenomenon can be qualitatively reproduced in our TCAD simulations, which suggest that this effect is likely associated with interface traps.
according to standard Shockley-Read-Hall theory, interface states are too fast to contribute to the hysteresis [4].

Evolution of the hysteresis in MoS 2 /SiO 2 FETs
The evolution of the hysteresis width for our MoS 2 /SiO 2 devices at different sweep rates S versus time in vacuum and temperature is shown in Figure S4. During the first 10 days at T = 25 • C, a large hysteresis was observed for small S, which was reduced after some time in vacuum. At the same time, no significant hysteresis was present for fast sweeps. However, when increasing the temperature to 85 • C, ∆V H measured with small S was significantly reduced, while a considerable hysteresis appeared for large S. Back at 25 • C, some increase in hysteresis width measured with small S is pronounced. However, ∆V H did not return to its initial values. Figure S4. Evolution of ∆V H measured for the MoS 2 /SiO 2 device versus time in the vacuum. During the first days at T = 25 • C, a hysteresis is only observed for slow sweeps and decreases with time. At T = 85 • C, ∆V H for small S decreases abruptly. However, the hysteresis suddenly becomes pronounced at larger S. Finally, when T is returned back to 25 • C, the slow sweep ∆V H slightly increases, while nearly no change is seen for fast sweeps. This means that a number of slower traps were annealed at the higher temperature. In Figure S5 we show the schematic ∆V H (f ) dependences for MoS 2 /SiO 2 FETs at different temperatures. The results of our measurements are sketched using solid lines for T = 25 • C (blue) and T = 85 • C (red), while the dashed line gives the ∆V H (f ) behaviour at T = 85 • C which is predicted by our Minimos-NT simulations. The deviation of our results measured at T = 85 • C from qualitative predictions means that in our MoS 2 /SiO 2 FETs the hysteresis is not only due to oxide traps, but also due to trapping sites (e.g. water molecules) situated on top of the non-covered MoS 2 surface. Since the latter defects become annealed at higher temperature, we observe a decreased contribution of slower traps. At the same time, an increasing contribution of faster traps fully agrees with the ∆V H (f ) maximum shift and thermal activation. Figure S6 shows an example of the I d -V g characteristics measured for MoS 2 /hBN/SiO 2 and MoS 2 /hBN FETs using different sweep rates at T = 25 • C and T = 85 • C.

Comparison of the hysteresis behaviour for different gate insulators
In Figure S7a we compare our findings for MoS 2 FETs with different gate insulators. While for MoS 2 /SiO 2 FETs the hysteresis is mostly dominated by slower traps, for MoS 2 /hBN/SiO 2 devices an increased contribution of faster traps is observed. Hence, in the latter case the maximum of ∆V H lies within our experimental range. At the same time, in MoS 2 /hBN devices the hysteresis is purely related to ultra-fast traps. In all cases the ∆V H (f ) dependence is shifted toward higher f at higher temperatures, which agrees with theory. In Figure S7b we compare the maximum hysteresis widths (vacuum, T = 25 • C) obtained within this work with the results from Refs. [1,3,5]. In order to account for the differences in the sweep ranges and insulator thicknesses used for different devices, we normalize ∆V H by the factor K = (V gmax -V gmin )/d ox . Although the hysteresis strongly depends on the temperature, the sweep rate and the gate bias sweep range, we can conclude that our MoS 2 /SiO 2 and MoS 2 /hBN FETs exhibit the best hysteresis stability.

PBTI in MoS 2 /SiO 2 FETs at different V g
Initially we examined our MoS 2 /SiO 2 FETs by applying subsequent PBTI stresses with a stress time of t s = 10 ks and increasing V g . The resulting evolution of the I d -V g characterestics is shown in Figure S8a. Clearly, the degradation is recoverable, while being more pronounced for larger V g . This agrees with our qualitative predictions, which suggests that for larger positive V g the Fermi level lies higher and hence the number of defects which are able to emit a hole during the stress is larger. As shown in Figure S8b, the relative ∆V th remaining after t r = 10 ks decreases from 85 % of the initially measured ∆V th for V g = 5 V toward 60 % for stronger stresses, i.e. for larger V g the degradation is stronger but more recoverable. This behaviour is similar to what is observed in Si technologies [6]. The resulting recovery traces for the threshold voltage shift ∆V th . The degradation is partially recoverable and strongly increases with increasing stress V g . While for the stress with V g = 5 V the relative ∆V th remaining after a relaxation time t r = 10 ks is around 85% of the initially measured value, for stronger stresses it is close to 60% (inset). Note that the measurements of the full I d -V g sweep at each recovery point introduce a delay of about 3 s.
The Role of Charge Trapping in MoS 2 /SiO 2 and MoS 2 /hBN Field-Effect Transistors 7

NBTI in MoS 2 /SiO 2 FETs
The NBTI degradation/recovery results obtained for our MoS 2 /SiO 2 FETs are provided in Figure S9. While V th is shifted in the opposite direction compared to PBTI, the observed shifts are larger than for PBTI. The latter is because most of the defects are neutral in the initial equilibrium. Hence, trapping of holes during NBTI stress is more favorable compared to their emission during PBTI stress. Nevertheless, the recovery traces can be well fitted by the universal relaxation model, which confirms the similarity between NBTI and PBTI. Moreover, the temperature dependence of NBTI degradation is similar to PBTI. Namely, stronger shifts and faster recovery are observed at T = 85 • C. Figure S9. (a) Degradation of the gate transfer characteristics of the MoS 2 /SiO 2 FET after subsequent NBTI stresses with V g = −20 V and increasing t s at T = 25 • C (left) and T = 85 • C (right). The observed threshold voltage shifts are significantly larger than for PBTI, while the recovery is also stronger. (b) Similarly to PBTI, the recovery traces for ∆V th can be reasonably well fitted using the universal relaxation model. The temperature dependence of the degradation/recovery dynamics is also similar to PBTI. Namely, larger shifts and stronger recovery are observed at higher T , which is also the case for Si technologies. (c) The normalized recovery again follows the universal relaxation relation.

Extrapolation of initial BTI shifts
The use of the universal relaxation model [7] allows us to extrapolate initial shifts ∆V th (t r = 0) for both MoS 2 /SiO 2 and MoS 2 /hBN FETs. The results provided in Figure S10 show that ∆V th (t r = 0) follow a power law dependence versus t s , while the exponent of this dependence becomes larger at T = 85 • C. The latter further confirms that, similarly to Si technologies, carrier trapping in our MoS 2 FETs is thermally activated [4].  Figure S11a, a temperature increase of up to T = 165 • C leads to a significant increase of the drain current measured for our MoS 2 /SiO 2 FET. However, when after 10 days the temperature is returned back to 25 • C, the drain current decreases insignificantly and does not return to its initial value ( Figure S11b). At the same time, baking of MoS 2 /SiO 2 FET at T = 165 • C causes a non-recoverable shift of the threshold voltage toward large negative values ( Figure S11c), which means that a number of traps become charged. Nevertheless, the mobility and on current after baking become considerably larger ( Figure S11d).   The typical ∆V th shifts are larger than those measured for lower temperatures. For example, some NBTI degradation can be observed already after t s = 0.1 ks stress. At the same time, the recovery traces can again be well fitted using the universal relaxation model as the normalized recovery is universal (c).
As for the MoS 2 /hBN device, it exhibits only an insignificant shift of the threshold voltage ( Figure S12) after 10 days at T = 165 • C, while on current and mobility become larger. This further confirms that MoS 2 /hBN FETs are more stable than their MoS 2 /SiO 2 counterparts.
In addition, we have analyzed PBTI and NBTI for MoS 2 /hBN FETs at T = 165 • C. As shown in Figure S13, the observed threshold voltage shifts are larger compared to those discussed in the manuscript for T = 25 • C and T = 85 • C. Nevertheless, in both cases the recovery can be well fitted using the universal relaxation model. Interestingly, NBTI is again considerably stronger than PBTI.